\n

MT0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x5C byte (0x0)
mem_usage : registers
protection : not protected

Registers

EN

TBFFCR

TBST

TBIM

TBUC

RG0

RG1

CP0

CP1

IGCR

IGRESTA

IGST

IGICR

RUN

IGOCR

IGRG2

IGRG3

IGRG4

IGEMGCR

IGEMGST

IGTRG

TBCR

TBMOD


EN

MPT Enable Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTMODE MTHALT MTEN

MTMODE : MTMODE
bits : 0 - 0 (1 bit)
access : read-write

MTHALT : MTHALT
bits : 6 - 6 (1 bit)
access : read-write

MTEN : MTEN
bits : 7 - 7 (1 bit)
access : read-write


TBFFCR

MPT Flip-Flop Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TBFFCR TBFFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTTBFF0C MTTBE0T1 MTTBE1T1 MTTBC0T1 MTTBC1T1

MTTBFF0C : MTTBFF0C
bits : 0 - 1 (2 bit)
access : read-write

MTTBE0T1 : MTTBE0T1
bits : 2 - 2 (1 bit)
access : read-write

MTTBE1T1 : MTTBE1T1
bits : 3 - 3 (1 bit)
access : read-write

MTTBC0T1 : MTTBC0T1
bits : 4 - 4 (1 bit)
access : read-write

MTTBC1T1 : MTTBC1T1
bits : 5 - 5 (1 bit)
access : read-write


TBST

MPT Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TBST TBST read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTTBINTTB0 MTTBINTTB1 MTTBINTTBOF

MTTBINTTB0 : MTTBINTTB0
bits : 0 - 0 (1 bit)
access : read-only

MTTBINTTB1 : MTTBINTTB1
bits : 1 - 1 (1 bit)
access : read-only

MTTBINTTBOF : MTTBINTTBOF
bits : 2 - 2 (1 bit)
access : read-only


TBIM

MPT Interrupt Mask Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TBIM TBIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTTBIM0 MTTBIM1 MTTBIMOF

MTTBIM0 : MTTBIM0
bits : 0 - 0 (1 bit)
access : read-write

MTTBIM1 : MTTBIM1
bits : 1 - 1 (1 bit)
access : read-write

MTTBIMOF : MTTBIMOF
bits : 2 - 2 (1 bit)
access : read-write


TBUC

MPT Read Capture Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TBUC TBUC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTUC

MTUC : MTUC
bits : 0 - 15 (16 bit)
access : read-only


RG0

MPT RG0 Timer Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RG0 RG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTRG0

MTRG0 : MTRG0
bits : 0 - 15 (16 bit)
access : read-write


RG1

MPT RG1 Timer Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RG1 RG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTRG1

MTRG1 : MTRG1
bits : 0 - 15 (16 bit)
access : read-write


CP0

MPT CP0 Capture Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CP0 CP0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTCP0

MTCP0 : MTCP0
bits : 0 - 15 (16 bit)
access : read-only


CP1

MPT CP1 Capture Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CP1 CP1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTCP1

MTCP1 : MTCP1
bits : 0 - 15 (16 bit)
access : read-only


IGCR

IGBT Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IGCR IGCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IGCLK IGSTA IGSTP IGSNGL IGPRD IGIDIS

IGCLK : IGCLK
bits : 0 - 1 (2 bit)
access : read-write

IGSTA : IGSTA
bits : 2 - 3 (2 bit)
access : read-write

IGSTP : IGSTP
bits : 4 - 5 (2 bit)
access : read-write

IGSNGL : IGSNGL
bits : 6 - 6 (1 bit)
access : read-write

IGPRD : IGPRD
bits : 8 - 9 (2 bit)
access : read-write

IGIDIS : IGIDIS
bits : 10 - 10 (1 bit)
access : read-write


IGRESTA

IGBT Timer Restart Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IGRESTA IGRESTA write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IGRESTA

IGRESTA : IGRESTA
bits : 0 - 0 (1 bit)
access : write-only


IGST

IGBT Timer Status Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IGST IGST read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IGST

IGST : IGST
bits : 0 - 0 (1 bit)
access : read-only


IGICR

IGBT Input Control Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IGICR IGICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IGNCSEL IGTRGSEL IGTRGM

IGNCSEL : IGNCSEL
bits : 0 - 3 (4 bit)
access : read-write

IGTRGSEL : IGTRGSEL
bits : 6 - 6 (1 bit)
access : read-write

IGTRGM : IGTRGM
bits : 7 - 7 (1 bit)
access : read-write


RUN

MPT RUN Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RUN RUN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTRUN MTPRUN

MTRUN : MTRUN
bits : 0 - 0 (1 bit)
access : read-write

MTPRUN : MTPRUN
bits : 2 - 2 (1 bit)
access : read-write


IGOCR

IGBT Output Control Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IGOCR IGOCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IGOEN0 IGOEN1 IGPOL0 IGPOL1

IGOEN0 : IGOEN0
bits : 0 - 0 (1 bit)
access : read-write

IGOEN1 : IGOEN1
bits : 1 - 1 (1 bit)
access : read-write

IGPOL0 : IGPOL0
bits : 4 - 4 (1 bit)
access : read-write

IGPOL1 : IGPOL1
bits : 5 - 5 (1 bit)
access : read-write


IGRG2

IGBT RG2 Timer Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IGRG2 IGRG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IGRG2

IGRG2 : IGRG2
bits : 0 - 15 (16 bit)
access : read-write


IGRG3

IGBT RG3 Timer Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IGRG3 IGRG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IGRG3

IGRG3 : IGRG3
bits : 0 - 15 (16 bit)
access : read-write


IGRG4

IGBT RG4 Timer Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IGRG4 IGRG4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IGRG4

IGRG4 : IGRG4
bits : 0 - 15 (16 bit)
access : read-write


IGEMGCR

IGBT EMG Control Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IGEMGCR IGEMGCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IGEMGEN IGEMGOC IGEMGRS IGEMGCNT

IGEMGEN : IGEMGEN
bits : 0 - 0 (1 bit)
access : read-write

IGEMGOC : IGEMGOC
bits : 1 - 1 (1 bit)
access : read-write

IGEMGRS : IGEMGRS
bits : 2 - 2 (1 bit)
access : write-only

IGEMGCNT : IGEMGCNT
bits : 4 - 7 (4 bit)
access : read-write


IGEMGST

IGBT EMG Status Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IGEMGST IGEMGST read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IGEMGST IGEMGIN

IGEMGST : IGEMGST
bits : 0 - 0 (1 bit)
access : read-only

IGEMGIN : IGEMGIN
bits : 1 - 1 (1 bit)
access : read-only


IGTRG

IGBT Trigger Status Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IGTRG IGTRG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IGTRG

IGTRG : IGTRG
bits : 0 - 15 (16 bit)
access : read-write


TBCR

MPT Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TBCR TBCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTTBCSSEL MTTBTRGSEL MTI2TB MTTBWBF

MTTBCSSEL : MTTBCSSEL
bits : 0 - 0 (1 bit)
access : read-write

MTTBTRGSEL : MTTBTRGSEL
bits : 1 - 1 (1 bit)
access : read-write

MTI2TB : MTI2TB
bits : 3 - 3 (1 bit)
access : read-write

MTTBWBF : MTTBWBF
bits : 7 - 7 (1 bit)
access : read-write


TBMOD

MPT Mode Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TBMOD TBMOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTTBCLK MTTBCLE MTTBCPM MTTBCP MTTBRSWR

MTTBCLK : MTTBCLK
bits : 0 - 1 (2 bit)
access : read-write

MTTBCLE : MTTBCLE
bits : 2 - 2 (1 bit)
access : read-write

MTTBCPM : MTTBCPM
bits : 3 - 4 (2 bit)
access : read-write

MTTBCP : MTTBCP
bits : 5 - 5 (1 bit)
access : write-only

MTTBRSWR : MTTBRSWR
bits : 6 - 6 (1 bit)
access : read-write



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