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CEC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x38 byte (0x0)
mem_usage : registers
protection : not protected

Registers

EN

RBUF

RCR1

RCR2

RCR3

TEN

TBUF

TCR

RSTAT

TSTAT

FSSEL

ADD

RESET

REN


EN

CEC Enable Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CECEN I2CEC

CECEN : CECEN
bits : 0 - 0 (1 bit)
access : read-write

I2CEC : I2CEC
bits : 1 - 1 (1 bit)
access : read-write


RBUF

CEC Receive Buffer Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RBUF RBUF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CECRBUF CECEOM CECACK

CECRBUF : CECRBUF
bits : 0 - 7 (8 bit)
access : read-only

CECEOM : CECEOM
bits : 8 - 8 (1 bit)
access : read-only

CECACK : CECACK
bits : 9 - 9 (1 bit)
access : read-only


RCR1

CEC Receive Control Register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCR1 RCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CECOTH CECRIHLD CECTOUT CECDAT CECMAX CECMIN CECLNC CECHNC CECACKDIS

CECOTH : CECOTH
bits : 0 - 0 (1 bit)
access : read-write

CECRIHLD : CECRIHLD
bits : 1 - 1 (1 bit)
access : read-write

CECTOUT : CECTOUT
bits : 2 - 3 (2 bit)
access : read-write

CECDAT : CECDAT
bits : 4 - 6 (3 bit)
access : read-write

CECMAX : CECMAX
bits : 8 - 10 (3 bit)
access : read-write

CECMIN : CECMIN
bits : 12 - 14 (3 bit)
access : read-write

CECLNC : CECLNC
bits : 16 - 18 (3 bit)
access : read-write

CECHNC : CECHNC
bits : 20 - 21 (2 bit)
access : read-write

CECACKDIS : CECACKDIS
bits : 24 - 24 (1 bit)
access : read-write


RCR2

CEC Receive Control Register 2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCR2 RCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CECSWAV0 CECSWAV1 CECSWAV2 CECSWAV3

CECSWAV0 : CECSWAV0
bits : 0 - 2 (3 bit)
access : read-write

CECSWAV1 : CECSWAV1
bits : 4 - 6 (3 bit)
access : read-write

CECSWAV2 : CECSWAV2
bits : 8 - 10 (3 bit)
access : read-write

CECSWAV3 : CECSWAV3
bits : 12 - 14 (3 bit)
access : read-write


RCR3

CEC Receive Control Register 3
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCR3 RCR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CECWAVEN CECRSTAEN CECWAV0 CECWAV1 CECWAV2 CECWAV3

CECWAVEN : CECWAVEN
bits : 0 - 0 (1 bit)
access : read-write

CECRSTAEN : CECRSTAEN
bits : 1 - 1 (1 bit)
access : read-write

CECWAV0 : CECWAV0
bits : 8 - 10 (3 bit)
access : read-write

CECWAV1 : CECWAV1
bits : 12 - 14 (3 bit)
access : read-write

CECWAV2 : CECWAV2
bits : 16 - 18 (3 bit)
access : read-write

CECWAV3 : CECWAV3
bits : 20 - 22 (3 bit)
access : read-write


TEN

CEC Transmit Enable Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TEN TEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CECTEN CECTRANS

CECTEN : CECTEN
bits : 0 - 0 (1 bit)
access : write-only

CECTRANS : CECTRANS
bits : 1 - 1 (1 bit)
access : read-only


TBUF

CEC Transmit Buffer Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TBUF TBUF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CECTBUF CECTEOM

CECTBUF : CECTBUF
bits : 0 - 7 (8 bit)
access : read-write

CECTEOM : CECTEOM
bits : 8 - 8 (1 bit)
access : read-write


TCR

CEC Transmit Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCR TCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CECFREE CECBRD CECDPRD CECDTRS CECSPRD CECSTRS

CECFREE : CECFREE
bits : 0 - 3 (4 bit)
access : read-write

CECBRD : CECBRD
bits : 4 - 4 (1 bit)
access : read-write

CECDPRD : CECDPRD
bits : 8 - 11 (4 bit)
access : read-write

CECDTRS : CECDTRS
bits : 12 - 14 (3 bit)
access : read-write

CECSPRD : CECSPRD
bits : 16 - 18 (3 bit)
access : read-write

CECSTRS : CECSTRS
bits : 20 - 22 (3 bit)
access : read-write


RSTAT

CEC Receive Interrupt Status Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RSTAT RSTAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CECRIEND CECRISTA CECRIMAX CECRIMIN CECRIACK CECRIOR CECRIWAV

CECRIEND : CECRIEND
bits : 0 - 0 (1 bit)
access : read-only

CECRISTA : CECRISTA
bits : 1 - 1 (1 bit)
access : read-only

CECRIMAX : CECRIMAX
bits : 2 - 2 (1 bit)
access : read-only

CECRIMIN : CECRIMIN
bits : 3 - 3 (1 bit)
access : read-only

CECRIACK : CECRIACK
bits : 4 - 4 (1 bit)
access : read-only

CECRIOR : CECRIOR
bits : 5 - 5 (1 bit)
access : read-only

CECRIWAV : CECRIWAV
bits : 6 - 6 (1 bit)
access : read-only


TSTAT

CEC Transmit Interrupt Status Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TSTAT TSTAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CECTISTA CECTIEND CECTIAL CECTIACK CECTIUR

CECTISTA : CECTISTA
bits : 0 - 0 (1 bit)
access : read-only

CECTIEND : CECTIEND
bits : 1 - 1 (1 bit)
access : read-only

CECTIAL : CECTIAL
bits : 2 - 2 (1 bit)
access : read-only

CECTIACK : CECTIACK
bits : 3 - 3 (1 bit)
access : read-only

CECTIUR : CECTIUR
bits : 4 - 4 (1 bit)
access : read-only


FSSEL

CEC Sampling Clock Select Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FSSEL FSSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CECCLK

CECCLK : CECCLK
bits : 0 - 0 (1 bit)
access : read-write


ADD

CEC Logical Address Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADD ADD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CECADD

CECADD : CECADD
bits : 0 - 15 (16 bit)
access : read-write


RESET

CEC Software Reset Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

RESET RESET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CECRESET

CECRESET : CECRESET
bits : 0 - 0 (1 bit)
access : write-only


REN

CEC Receive Enable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REN REN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CECREN

CECREN : CECREN
bits : 0 - 0 (1 bit)
access : read-write



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