\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Counter enable
bits : 0 - 0 (1 bit)
UDIS : Update disable
bits : 1 - 1 (1 bit)
URS : Update request source
bits : 2 - 2 (1 bit)
OPM : One-pulse mode
bits : 3 - 3 (1 bit)
ARPE : Auto-reload preload enable
bits : 7 - 7 (1 bit)
CKD : Clock division
bits : 8 - 9 (2 bit)
status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UIF : Update interrupt flag
bits : 0 - 0 (1 bit)
CC1IF : Capture/compare 1 interrupt flag
bits : 1 - 1 (1 bit)
CC2IF : Capture/Compare 2 interrupt flag
bits : 2 - 2 (1 bit)
TIF : Trigger interrupt flag
bits : 6 - 6 (1 bit)
CC1OF : Capture/Compare 1 overcapture flag
bits : 9 - 9 (1 bit)
CC2OF : Capture/compare 2 overcapture flag
bits : 10 - 10 (1 bit)
event generation register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UG : Update generation
bits : 0 - 0 (1 bit)
CC1G : Capture/compare 1 generation
bits : 1 - 1 (1 bit)
CC2G : Capture/compare 2 generation
bits : 2 - 2 (1 bit)
TG : Trigger generation
bits : 6 - 6 (1 bit)
capture/compare mode register 1 (output mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC1S : Capture/Compare 1 selection
bits : 0 - 1 (2 bit)
OC1FE : Output Compare 1 fast enable
bits : 2 - 2 (1 bit)
OC1PE : Output Compare 1 preload enable
bits : 3 - 3 (1 bit)
OC1M : Output Compare 1 mode
bits : 4 - 6 (3 bit)
CC2S : Capture/Compare 2 selection
bits : 8 - 9 (2 bit)
OC2FE : Output Compare 2 fast enable
bits : 10 - 10 (1 bit)
OC2PE : Output Compare 2 preload enable
bits : 11 - 11 (1 bit)
OC2M : Output Compare 2 mode
bits : 12 - 14 (3 bit)
capture/compare mode register 1 (input mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCMR1_Output
reset_Mask : 0x0
CC1S : Capture/Compare 1 selection
bits : 0 - 1 (2 bit)
ICPCS : Input capture 1 prescaler
bits : 2 - 3 (2 bit)
IC1F : Input capture 1 filter
bits : 4 - 6 (3 bit)
CC2S : Capture/Compare 2 selection
bits : 8 - 9 (2 bit)
IC2PCS : Input capture 2 prescaler
bits : 10 - 11 (2 bit)
IC2F : Input capture 2 filter
bits : 12 - 14 (3 bit)
capture/compare enable register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC1E : Capture/Compare 1 output enable
bits : 0 - 0 (1 bit)
CC1P : Capture/Compare 1 output Polarity
bits : 1 - 1 (1 bit)
CC1NP : Capture/Compare 1 output Polarity
bits : 3 - 3 (1 bit)
CC2E : Capture/Compare 2 output enable
bits : 4 - 4 (1 bit)
CC2P : Capture/Compare 2 output Polarity
bits : 5 - 5 (1 bit)
CC2NP : Capture/Compare 2 output Polarity
bits : 7 - 7 (1 bit)
counter
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : counter value
bits : 0 - 15 (16 bit)
prescaler
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSC : Prescaler value
bits : 0 - 15 (16 bit)
auto-reload register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARR : Auto-reload value
bits : 0 - 15 (16 bit)
capture/compare register 1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCR1 : Capture/Compare 1 value
bits : 0 - 15 (16 bit)
capture/compare register 2
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCR2 : Capture/Compare 2 value
bits : 0 - 15 (16 bit)
control register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MMS : Master mode selection
bits : 4 - 6 (3 bit)
slave mode control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMS : Slave mode selection
bits : 0 - 2 (3 bit)
TS : Trigger selection
bits : 4 - 6 (3 bit)
MSM : Master/Slave mode
bits : 7 - 7 (1 bit)
DMA/Interrupt enable register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UIE : Update interrupt enable
bits : 0 - 0 (1 bit)
CC1IE : Capture/Compare 1 interrupt enable
bits : 1 - 1 (1 bit)
CC2IE : Capture/Compare 2 interrupt enable
bits : 2 - 2 (1 bit)
TIE : Trigger interrupt enable
bits : 6 - 6 (1 bit)
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