\n
address_offset : 0x0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
Interval Sencing Detector(ISD)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
Input Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I0M : I0M
bits : 0 - 2 (3 bit)
access : read-write
I1M : I1M
bits : 4 - 6 (3 bit)
access : read-write
I2M : I2M
bits : 8 - 10 (3 bit)
access : read-write
I3M : I3M
bits : 12 - 14 (3 bit)
access : read-write
Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : START
bits : 0 - 0 (1 bit)
access : read-write
Buffer Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
B0 : B0
bits : 0 - 3 (4 bit)
access : read-only
Status Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
S0 : S0
bits : 0 - 3 (4 bit)
access : read-only
Interrupu Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTEN : INTEN
bits : 0 - 0 (1 bit)
access : read-only
Clock Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MS : MS
bits : 0 - 0 (1 bit)
access : read-write
SC : SC
bits : 1 - 1 (1 bit)
access : read-write
DIV : DIV
bits : 2 - 3 (2 bit)
access : read-write
Output Control Register 0
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDOP : SDOP
bits : 0 - 0 (1 bit)
access : read-write
Output Control Register 1
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T0 : T0
bits : 0 - 7 (8 bit)
access : read-write
T1 : T1
bits : 8 - 15 (8 bit)
access : read-write
T2 : T2
bits : 16 - 23 (8 bit)
access : read-write
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