\n

PL

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x38 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x28 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x34 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x24 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x1C Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x8 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : reserved
protection : not protected

Registers

DATA

FR6

FR7

OD

PUP

PDN

IE

CR


DATA

PL Data Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PL0 PL1 PL2 PL3 PL4

PL0 : PL0
bits : 0 - 0 (1 bit)
access : read-write

PL1 : PL1
bits : 1 - 1 (1 bit)
access : read-write

PL2 : PL2
bits : 2 - 2 (1 bit)
access : read-write

PL3 : PL3
bits : 3 - 3 (1 bit)
access : read-write

PL4 : PL4
bits : 4 - 4 (1 bit)
access : read-write


FR6

PL Function Register 6
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FR6 FR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PL0F6 PL1F6 PL2F6 PL3F6 PL4F6

PL0F6 : PL0F6
bits : 0 - 0 (1 bit)
access : read-write

PL1F6 : PL1F6
bits : 1 - 1 (1 bit)
access : read-write

PL2F6 : PL2F6
bits : 2 - 2 (1 bit)
access : read-write

PL3F6 : PL3F6
bits : 3 - 3 (1 bit)
access : read-write

PL4F6 : PL4F6
bits : 4 - 4 (1 bit)
access : read-write


FR7

PL Function Register 7
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FR7 FR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PL0F7 PL1F7 PL2F7 PL3F7 PL4F7

PL0F7 : PL0F7
bits : 0 - 0 (1 bit)
access : read-write

PL1F7 : PL1F7
bits : 1 - 1 (1 bit)
access : read-write

PL2F7 : PL2F7
bits : 2 - 2 (1 bit)
access : read-write

PL3F7 : PL3F7
bits : 3 - 3 (1 bit)
access : read-write

PL4F7 : PL4F7
bits : 4 - 4 (1 bit)
access : read-write


OD

PL Open Drain Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OD OD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PL0OD PL1OD PL2OD PL3OD PL4OD

PL0OD : PL0OD
bits : 0 - 0 (1 bit)
access : read-write

PL1OD : PL1OD
bits : 1 - 1 (1 bit)
access : read-write

PL2OD : PL2OD
bits : 2 - 2 (1 bit)
access : read-write

PL3OD : PL3OD
bits : 3 - 3 (1 bit)
access : read-write

PL4OD : PL4OD
bits : 4 - 4 (1 bit)
access : read-write


PUP

PL Pull-up Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUP PUP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PL0PUP PL1PUP PL2PUP PL3PUP PL4PUP

PL0PUP : PL0PUP
bits : 0 - 0 (1 bit)
access : read-write

PL1PUP : PL1PUP
bits : 1 - 1 (1 bit)
access : read-write

PL2PUP : PL2PUP
bits : 2 - 2 (1 bit)
access : read-write

PL3PUP : PL3PUP
bits : 3 - 3 (1 bit)
access : read-write

PL4PUP : PL4PUP
bits : 4 - 4 (1 bit)
access : read-write


PDN

PL Pull-Down Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDN PDN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PL0PDN PL1PDN PL2PDN PL3PDN PL4PDN

PL0PDN : PL0PDN
bits : 0 - 0 (1 bit)
access : read-write

PL1PDN : PL1PDN
bits : 1 - 1 (1 bit)
access : read-write

PL2PDN : PL2PDN
bits : 2 - 2 (1 bit)
access : read-write

PL3PDN : PL3PDN
bits : 3 - 3 (1 bit)
access : read-write

PL4PDN : PL4PDN
bits : 4 - 4 (1 bit)
access : read-write


IE

PL Input Enable Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IE IE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PL0IE PL1IE PL2IE PL3IE PL4IE

PL0IE : PL0IE
bits : 0 - 0 (1 bit)
access : read-write

PL1IE : PL1IE
bits : 1 - 1 (1 bit)
access : read-write

PL2IE : PL2IE
bits : 2 - 2 (1 bit)
access : read-write

PL3IE : PL3IE
bits : 3 - 3 (1 bit)
access : read-write

PL4IE : PL4IE
bits : 4 - 4 (1 bit)
access : read-write


CR

PL Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PL0C PL1C PL2C PL3C PL4C

PL0C : PL0C
bits : 0 - 0 (1 bit)
access : read-write

PL1C : PL1C
bits : 1 - 1 (1 bit)
access : read-write

PL2C : PL2C
bits : 2 - 2 (1 bit)
access : read-write

PL3C : PL3C
bits : 3 - 3 (1 bit)
access : read-write

PL4C : PL4C
bits : 4 - 4 (1 bit)
access : read-write



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