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T32A0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x40 Bytes (0x0)
size : 0x38 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x4 Bytes (0x0)
size : 0x3C byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x78 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x80 Bytes (0x0)
size : 0x38 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xB8 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0xC0 Bytes (0x0)
size : 0x3C byte (0x0)
mem_usage : registers
protection : not protected

Registers

MOD

RUNA

CRA

CAPCRA

OUTCRA0

OUTCRA1

STA

IMA

TMRA

RELDA

RGA0

RGA1

CAPA0

CAPA1

DMAA

RUNB

CRB

CAPCRB

OUTCRB0

OUTCRB1

STB

IMB

TMRB

RELDB

RGB0

RGB1

CAPB0

CAPB1

DMAB

RUNC

CRC

CAPCRC

OUTCRC0

OUTCRC1

STC

IMC

TMRC

RELDC

RGC0

RGC1

CAPC0

CAPC1

DMAC

PLSCR


MOD

T32A Mode Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOD MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE32 HALT

MODE32 : MODE32
bits : 0 - 0 (1 bit)
access : read-write

HALT : HALT
bits : 1 - 1 (1 bit)
access : read-write


RUNA

T32A Run Register A
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RUNA RUNA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUNA SFTSTAA SFTSTPA RUNFLGA

RUNA : RUNA
bits : 0 - 0 (1 bit)
access : read-write

SFTSTAA : SFTSTAA
bits : 1 - 1 (1 bit)
access : write-only

SFTSTPA : SFTSTPA
bits : 2 - 2 (1 bit)
access : write-only

RUNFLGA : RUNFLGA
bits : 4 - 4 (1 bit)
access : read-only


CRA

T32A Control Register A
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRA CRA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STARTA STOPA RELDA UPDNA WBFA CLKA PRSCLA

STARTA : STARTA
bits : 0 - 2 (3 bit)
access : read-write

STOPA : STOPA
bits : 4 - 6 (3 bit)
access : read-write

RELDA : RELDA
bits : 8 - 10 (3 bit)
access : read-write

UPDNA : UPDNA
bits : 16 - 17 (2 bit)
access : read-write

WBFA : WBFA
bits : 20 - 20 (1 bit)
access : read-write

CLKA : CLKA
bits : 24 - 26 (3 bit)
access : read-write

PRSCLA : PRSCLA
bits : 28 - 30 (3 bit)
access : read-write


CAPCRA

T32A Capture Control Register A
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAPCRA CAPCRA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPMA0 CAPMA1

CAPMA0 : CAPMA0
bits : 0 - 2 (3 bit)
access : read-write

CAPMA1 : CAPMA1
bits : 4 - 6 (3 bit)
access : read-write


OUTCRA0

T32A Output Control Register A0
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

OUTCRA0 OUTCRA0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCRA

OCRA : OCRA
bits : 0 - 1 (2 bit)
access : write-only


OUTCRA1

T32A Output Control Register A1
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OUTCRA1 OUTCRA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCRCMPA0 OCRCMPA1 OCRCAPA0 OCRCAPA1

OCRCMPA0 : OCRCMPA0
bits : 0 - 1 (2 bit)
access : read-write

OCRCMPA1 : OCRCMPA1
bits : 2 - 3 (2 bit)
access : read-write

OCRCAPA0 : OCRCAPA0
bits : 4 - 5 (2 bit)
access : read-write

OCRCAPA1 : OCRCAPA1
bits : 6 - 7 (2 bit)
access : read-write


STA

T32A Status Register A
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STA STA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTA0 INTA1 INTOFA INTUFA

INTA0 : INTA0
bits : 0 - 0 (1 bit)
access : read-write

INTA1 : INTA1
bits : 1 - 1 (1 bit)
access : read-write

INTOFA : INTOFA
bits : 2 - 2 (1 bit)
access : read-write

INTUFA : INTUFA
bits : 3 - 3 (1 bit)
access : read-write


IMA

T32A Interrupt Mask Register A
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMA IMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IMA0 IMA1 IMOFA IMUFA

IMA0 : IMA0
bits : 0 - 0 (1 bit)
access : read-write

IMA1 : IMA1
bits : 1 - 1 (1 bit)
access : read-write

IMOFA : IMOFA
bits : 2 - 2 (1 bit)
access : read-write

IMUFA : IMUFA
bits : 3 - 3 (1 bit)
access : read-write


TMRA

T32A Counter Capture Register A
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TMRA TMRA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRA

TMRA : TMRA
bits : 0 - 15 (16 bit)
access : read-only


RELDA

T32A Reload Register A
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RELDA RELDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RELDA

RELDA : RELDA
bits : 0 - 15 (16 bit)
access : read-write


RGA0

T32A Timer Register A0
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGA0 RGA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RGA0

RGA0 : RGA0
bits : 0 - 15 (16 bit)
access : read-write


RGA1

T32A Timer Register A1
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGA1 RGA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RGA1

RGA1 : RGA1
bits : 0 - 15 (16 bit)
access : read-write


CAPA0

T32A Capture Register A0
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CAPA0 CAPA0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPA0

CAPA0 : CAPA0
bits : 0 - 15 (16 bit)
access : read-only


CAPA1

T32A Capture Register A1
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CAPA1 CAPA1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPA1

CAPA1 : CAPA1
bits : 0 - 15 (16 bit)
access : read-only


DMAA

T32A DMA Request Enable Register A
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAA DMAA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAENA0 DMAENA1 DMAENA2

DMAENA0 : DMAENA0
bits : 0 - 0 (1 bit)
access : read-write

DMAENA1 : DMAENA1
bits : 1 - 1 (1 bit)
access : read-write

DMAENA2 : DMAENA2
bits : 2 - 2 (1 bit)
access : read-write


RUNB

T32A Run Register B
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RUNB RUNB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUNB SFTSTAB SFTSTPB RUNFLGB

RUNB : RUNB
bits : 0 - 0 (1 bit)
access : read-write

SFTSTAB : SFTSTAB
bits : 1 - 1 (1 bit)
access : write-only

SFTSTPB : SFTSTPB
bits : 2 - 2 (1 bit)
access : write-only

RUNFLGB : RUNFLGB
bits : 4 - 4 (1 bit)
access : read-only


CRB

T32A Control Register B
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRB CRB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STARTB STOPB RELDB UPDNB WBFB CLKB PRSCLB

STARTB : STARTB
bits : 0 - 2 (3 bit)
access : read-write

STOPB : STOPB
bits : 4 - 6 (3 bit)
access : read-write

RELDB : RELDB
bits : 8 - 10 (3 bit)
access : read-write

UPDNB : UPDNB
bits : 16 - 17 (2 bit)
access : read-write

WBFB : WBFB
bits : 20 - 20 (1 bit)
access : read-write

CLKB : CLKB
bits : 24 - 26 (3 bit)
access : read-write

PRSCLB : PRSCLB
bits : 28 - 30 (3 bit)
access : read-write


CAPCRB

T32A Capture Control Register B
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAPCRB CAPCRB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPMB0 CAPMB1

CAPMB0 : CAPMB0
bits : 0 - 2 (3 bit)
access : read-write

CAPMB1 : CAPMB1
bits : 4 - 6 (3 bit)
access : read-write


OUTCRB0

T32A Output Control Register B0
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

OUTCRB0 OUTCRB0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCRB

OCRB : OCRB
bits : 0 - 1 (2 bit)
access : write-only


OUTCRB1

T32A Output Control Register B1
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OUTCRB1 OUTCRB1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCRCMPB0 OCRCMPB1 OCRCAPB0 OCRCAPB1

OCRCMPB0 : OCRCMPB0
bits : 0 - 1 (2 bit)
access : read-write

OCRCMPB1 : OCRCMPB1
bits : 2 - 3 (2 bit)
access : read-write

OCRCAPB0 : OCRCAPB0
bits : 4 - 5 (2 bit)
access : read-write

OCRCAPB1 : OCRCAPB1
bits : 6 - 7 (2 bit)
access : read-write


STB

T32A Status Register B
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STB STB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTB0 INTB1 INTOFB INTUFB

INTB0 : INTB0
bits : 0 - 0 (1 bit)
access : read-write

INTB1 : INTB1
bits : 1 - 1 (1 bit)
access : read-write

INTOFB : INTOFB
bits : 2 - 2 (1 bit)
access : read-write

INTUFB : INTUFB
bits : 3 - 3 (1 bit)
access : read-write


IMB

T32A Interrupt Mask Register B
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMB IMB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IMB0 IMB1 IMOFB IMUFB

IMB0 : IMB0
bits : 0 - 0 (1 bit)
access : read-write

IMB1 : IMB1
bits : 1 - 1 (1 bit)
access : read-write

IMOFB : IMOFB
bits : 2 - 2 (1 bit)
access : read-write

IMUFB : IMUFB
bits : 3 - 3 (1 bit)
access : read-write


TMRB

T32A Counter Capture Register B
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TMRB TMRB read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRB

TMRB : TMRB
bits : 0 - 15 (16 bit)
access : read-only


RELDB

T32A Reload Register B
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RELDB RELDB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RELDB

RELDB : RELDB
bits : 0 - 15 (16 bit)
access : read-write


RGB0

T32A Timer Register B0
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGB0 RGB0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RGB0

RGB0 : RGB0
bits : 0 - 15 (16 bit)
access : read-write


RGB1

T32A Timer Register B1
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGB1 RGB1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RGB1

RGB1 : RGB1
bits : 0 - 15 (16 bit)
access : read-write


CAPB0

T32A Capture Register B0
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CAPB0 CAPB0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPB0

CAPB0 : CAPB0
bits : 0 - 15 (16 bit)
access : read-only


CAPB1

T32A Capture Register B1
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CAPB1 CAPB1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPB1

CAPB1 : CAPB1
bits : 0 - 15 (16 bit)
access : read-only


DMAB

T32A DMA Request Enable Register B
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAB DMAB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAENB0 DMAENB1 DMAENB2

DMAENB0 : DMAENB0
bits : 0 - 0 (1 bit)
access : read-write

DMAENB1 : DMAENB1
bits : 1 - 1 (1 bit)
access : read-write

DMAENB2 : DMAENB2
bits : 2 - 2 (1 bit)
access : read-write


RUNC

T32A Run Register C
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RUNC RUNC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUNC SFTSTAC SFTSTPC RUNFLGC

RUNC : RUNC
bits : 0 - 0 (1 bit)
access : read-write

SFTSTAC : SFTSTAC
bits : 1 - 1 (1 bit)
access : write-only

SFTSTPC : SFTSTPC
bits : 2 - 2 (1 bit)
access : write-only

RUNFLGC : RUNFLGC
bits : 4 - 4 (1 bit)
access : read-only


CRC

T32A Control Register C
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRC CRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STARTC STOPC RELDC UPDNC WBFC CLKC PRSCLC

STARTC : STARTC
bits : 0 - 2 (3 bit)
access : read-write

STOPC : STOPC
bits : 4 - 6 (3 bit)
access : read-write

RELDC : RELDC
bits : 8 - 10 (3 bit)
access : read-write

UPDNC : UPDNC
bits : 16 - 17 (2 bit)
access : read-write

WBFC : WBFC
bits : 20 - 20 (1 bit)
access : read-write

CLKC : CLKC
bits : 24 - 26 (3 bit)
access : read-write

PRSCLC : PRSCLC
bits : 28 - 30 (3 bit)
access : read-write


CAPCRC

T32A Capture Control Register C
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAPCRC CAPCRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPMC0 CAPMC1

CAPMC0 : CAPMC0
bits : 0 - 2 (3 bit)
access : read-write

CAPMC1 : CAPMC1
bits : 4 - 6 (3 bit)
access : read-write


OUTCRC0

T32A Output Control Register C0
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

OUTCRC0 OUTCRC0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCRC

OCRC : OCRC
bits : 0 - 1 (2 bit)
access : write-only


OUTCRC1

T32A Output Control Register C1
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OUTCRC1 OUTCRC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCRCMPC0 OCRCMPC1 OCRCAPC0 OCRCAPC1

OCRCMPC0 : OCRCMPC0
bits : 0 - 1 (2 bit)
access : read-write

OCRCMPC1 : OCRCMPC1
bits : 2 - 3 (2 bit)
access : read-write

OCRCAPC0 : OCRCAPC0
bits : 4 - 5 (2 bit)
access : read-write

OCRCAPC1 : OCRCAPC1
bits : 6 - 7 (2 bit)
access : read-write


STC

T32A Status Register C
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STC STC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTC0 INTC1 INTOFC INTUFC INTSTERR

INTC0 : INTC0
bits : 0 - 0 (1 bit)
access : read-write

INTC1 : INTC1
bits : 1 - 1 (1 bit)
access : read-write

INTOFC : INTOFC
bits : 2 - 2 (1 bit)
access : read-write

INTUFC : INTUFC
bits : 3 - 3 (1 bit)
access : read-write

INTSTERR : INTSTERR
bits : 4 - 4 (1 bit)
access : read-write


IMC

T32A Interrupt Mask Register C
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC IMC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IMC0 IMC1 IMOFC IMUFC IMSTERR

IMC0 : IMC0
bits : 0 - 0 (1 bit)
access : read-write

IMC1 : IMC1
bits : 1 - 1 (1 bit)
access : read-write

IMOFC : IMOFC
bits : 2 - 2 (1 bit)
access : read-write

IMUFC : IMUFC
bits : 3 - 3 (1 bit)
access : read-write

IMSTERR : IMSTERR
bits : 4 - 4 (1 bit)
access : read-write


TMRC

T32A Counter Capture Register C
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TMRC TMRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRC

TMRC : TMRC
bits : 0 - 31 (32 bit)
access : read-only


RELDC

T32A Reload Register C
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RELDC RELDC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RELDC

RELDC : RELDC
bits : 0 - 31 (32 bit)
access : read-write


RGC0

T32A Timer Register C0
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGC0 RGC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RGC0

RGC0 : RGC0
bits : 0 - 31 (32 bit)
access : read-write


RGC1

T32A Timer Register C1
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGC1 RGC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RGC1

RGC1 : RGC1
bits : 0 - 31 (32 bit)
access : read-write


CAPC0

T32A Capture Register C0
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CAPC0 CAPC0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPC0

CAPC0 : CAPC0
bits : 0 - 31 (32 bit)
access : read-only


CAPC1

T32A Capture Register C1
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CAPC1 CAPC1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPC1

CAPC1 : CAPC1
bits : 0 - 31 (32 bit)
access : read-only


DMAC

T32A DMA Request Enable Register C
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAC DMAC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAENC0 DMAENC1 DMAENC2

DMAENC0 : DMAENC0
bits : 0 - 0 (1 bit)
access : read-write

DMAENC1 : DMAENC1
bits : 1 - 1 (1 bit)
access : read-write

DMAENC2 : DMAENC2
bits : 2 - 2 (1 bit)
access : read-write


PLSCR

T32A Pulse Count Control Register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLSCR PLSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PMODE PDIR NF PUP PDN

PMODE : PMODE
bits : 0 - 0 (1 bit)
access : read-write

PDIR : PDIR
bits : 1 - 1 (1 bit)
access : read-write

NF : NF
bits : 4 - 5 (2 bit)
access : read-write

PUP : PUP
bits : 8 - 10 (3 bit)
access : read-write

PDN : PDN
bits : 12 - 14 (3 bit)
access : read-write



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