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PU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x38 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x28 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x34 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x24 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected

Registers

DATA

FR3

FR4

FR5

FR6

FR7

OD

PUP

PDN

IE

CR

FR1

FR2


DATA

Port U Data Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU0 PU1 PU2 PU3 PU4 PU5 PU6

PU0 : PU0
bits : 0 - 0 (1 bit)
access : read-write

PU1 : PU1
bits : 1 - 1 (1 bit)
access : read-write

PU2 : PU2
bits : 2 - 2 (1 bit)
access : read-write

PU3 : PU3
bits : 3 - 3 (1 bit)
access : read-write

PU4 : PU4
bits : 4 - 4 (1 bit)
access : read-write

PU5 : PU5
bits : 5 - 5 (1 bit)
access : read-write

PU6 : PU6
bits : 6 - 6 (1 bit)
access : read-write


FR3

Port U Function Register 3
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FR3 FR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU0F3 PU1F3

PU0F3 : PU0F3
bits : 0 - 0 (1 bit)
access : read-write

PU1F3 : PU1F3
bits : 1 - 1 (1 bit)
access : read-write


FR4

Port U Function Register 4
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FR4 FR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU0F4 PU1F4 PU2F4 PU3F4 PU4F4 PU5F4

PU0F4 : PU0F4
bits : 0 - 0 (1 bit)
access : read-write

PU1F4 : PU1F4
bits : 1 - 1 (1 bit)
access : read-write

PU2F4 : PU2F4
bits : 2 - 2 (1 bit)
access : read-write

PU3F4 : PU3F4
bits : 3 - 3 (1 bit)
access : read-write

PU4F4 : PU4F4
bits : 4 - 4 (1 bit)
access : read-write

PU5F4 : PU5F4
bits : 5 - 5 (1 bit)
access : read-write


FR5

Port U Function Register 5
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FR5 FR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU1F5 PU2F5 PU3F5 PU4F5 PU5F5 PU6F5

PU1F5 : PU1F5
bits : 1 - 1 (1 bit)
access : read-write

PU2F5 : PU2F5
bits : 2 - 2 (1 bit)
access : read-write

PU3F5 : PU3F5
bits : 3 - 3 (1 bit)
access : read-write

PU4F5 : PU4F5
bits : 4 - 4 (1 bit)
access : read-write

PU5F5 : PU5F5
bits : 5 - 5 (1 bit)
access : read-write

PU6F5 : PU6F5
bits : 6 - 6 (1 bit)
access : read-write


FR6

Port U Function Register 6
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FR6 FR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU0F6 PU1F6 PU2F6 PU3F6 PU4F6 PU5F6 PU6F6

PU0F6 : PU0F6
bits : 0 - 0 (1 bit)
access : read-write

PU1F6 : PU1F6
bits : 1 - 1 (1 bit)
access : read-write

PU2F6 : PU2F6
bits : 2 - 2 (1 bit)
access : read-write

PU3F6 : PU3F6
bits : 3 - 3 (1 bit)
access : read-write

PU4F6 : PU4F6
bits : 4 - 4 (1 bit)
access : read-write

PU5F6 : PU5F6
bits : 5 - 5 (1 bit)
access : read-write

PU6F6 : PU6F6
bits : 6 - 6 (1 bit)
access : read-write


FR7

Port U Function Register 7
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FR7 FR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OD

Port U Open Drain Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OD OD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU0OD PU1OD PU2OD PU3OD PU4OD PU5OD PU6OD

PU0OD : PU0OD
bits : 0 - 0 (1 bit)
access : read-write

PU1OD : PU1OD
bits : 1 - 1 (1 bit)
access : read-write

PU2OD : PU2OD
bits : 2 - 2 (1 bit)
access : read-write

PU3OD : PU3OD
bits : 3 - 3 (1 bit)
access : read-write

PU4OD : PU4OD
bits : 4 - 4 (1 bit)
access : read-write

PU5OD : PU5OD
bits : 5 - 5 (1 bit)
access : read-write

PU6OD : PU6OD
bits : 6 - 6 (1 bit)
access : read-write


PUP

Port U Pull-up Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUP PUP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU0UP PU1UP PU2UP PU3UP PU4UP PU5UP PU6UP

PU0UP : PU0UP
bits : 0 - 0 (1 bit)
access : read-write

PU1UP : PU1UP
bits : 1 - 1 (1 bit)
access : read-write

PU2UP : PU2UP
bits : 2 - 2 (1 bit)
access : read-write

PU3UP : PU3UP
bits : 3 - 3 (1 bit)
access : read-write

PU4UP : PU4UP
bits : 4 - 4 (1 bit)
access : read-write

PU5UP : PU5UP
bits : 5 - 5 (1 bit)
access : read-write

PU6UP : PU6UP
bits : 6 - 6 (1 bit)
access : read-write


PDN

Port U Pull-down Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDN PDN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU0DN PU1DN PU2DN PU3DN PU4DN PU5DN PU6DN

PU0DN : PU0DN
bits : 0 - 0 (1 bit)
access : read-write

PU1DN : PU1DN
bits : 1 - 1 (1 bit)
access : read-write

PU2DN : PU2DN
bits : 2 - 2 (1 bit)
access : read-write

PU3DN : PU3DN
bits : 3 - 3 (1 bit)
access : read-write

PU4DN : PU4DN
bits : 4 - 4 (1 bit)
access : read-write

PU5DN : PU5DN
bits : 5 - 5 (1 bit)
access : read-write

PU6DN : PU6DN
bits : 6 - 6 (1 bit)
access : read-write


IE

Port U Input Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IE IE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU0IE PU1IE PU2IE PU3IE PU4IE PU5IE PU6IE

PU0IE : PU0IE
bits : 0 - 0 (1 bit)
access : read-write

PU1IE : PU1IE
bits : 1 - 1 (1 bit)
access : read-write

PU2IE : PU2IE
bits : 2 - 2 (1 bit)
access : read-write

PU3IE : PU3IE
bits : 3 - 3 (1 bit)
access : read-write

PU4IE : PU4IE
bits : 4 - 4 (1 bit)
access : read-write

PU5IE : PU5IE
bits : 5 - 5 (1 bit)
access : read-write

PU6IE : PU6IE
bits : 6 - 6 (1 bit)
access : read-write


CR

Port U Output Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU0C PU1C PU2C PU3C PU4C PU5C PU6C

PU0C : PU0C
bits : 0 - 0 (1 bit)
access : read-write

PU1C : PU1C
bits : 1 - 1 (1 bit)
access : read-write

PU2C : PU2C
bits : 2 - 2 (1 bit)
access : read-write

PU3C : PU3C
bits : 3 - 3 (1 bit)
access : read-write

PU4C : PU4C
bits : 4 - 4 (1 bit)
access : read-write

PU5C : PU5C
bits : 5 - 5 (1 bit)
access : read-write

PU6C : PU6C
bits : 6 - 6 (1 bit)
access : read-write


FR1

Port U Function Register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FR1 FR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU0F1 PU1F1 PU3F1 PU4F1 PU5F1 PU6F1

PU0F1 : PU0F1
bits : 0 - 0 (1 bit)
access : read-write

PU1F1 : PU1F1
bits : 1 - 1 (1 bit)
access : read-write

PU3F1 : PU3F1
bits : 3 - 3 (1 bit)
access : read-write

PU4F1 : PU4F1
bits : 4 - 4 (1 bit)
access : read-write

PU5F1 : PU5F1
bits : 5 - 5 (1 bit)
access : read-write

PU6F1 : PU6F1
bits : 6 - 6 (1 bit)
access : read-write


FR2

Port U Function Register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FR2 FR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU0F2 PU1F2 PU5F2 PU6F2

PU0F2 : PU0F2
bits : 0 - 0 (1 bit)
access : read-write

PU1F2 : PU1F2
bits : 1 - 1 (1 bit)
access : read-write

PU5F2 : PU5F2
bits : 5 - 5 (1 bit)
access : read-write

PU6F2 : PU6F2
bits : 6 - 6 (1 bit)
access : read-write



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