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TSEL

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR0

CR1

CR2

CR3


CR0

TRGSEL Control register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR0 CR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN0 INSEL0 EN1 INSEL1 EN2 INSEL2 EN3 INSEL3

EN0 : EN0
bits : 0 - 0 (1 bit)
access : read-write

INSEL0 : INSEL0
bits : 4 - 6 (3 bit)
access : read-write

EN1 : EN1
bits : 8 - 8 (1 bit)
access : read-write

INSEL1 : INSEL1
bits : 12 - 14 (3 bit)
access : read-write

EN2 : EN2
bits : 16 - 16 (1 bit)
access : read-write

INSEL2 : INSEL2
bits : 20 - 22 (3 bit)
access : read-write

EN3 : EN3
bits : 24 - 24 (1 bit)
access : read-write

INSEL3 : INSEL3
bits : 28 - 30 (3 bit)
access : read-write


CR1

TRGSEL Control register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN4 INSEL4 EN5 INSEL5 EN6 INSEL6 EN7 INSEL7

EN4 : EN4
bits : 0 - 0 (1 bit)
access : read-write

INSEL4 : INSEL4
bits : 4 - 6 (3 bit)
access : read-write

EN5 : EN5
bits : 8 - 8 (1 bit)
access : read-write

INSEL5 : INSEL5
bits : 12 - 14 (3 bit)
access : read-write

EN6 : EN6
bits : 16 - 16 (1 bit)
access : read-write

INSEL6 : INSEL6
bits : 20 - 22 (3 bit)
access : read-write

EN7 : EN7
bits : 24 - 24 (1 bit)
access : read-write

INSEL7 : INSEL7
bits : 28 - 30 (3 bit)
access : read-write


CR2

TSEL Control register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR2 CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN8 INSEL8 EN9 INSEL9 EN10 INSEL10 EN11 INSEL11

EN8 : EN8
bits : 0 - 0 (1 bit)
access : read-write

INSEL8 : INSEL8
bits : 4 - 6 (3 bit)
access : read-write

EN9 : EN9
bits : 8 - 8 (1 bit)
access : read-write

INSEL9 : INSEL9
bits : 12 - 14 (3 bit)
access : read-write

EN10 : EN10
bits : 16 - 16 (1 bit)
access : read-write

INSEL10 : INSEL10
bits : 20 - 22 (3 bit)
access : read-write

EN11 : EN11
bits : 24 - 24 (1 bit)
access : read-write

INSEL11 : INSEL11
bits : 28 - 30 (3 bit)
access : read-write


CR3

TRGSEL Control register 3
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR3 CR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN12 INSEL12 EN13 INSEL13 EN14 INSEL14 EN15 INSEL15

EN12 : EN12
bits : 0 - 0 (1 bit)
access : read-write

INSEL12 : INSEL12
bits : 4 - 6 (3 bit)
access : read-write

EN13 : EN13
bits : 8 - 8 (1 bit)
access : read-write

INSEL13 : INSEL13
bits : 12 - 14 (3 bit)
access : read-write

EN14 : EN14
bits : 16 - 16 (1 bit)
access : read-write

INSEL14 : INSEL14
bits : 20 - 22 (3 bit)
access : read-write

EN15 : EN15
bits : 24 - 24 (1 bit)
access : read-write

INSEL15 : INSEL15
bits : 28 - 30 (3 bit)
access : read-write



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