\n
address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection :
PWM control register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWMEN : Master enable for PWM
bits : 0 - 0 (1 bit)
Enumeration:
0 : DIS
Disable all PWM outputs
1 : EN
Enable all PWM outputs
End of enumeration elements list.
HMODE : Set to enable H-bridge mode
bits : 1 - 1 (1 bit)
DIR : Direction control when PWM is in H-bridge mode
bits : 2 - 2 (1 bit)
Enumeration:
0 : DIS
PWM2 and PWM3 act as output signals while PWM0 and PWM1 are held low
1 : EN
PWM0 and PWM1 act as output signals while PWM2 and PWM3 are held low
End of enumeration elements list.
LCOMP : Signal to load a new set of compare register values. In standard mode, this bit is cleared when the new values are loaded in the compare registers for all the channels. In H-bridge mode this bit does not get cleared, but the user must write a value of 1 to this bit in order for the compare registers to be loaded
bits : 3 - 3 (1 bit)
Enumeration:
0 : DIS
Use the values previously store in the compare and length registers
1 : EN
Load the internal compare registers with values stored in the PWMxCOMx and PWMxLEN registers
End of enumeration elements list.
HOFF : Set to turn off the high-side for Pair 0 and 1 when PWM is in H-bridge mode
bits : 4 - 4 (1 bit)
POINV : Set to invert PWM outputs for Pair 0 and 1 when PWM is in H-bridge mode
bits : 5 - 5 (1 bit)
PWMCMP : PWM Clock prescaler. Sets HCLK divider.
bits : 6 - 8 (3 bit)
Enumeration:
0 : DIV2
HCLK/2
1 : DIV4
HCLK/4
2 : DIV8
HCLK/8
3 : DIV16
HCLK/16
4 : DIV32
HCLK/32
5 : DIV64
HCLK/64
6 : DIV128
HCLK/128
7 : DIV256
HCLK/256
End of enumeration elements list.
ENA : When HOFF=0 and HMODE=1 this serves as enable for Pair 0 and 1
bits : 9 - 9 (1 bit)
Enumeration:
0 : DIS
Disable Pair 0 and 1
1 : EN
Enable Pair 0 and 1
End of enumeration elements list.
PWMIEN : Set to enable interrupts for PWM
bits : 10 - 10 (1 bit)
PWM1INV : Set to invert PWM1 output
bits : 11 - 11 (1 bit)
PWM3INV : Set to invert PWM3 output
bits : 12 - 12 (1 bit)
PWM5INV : Set to invert PWM5 output
bits : 13 - 13 (1 bit)
PWM7INV : Set to invert PWM7 output
bits : 14 - 14 (1 bit)
SYNC : Set to enable PWM synchronization from the SYNC pin of the PWM
bits : 15 - 15 (1 bit)
Enumeration:
0 : DIS
Ignore transition from the SYNC pin
1 : EN
All PWM counters are reset on the next clock cycle after detection of a falling edge from SYNC pin
End of enumeration elements list.
Compare Register 0 for PWM0 and PWM1
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COM0 : Compare register 0 data
bits : 0 - 15 (16 bit)
Compare Register 1 for PWM0 and PWM1
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COM1 : Compare register 1 data
bits : 0 - 15 (16 bit)
Compare Register 2 for PWM0 and PWM1
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COM2 : Compare register 2 data
bits : 0 - 15 (16 bit)
Period value register for PWM0 and PWM1
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEN : Period value
bits : 0 - 15 (16 bit)
Compare Register 0 for PWM2 and PWM3
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COM0 : Compare register 0 data
bits : 0 - 15 (16 bit)
Compare Register 1 for PWM2 and PWM3
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COM1 : Compare register 1 data
bits : 0 - 15 (16 bit)
Compare Register 2 for PWM2 and PWM3
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COM2 : Compare register 2 data
bits : 0 - 15 (16 bit)
Period value register for PWM2 and PWM3
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEN : Period value
bits : 0 - 15 (16 bit)
Compare Register 0 for PWM4 and PWM5
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COM0 : Compare register 0 data
bits : 0 - 15 (16 bit)
Compare Register 1 for PWM4 and PWM5
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COM1 : Compare register 1 data
bits : 0 - 15 (16 bit)
Compare Register 2 for PWM4 and PWM5
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COM2 : Compare register 2 data
bits : 0 - 15 (16 bit)
Period value register for PWM4 and PWM5
address_offset : 0x3C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEN : Period value
bits : 0 - 15 (16 bit)
ADC conversion start and trip control register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIP_EN : Set to enable PWM Trip functionality
bits : 6 - 6 (1 bit)
Compare Register 0 for PWM6 and PWM7
address_offset : 0x40 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COM0 : Compare register 0 data
bits : 0 - 15 (16 bit)
Compare Register 1 for PWM6 and PWM7
address_offset : 0x44 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COM1 : Compare register 1 data
bits : 0 - 15 (16 bit)
Compare Register 2 for PWM6 and PWM7
address_offset : 0x48 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COM2 : Compare register 2 data
bits : 0 - 15 (16 bit)
Period value register for PWM6 and PWM7
address_offset : 0x4C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEN : Period value
bits : 0 - 15 (16 bit)
Hardware trip configuration register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM0 : Write a 1 to clear latched IRQPWM0 interrupt. Returns 0 on reads.
bits : 0 - 0 (1 bit)
PWM1 : Write a 1 to clear latched IRQPWM1 interrupt. Returns 0 on reads.
bits : 1 - 1 (1 bit)
PWM2 : Write a 1 to clear latched IRQPWM2 interrupt. Returns 0 on reads.
bits : 2 - 2 (1 bit)
PWM3 : Write a 1 to clear latched IRQPWM3 interrupt. Returns 0 on reads.
bits : 3 - 3 (1 bit)
TRIP : Write a 1 to clear latched IRQPWMTrip interrupt. Returns 0 on reads.
bits : 4 - 4 (1 bit)
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