Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x40 byte (0x0)
mem_usage : registers
protection : not protected
Control A
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Enable
bits : 1 - 1 (1 bit)
CKEN0 : Clock Unit 0 Enable
bits : 2 - 2 (1 bit)
CKEN1 : Clock Unit 1 Enable
bits : 3 - 3 (1 bit)
SEREN0 : Serializer 0 Enable
bits : 4 - 4 (1 bit)
SEREN1 : Serializer 1 Enable
bits : 5 - 5 (1 bit)
Clock Unit n Control
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOTSIZE : Slot Size
bits : 0 - 1 (2 bit)
Enumeration: SLOTSIZESelect
0x0 : 8
8-bit Slot for Clock Unit n
0x1 : 16
16-bit Slot for Clock Unit n
0x2 : 24
24-bit Slot for Clock Unit n
0x3 : 32
32-bit Slot for Clock Unit n
End of enumeration elements list.
NBSLOTS : Number of Slots in Frame
bits : 2 - 4 (3 bit)
FSWIDTH : Frame Sync Width
bits : 5 - 6 (2 bit)
Enumeration: FSWIDTHSelect
0x0 : SLOT
Frame Sync Pulse is 1 Slot wide (default for I2S protocol)
0x1 : HALF
Frame Sync Pulse is half a Frame wide
0x2 : BIT
Frame Sync Pulse is 1 Bit wide
0x3 : BURST
Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested
End of enumeration elements list.
BITDELAY : Data Delay from Frame Sync
bits : 7 - 7 (1 bit)
Enumeration: BITDELAYSelect
0x0 : LJ
Left Justified (0 Bit Delay)
0x1 : I2S
I2S (1 Bit Delay)
End of enumeration elements list.
FSSEL : Frame Sync Select
bits : 8 - 8 (1 bit)
Enumeration: FSSELSelect
0x0 : SCKDIV
Divided Serial Clock n is used as Frame Sync n source
0x1 : FSPIN
FSn input pin is used as Frame Sync n source
End of enumeration elements list.
FSINV : Frame Sync Invert
bits : 11 - 11 (1 bit)
SCKSEL : Serial Clock Select
bits : 12 - 12 (1 bit)
Enumeration: SCKSELSelect
0x0 : MCKDIV
Divided Master Clock n is used as Serial Clock n source
0x1 : SCKPIN
SCKn input pin is used as Serial Clock n source
End of enumeration elements list.
MCKSEL : Master Clock Select
bits : 16 - 16 (1 bit)
Enumeration: MCKSELSelect
0x0 : GCLK
GCLK_I2S_n is used as Master Clock n source
0x1 : MCKPIN
MCKn input pin is used as Master Clock n source
End of enumeration elements list.
MCKEN : Master Clock Enable
bits : 18 - 18 (1 bit)
MCKDIV : Master Clock Division Factor
bits : 19 - 23 (5 bit)
MCKOUTDIV : Master Clock Output Division Factor
bits : 24 - 28 (5 bit)
FSOUTINV : Frame Sync Output Invert
bits : 29 - 29 (1 bit)
SCKOUTINV : Serial Clock Output Invert
bits : 30 - 30 (1 bit)
MCKOUTINV : Master Clock Output Invert
bits : 31 - 31 (1 bit)
Interrupt Enable Set
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXRDY0 : Receive Ready 0 Interrupt Enable
bits : 0 - 0 (1 bit)
RXRDY1 : Receive Ready 1 Interrupt Enable
bits : 1 - 1 (1 bit)
RXOR0 : Receive Overrun 0 Interrupt Enable
bits : 4 - 4 (1 bit)
RXOR1 : Receive Overrun 1 Interrupt Enable
bits : 5 - 5 (1 bit)
TXRDY0 : Transmit Ready 0 Interrupt Enable
bits : 8 - 8 (1 bit)
TXRDY1 : Transmit Ready 1 Interrupt Enable
bits : 9 - 9 (1 bit)
TXUR0 : Transmit Underrun 0 Interrupt Enable
bits : 12 - 12 (1 bit)
TXUR1 : Transmit Underrun 1 Interrupt Enable
bits : 13 - 13 (1 bit)
Interrupt Flag Status and Clear
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXRDY0 : Receive Ready 0
bits : 0 - 0 (1 bit)
RXRDY1 : Receive Ready 1
bits : 1 - 1 (1 bit)
RXOR0 : Receive Overrun 0
bits : 4 - 4 (1 bit)
RXOR1 : Receive Overrun 1
bits : 5 - 5 (1 bit)
TXRDY0 : Transmit Ready 0
bits : 8 - 8 (1 bit)
TXRDY1 : Transmit Ready 1
bits : 9 - 9 (1 bit)
TXUR0 : Transmit Underrun 0
bits : 12 - 12 (1 bit)
TXUR1 : Transmit Underrun 1
bits : 13 - 13 (1 bit)
Synchronization Status
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset Synchronization Status
bits : 0 - 0 (1 bit)
ENABLE : Enable Synchronization Status
bits : 1 - 1 (1 bit)
CKEN0 : Clock Unit 0 Enable Synchronization Status
bits : 2 - 2 (1 bit)
CKEN1 : Clock Unit 1 Enable Synchronization Status
bits : 3 - 3 (1 bit)
SEREN0 : Serializer 0 Enable Synchronization Status
bits : 4 - 4 (1 bit)
SEREN1 : Serializer 1 Enable Synchronization Status
bits : 5 - 5 (1 bit)
DATA0 : Data 0 Synchronization Status
bits : 8 - 8 (1 bit)
DATA1 : Data 1 Synchronization Status
bits : 9 - 9 (1 bit)
Serializer n Control
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SERMODE : Serializer Mode
bits : 0 - 1 (2 bit)
Enumeration: SERMODESelect
0x0 : RX
Receive
0x1 : TX
Transmit
0x2 : PDM2
Receive one PDM data on each serial clock edge
End of enumeration elements list.
TXDEFAULT : Line Default Line when Slot Disabled
bits : 2 - 3 (2 bit)
Enumeration: TXDEFAULTSelect
0x0 : ZERO
Output Default Value is 0
0x1 : ONE
Output Default Value is 1
0x3 : HIZ
Output Default Value is high impedance
End of enumeration elements list.
TXSAME : Transmit Data when Underrun
bits : 4 - 4 (1 bit)
Enumeration: TXSAMESelect
0x0 : ZERO
Zero data transmitted in case of underrun
0x1 : SAME
Last data transmitted in case of underrun
End of enumeration elements list.
CLKSEL : Clock Unit Selection
bits : 5 - 5 (1 bit)
Enumeration: CLKSELSelect
0x0 : CLK0
Use Clock Unit 0
0x1 : CLK1
Use Clock Unit 1
End of enumeration elements list.
SLOTADJ : Data Slot Formatting Adjust
bits : 7 - 7 (1 bit)
Enumeration: SLOTADJSelect
0x0 : RIGHT
Data is right adjusted in slot
0x1 : LEFT
Data is left adjusted in slot
End of enumeration elements list.
DATASIZE : Data Word Size
bits : 8 - 10 (3 bit)
Enumeration: DATASIZESelect
0x0 : 32
32 bits
0x1 : 24
24 bits
0x2 : 20
20 bits
0x3 : 18
18 bits
0x4 : 16
16 bits
0x5 : 16C
16 bits compact stereo
0x6 : 8
8 bits
0x7 : 8C
8 bits compact stereo
End of enumeration elements list.
WORDADJ : Data Word Formatting Adjust
bits : 12 - 12 (1 bit)
Enumeration: WORDADJSelect
0x0 : RIGHT
Data is right adjusted in word
0x1 : LEFT
Data is left adjusted in word
End of enumeration elements list.
EXTEND : Data Formatting Bit Extension
bits : 13 - 14 (2 bit)
Enumeration: EXTENDSelect
0x0 : ZERO
Extend with zeroes
0x1 : ONE
Extend with ones
0x2 : MSBIT
Extend with Most Significant Bit
0x3 : LSBIT
Extend with Least Significant Bit
End of enumeration elements list.
BITREV : Data Formatting Bit Reverse
bits : 15 - 15 (1 bit)
Enumeration: BITREVSelect
0x0 : MSBIT
Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)
0x1 : LSBIT
Transfer Data Least Significant Bit (LSB) first
End of enumeration elements list.
SLOTDIS0 : Slot 0 Disabled for this Serializer
bits : 16 - 16 (1 bit)
SLOTDIS1 : Slot 1 Disabled for this Serializer
bits : 17 - 17 (1 bit)
SLOTDIS2 : Slot 2 Disabled for this Serializer
bits : 18 - 18 (1 bit)
SLOTDIS3 : Slot 3 Disabled for this Serializer
bits : 19 - 19 (1 bit)
SLOTDIS4 : Slot 4 Disabled for this Serializer
bits : 20 - 20 (1 bit)
SLOTDIS5 : Slot 5 Disabled for this Serializer
bits : 21 - 21 (1 bit)
SLOTDIS6 : Slot 6 Disabled for this Serializer
bits : 22 - 22 (1 bit)
SLOTDIS7 : Slot 7 Disabled for this Serializer
bits : 23 - 23 (1 bit)
MONO : Mono Mode
bits : 24 - 24 (1 bit)
Enumeration: MONOSelect
0x0 : STEREO
Normal mode
0x1 : MONO
Left channel data is duplicated to right channel
End of enumeration elements list.
DMA : Single or Multiple DMA Channels
bits : 25 - 25 (1 bit)
Enumeration: DMASelect
0x0 : SINGLE
Single DMA channel
0x1 : MULTIPLE
One DMA channel per data channel
End of enumeration elements list.
RXLOOP : Loop-back Test Mode
bits : 26 - 26 (1 bit)
Data n
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Sample Data
bits : 0 - 31 (32 bit)
Serializer n Control
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SERMODE : Serializer Mode
bits : 0 - 1 (2 bit)
Enumeration: SERMODESelect
0x0 : RX
Receive
0x1 : TX
Transmit
0x2 : PDM2
Receive one PDM data on each serial clock edge
End of enumeration elements list.
TXDEFAULT : Line Default Line when Slot Disabled
bits : 2 - 3 (2 bit)
Enumeration: TXDEFAULTSelect
0x0 : ZERO
Output Default Value is 0
0x1 : ONE
Output Default Value is 1
0x3 : HIZ
Output Default Value is high impedance
End of enumeration elements list.
TXSAME : Transmit Data when Underrun
bits : 4 - 4 (1 bit)
Enumeration: TXSAMESelect
0x0 : ZERO
Zero data transmitted in case of underrun
0x1 : SAME
Last data transmitted in case of underrun
End of enumeration elements list.
CLKSEL : Clock Unit Selection
bits : 5 - 5 (1 bit)
Enumeration: CLKSELSelect
0x0 : CLK0
Use Clock Unit 0
0x1 : CLK1
Use Clock Unit 1
End of enumeration elements list.
SLOTADJ : Data Slot Formatting Adjust
bits : 7 - 7 (1 bit)
Enumeration: SLOTADJSelect
0x0 : RIGHT
Data is right adjusted in slot
0x1 : LEFT
Data is left adjusted in slot
End of enumeration elements list.
DATASIZE : Data Word Size
bits : 8 - 10 (3 bit)
Enumeration: DATASIZESelect
0x0 : 32
32 bits
0x1 : 24
24 bits
0x2 : 20
20 bits
0x3 : 18
18 bits
0x4 : 16
16 bits
0x5 : 16C
16 bits compact stereo
0x6 : 8
8 bits
0x7 : 8C
8 bits compact stereo
End of enumeration elements list.
WORDADJ : Data Word Formatting Adjust
bits : 12 - 12 (1 bit)
Enumeration: WORDADJSelect
0x0 : RIGHT
Data is right adjusted in word
0x1 : LEFT
Data is left adjusted in word
End of enumeration elements list.
EXTEND : Data Formatting Bit Extension
bits : 13 - 14 (2 bit)
Enumeration: EXTENDSelect
0x0 : ZERO
Extend with zeroes
0x1 : ONE
Extend with ones
0x2 : MSBIT
Extend with Most Significant Bit
0x3 : LSBIT
Extend with Least Significant Bit
End of enumeration elements list.
BITREV : Data Formatting Bit Reverse
bits : 15 - 15 (1 bit)
Enumeration: BITREVSelect
0x0 : MSBIT
Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)
0x1 : LSBIT
Transfer Data Least Significant Bit (LSB) first
End of enumeration elements list.
SLOTDIS0 : Slot 0 Disabled for this Serializer
bits : 16 - 16 (1 bit)
SLOTDIS1 : Slot 1 Disabled for this Serializer
bits : 17 - 17 (1 bit)
SLOTDIS2 : Slot 2 Disabled for this Serializer
bits : 18 - 18 (1 bit)
SLOTDIS3 : Slot 3 Disabled for this Serializer
bits : 19 - 19 (1 bit)
SLOTDIS4 : Slot 4 Disabled for this Serializer
bits : 20 - 20 (1 bit)
SLOTDIS5 : Slot 5 Disabled for this Serializer
bits : 21 - 21 (1 bit)
SLOTDIS6 : Slot 6 Disabled for this Serializer
bits : 22 - 22 (1 bit)
SLOTDIS7 : Slot 7 Disabled for this Serializer
bits : 23 - 23 (1 bit)
MONO : Mono Mode
bits : 24 - 24 (1 bit)
Enumeration: MONOSelect
0x0 : STEREO
Normal mode
0x1 : MONO
Left channel data is duplicated to right channel
End of enumeration elements list.
DMA : Single or Multiple DMA Channels
bits : 25 - 25 (1 bit)
Enumeration: DMASelect
0x0 : SINGLE
Single DMA channel
0x1 : MULTIPLE
One DMA channel per data channel
End of enumeration elements list.
RXLOOP : Loop-back Test Mode
bits : 26 - 26 (1 bit)
Clock Unit n Control
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOTSIZE : Slot Size
bits : 0 - 1 (2 bit)
Enumeration: SLOTSIZESelect
0x0 : 8
8-bit Slot for Clock Unit n
0x1 : 16
16-bit Slot for Clock Unit n
0x2 : 24
24-bit Slot for Clock Unit n
0x3 : 32
32-bit Slot for Clock Unit n
End of enumeration elements list.
NBSLOTS : Number of Slots in Frame
bits : 2 - 4 (3 bit)
FSWIDTH : Frame Sync Width
bits : 5 - 6 (2 bit)
Enumeration: FSWIDTHSelect
0x0 : SLOT
Frame Sync Pulse is 1 Slot wide (default for I2S protocol)
0x1 : HALF
Frame Sync Pulse is half a Frame wide
0x2 : BIT
Frame Sync Pulse is 1 Bit wide
0x3 : BURST
Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested
End of enumeration elements list.
BITDELAY : Data Delay from Frame Sync
bits : 7 - 7 (1 bit)
Enumeration: BITDELAYSelect
0x0 : LJ
Left Justified (0 Bit Delay)
0x1 : I2S
I2S (1 Bit Delay)
End of enumeration elements list.
FSSEL : Frame Sync Select
bits : 8 - 8 (1 bit)
Enumeration: FSSELSelect
0x0 : SCKDIV
Divided Serial Clock n is used as Frame Sync n source
0x1 : FSPIN
FSn input pin is used as Frame Sync n source
End of enumeration elements list.
FSINV : Frame Sync Invert
bits : 11 - 11 (1 bit)
SCKSEL : Serial Clock Select
bits : 12 - 12 (1 bit)
Enumeration: SCKSELSelect
0x0 : MCKDIV
Divided Master Clock n is used as Serial Clock n source
0x1 : SCKPIN
SCKn input pin is used as Serial Clock n source
End of enumeration elements list.
MCKSEL : Master Clock Select
bits : 16 - 16 (1 bit)
Enumeration: MCKSELSelect
0x0 : GCLK
GCLK_I2S_n is used as Master Clock n source
0x1 : MCKPIN
MCKn input pin is used as Master Clock n source
End of enumeration elements list.
MCKEN : Master Clock Enable
bits : 18 - 18 (1 bit)
MCKDIV : Master Clock Division Factor
bits : 19 - 23 (5 bit)
MCKOUTDIV : Master Clock Output Division Factor
bits : 24 - 28 (5 bit)
FSOUTINV : Frame Sync Output Invert
bits : 29 - 29 (1 bit)
SCKOUTINV : Serial Clock Output Invert
bits : 30 - 30 (1 bit)
MCKOUTINV : Master Clock Output Invert
bits : 31 - 31 (1 bit)
Data n
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Sample Data
bits : 0 - 31 (32 bit)
Interrupt Enable Clear
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXRDY0 : Receive Ready 0 Interrupt Enable
bits : 0 - 0 (1 bit)
RXRDY1 : Receive Ready 1 Interrupt Enable
bits : 1 - 1 (1 bit)
RXOR0 : Receive Overrun 0 Interrupt Enable
bits : 4 - 4 (1 bit)
RXOR1 : Receive Overrun 1 Interrupt Enable
bits : 5 - 5 (1 bit)
TXRDY0 : Transmit Ready 0 Interrupt Enable
bits : 8 - 8 (1 bit)
TXRDY1 : Transmit Ready 1 Interrupt Enable
bits : 9 - 9 (1 bit)
TXUR0 : Transmit Underrun 0 Interrupt Enable
bits : 12 - 12 (1 bit)
TXUR1 : Transmit Underrun 1 Interrupt Enable
bits : 13 - 13 (1 bit)
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