Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection :
16-bit load value register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOAD : Load value
bits : 0 - 15 (16 bit)
Capture register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAP : 16-bit captured value
bits : 0 - 15 (16 bit)
Status register
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TMOUT : Timeout event occurred
bits : 0 - 0 (1 bit)
Enumeration:
0 : CLR
No timeout event has occurred
1 : SET
A timeout event has occurred
End of enumeration elements list.
CAP : Capture event pending
bits : 1 - 1 (1 bit)
Enumeration:
0 : CLR
No capture event is pending
1 : SET
A capture event is pending
End of enumeration elements list.
BUSY : Timer Busy
bits : 6 - 6 (1 bit)
Enumeration:
0 : CLR
Timer ready to receive commands to TCON
1 : SET
Timer not ready to receive commands to TCON
End of enumeration elements list.
PDOK : TCLRI synchronization
bits : 7 - 7 (1 bit)
Enumeration:
0 : CLR
The interrupt is cleared in the timer clock domain
1 : SET
TCLRI[0] is being updated in the timer clock domain
End of enumeration elements list.
16-bit timer value register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VAL : Current count
bits : 0 - 15 (16 bit)
Control register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRE : Prescaler
bits : 0 - 1 (2 bit)
Enumeration:
0 : DIV1
source_clock / [1 or 4]
1 : DIV16
source_clock / 16
2 : DIV256
source_clock / 256
3 : DIV32768
source_clock / 32,768
End of enumeration elements list.
UP : Count up
bits : 2 - 2 (1 bit)
Enumeration:
0 : DIS
Timer is set to count down (default)
1 : EN
Timer is set to count up
End of enumeration elements list.
MOD : Timer mode
bits : 3 - 3 (1 bit)
Enumeration:
0 : FREERUN
Timer runs in free running mode
1 : PERIODIC
Timer runs in periodic mode (default)
End of enumeration elements list.
ENABLE : Timer enable
bits : 4 - 4 (1 bit)
Enumeration:
0 : DIS
Timer is disabled (default)
1 : EN
Timer is enabled
End of enumeration elements list.
CLK : Clock select
bits : 5 - 6 (2 bit)
Enumeration:
0 : PCLK
PCLK.
1 : HCLK
HCLK.
2 : LFOSC
32 KHz OSC
3 : HFXTAL
16 MHz OSC or XTAL (Dependent on CLKCON0.11)
End of enumeration elements list.
RLD : Reload control
bits : 7 - 7 (1 bit)
Enumeration:
1 : EN
Resets the up/down counter when TCLRI[0] is set
0 : DIS
Up/Down counter is only reset on a timeout event
End of enumeration elements list.
EVENT : Event select range
bits : 8 - 11 (4 bit)
EVENTEN : Event select
bits : 12 - 12 (1 bit)
Enumeration:
0 : DIS
Events will not be captured
1 : EN
Events will be captured
End of enumeration elements list.
Clear interrupt register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TMOUT : Clear timeout interrupt
bits : 0 - 0 (1 bit)
Enumeration:
1 : CLR
Clears the timeout interrupt
End of enumeration elements list.
CAP : Clear captured event interrupt
bits : 1 - 1 (1 bit)
Enumeration:
1 : CLR
Clear the capture event interrupt
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.