\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
DMA Interrupt status register (DMA_IF)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
GIFC1 : Channel 1 Global interrupt flag
bits : 0 - 0 (1 bit)
EOTTFC1 : Channel 1 Transfer Complete flag
bits : 1 - 1 (1 bit)
MOTIFC1 : Channel 1 Half Transfer Complete flag
bits : 2 - 2 (1 bit)
FOTIFC1 : Channel 1 Transfer Error flag
bits : 3 - 3 (1 bit)
GIFC2 : Channel 2 Global interrupt flag
bits : 4 - 4 (1 bit)
EOTTFC2 : Channel 2 Transfer Complete flag
bits : 5 - 5 (1 bit)
MOTIFC2 : Channel 2 Half Transfer Complete flag
bits : 6 - 6 (1 bit)
FOTIFC2 : Channel 2 Transfer Error flag
bits : 7 - 7 (1 bit)
GIFC3 : Channel 3 Global interrupt flag
bits : 8 - 8 (1 bit)
EOTTFC3 : Channel 3 Transfer Complete flag
bits : 9 - 9 (1 bit)
MOTIFC3 : Channel 3 Half Transfer Complete flag
bits : 10 - 10 (1 bit)
FOTIFC3 : Channel 3 Transfer Error flag
bits : 11 - 11 (1 bit)
GIFC4 : Channel 4 Global interrupt flag
bits : 12 - 12 (1 bit)
EOTTFC4 : Channel 4 Transfer Complete flag
bits : 13 - 13 (1 bit)
MOTIFC4 : Channel 4 Half Transfer Complete flag
bits : 14 - 14 (1 bit)
FOTIFC4 : Channel 4 Transfer Error flag
bits : 15 - 15 (1 bit)
GIFC5 : Channel 5 Global interrupt flag
bits : 16 - 16 (1 bit)
EOTTFC5 : Channel 5 Transfer Complete flag
bits : 17 - 17 (1 bit)
MOTIFC5 : Channel 5 Half Transfer Complete flag
bits : 18 - 18 (1 bit)
FOTIFC5 : Channel 5 Transfer Error flag
bits : 19 - 19 (1 bit)
GIFC6 : Channel 6 Global interrupt flag
bits : 20 - 20 (1 bit)
EOTTFC6 : Channel 6 Transfer Complete flag
bits : 21 - 21 (1 bit)
MOTIFC6 : Channel 6 Half Transfer Complete flag
bits : 22 - 22 (1 bit)
FOTIFC6 : Channel 6 Transfer Error flag
bits : 23 - 23 (1 bit)
GIFC7 : Channel 7 Global interrupt flag
bits : 24 - 24 (1 bit)
EOTTFC7 : Channel 7 Transfer Complete flag
bits : 25 - 25 (1 bit)
MOTIFC7 : Channel 7 Half Transfer Complete flag
bits : 26 - 26 (1 bit)
FOTIFC7 : Channel 7 Transfer Error flag
bits : 27 - 27 (1 bit)
DMA channel 1 peripheral address register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PAC : Peripheral address
bits : 0 - 31 (32 bit)
DMA channel 1 memory address register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC : Memory address
bits : 0 - 31 (32 bit)
DMA channel 2 configuration register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Channel enable
bits : 0 - 0 (1 bit)
EOTIEN : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)
MOTIEN : Half Transfer interrupt enable
bits : 2 - 2 (1 bit)
FOTIEN : Transfer error interrupt enable
bits : 3 - 3 (1 bit)
DOT : Data transfer direction
bits : 4 - 4 (1 bit)
LOOP : Circular mode
bits : 5 - 5 (1 bit)
PLOOP : Peripheral increment mode
bits : 6 - 6 (1 bit)
MLOOP : Memory increment mode
bits : 7 - 7 (1 bit)
PWID : Peripheral size
bits : 8 - 9 (2 bit)
MWID : Memory size
bits : 10 - 11 (2 bit)
PL : Channel Priority level
bits : 12 - 13 (2 bit)
M2MEN : Memory to memory mode
bits : 14 - 14 (1 bit)
DMA channel 2 number of data register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTTC : Number of data to transfer
bits : 0 - 15 (16 bit)
DMA channel 2 peripheral address register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PAC : Peripheral address
bits : 0 - 31 (32 bit)
DMA channel 2 memory address register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC : Memory address
bits : 0 - 31 (32 bit)
DMA channel 3 configuration register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Channel enable
bits : 0 - 0 (1 bit)
EOTIEN : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)
MOTIEN : Half Transfer interrupt enable
bits : 2 - 2 (1 bit)
FOTIEN : Transfer error interrupt enable
bits : 3 - 3 (1 bit)
DOT : Data transfer direction
bits : 4 - 4 (1 bit)
LOOP : Circular mode
bits : 5 - 5 (1 bit)
PLOOP : Peripheral increment mode
bits : 6 - 6 (1 bit)
MLOOP : Memory increment mode
bits : 7 - 7 (1 bit)
PWID : Peripheral size
bits : 8 - 9 (2 bit)
MWID : Memory size
bits : 10 - 11 (2 bit)
PL : Channel Priority level
bits : 12 - 13 (2 bit)
M2MEN : Memory to memory mode
bits : 14 - 14 (1 bit)
DMA channel 3 number of data register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTTC : Number of data to transfer
bits : 0 - 15 (16 bit)
DMA channel 3 peripheral address register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PAC : Peripheral address
bits : 0 - 31 (32 bit)
DMA channel 3 memory address register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC : Memory address
bits : 0 - 31 (32 bit)
DMA Interrupt reset register (DMA_IFR)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RGIFC1 : Channel 1 Global interrupt resetr
bits : 0 - 0 (1 bit)
REOTIFC1 : Channel 1 Transfer Complete reset
bits : 1 - 1 (1 bit)
RMOTIFC1 : Channel 1 Half Transfer reset
bits : 2 - 2 (1 bit)
RFOTIFC1 : Channel 1 Transfer Error reset
bits : 3 - 3 (1 bit)
RGIFC2 : Channel 2 Global interrupt reset
bits : 4 - 4 (1 bit)
REOTIFC2 : Channel 2 Transfer Complete reset
bits : 5 - 5 (1 bit)
RMOTIFC2 : Channel 2 Half Transfer reset
bits : 6 - 6 (1 bit)
RFOTIFC2 : Channel 2 Transfer Error reset
bits : 7 - 7 (1 bit)
RGIFC3 : Channel 3 Global interrupt reset
bits : 8 - 8 (1 bit)
REOTIFC3 : Channel 3 Transfer Complete reset
bits : 9 - 9 (1 bit)
RMOTIFC3 : Channel 3 Half Transfer reset
bits : 10 - 10 (1 bit)
RFOTIFC3 : Channel 3 Transfer Error reset
bits : 11 - 11 (1 bit)
RGIFC4 : Channel 4 Global interrupt reset
bits : 12 - 12 (1 bit)
REOTIFC4 : Channel 4 Transfer Complete reset
bits : 13 - 13 (1 bit)
RMOTIFC4 : Channel 4 Half Transfer reset
bits : 14 - 14 (1 bit)
RFOTIFC4 : Channel 4 Transfer Error reset
bits : 15 - 15 (1 bit)
RGIFC5 : Channel 5 Global interrupt reset
bits : 16 - 16 (1 bit)
REOTIFC5 : Channel 5 Transfer Complete reset
bits : 17 - 17 (1 bit)
RMOTIFC5 : Channel 5 Half Transfer reset
bits : 18 - 18 (1 bit)
RFOTIFC5 : Channel 5 Transfer Error reset
bits : 19 - 19 (1 bit)
RGIFC6 : Channel 6 Global interrupt reset
bits : 20 - 20 (1 bit)
REOTIFC6 : Channel 6 Transfer Complete reset
bits : 21 - 21 (1 bit)
RMOTIFC6 : Channel 6 Half Transfer reset
bits : 22 - 22 (1 bit)
RFOTIFC6 : Channel 6 Transfer Error reset
bits : 23 - 23 (1 bit)
RGIFC7 : Channel 7 Global interrupt reset
bits : 24 - 24 (1 bit)
REOTIFC7 : Channel 7 Transfer Complete reset
bits : 25 - 25 (1 bit)
RMOTIFC7 : Channel 7 Half Transfer reset
bits : 26 - 26 (1 bit)
RFOTIFC7 : Channel 7 Transfer Error reset
bits : 27 - 27 (1 bit)
DMA channel 4 configuration register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Channel enable
bits : 0 - 0 (1 bit)
EOTIEN : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)
MOTIEN : Half Transfer interrupt enable
bits : 2 - 2 (1 bit)
FOTIEN : Transfer error interrupt enable
bits : 3 - 3 (1 bit)
DOT : Data transfer direction
bits : 4 - 4 (1 bit)
LOOP : Circular mode
bits : 5 - 5 (1 bit)
PLOOP : Peripheral increment mode
bits : 6 - 6 (1 bit)
MLOOP : Memory increment mode
bits : 7 - 7 (1 bit)
PWID : Peripheral size
bits : 8 - 9 (2 bit)
MWID : Memory size
bits : 10 - 11 (2 bit)
PL : Channel Priority level
bits : 12 - 13 (2 bit)
M2MEN : Memory to memory mode
bits : 14 - 14 (1 bit)
DMA channel 4 number of data register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTTC : Number of data to transfer
bits : 0 - 15 (16 bit)
DMA channel 4 peripheral address register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PAC : Peripheral address
bits : 0 - 31 (32 bit)
DMA channel 4 memory address register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC : Memory address
bits : 0 - 31 (32 bit)
DMA channel 5 configuration register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Channel enable
bits : 0 - 0 (1 bit)
EOTIEN : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)
MOTIEN : Half Transfer interrupt enable
bits : 2 - 2 (1 bit)
FOTIEN : Transfer error interrupt enable
bits : 3 - 3 (1 bit)
DOT : Data transfer direction
bits : 4 - 4 (1 bit)
LOOP : Circular mode
bits : 5 - 5 (1 bit)
PLOOP : Peripheral increment mode
bits : 6 - 6 (1 bit)
MLOOP : Memory increment mode
bits : 7 - 7 (1 bit)
PWID : Peripheral size
bits : 8 - 9 (2 bit)
MWID : Memory size
bits : 10 - 11 (2 bit)
PL : Channel Priority level
bits : 12 - 13 (2 bit)
M2MEN : Memory to memory mode
bits : 14 - 14 (1 bit)
DMA channel 5 number of data register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTTC : Number of data to transfer
bits : 0 - 15 (16 bit)
DMA channel 5 peripheral address register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PAC : Peripheral address
bits : 0 - 31 (32 bit)
DMA channel 5 memory address register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC : Memory address
bits : 0 - 31 (32 bit)
DMA channel 6 configuration register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Channel enable
bits : 0 - 0 (1 bit)
EOTIEN : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)
MOTIEN : Half Transfer interrupt enable
bits : 2 - 2 (1 bit)
FOTIEN : Transfer error interrupt enable
bits : 3 - 3 (1 bit)
DOT : Data transfer direction
bits : 4 - 4 (1 bit)
LOOP : Circular mode
bits : 5 - 5 (1 bit)
PLOOP : Peripheral increment mode
bits : 6 - 6 (1 bit)
MLOOP : Memory increment mode
bits : 7 - 7 (1 bit)
PWID : Peripheral size
bits : 8 - 9 (2 bit)
MWID : Memory size
bits : 10 - 11 (2 bit)
PL : Channel Priority level
bits : 12 - 13 (2 bit)
M2MEN : Memory to memory mode
bits : 14 - 14 (1 bit)
DMA channel 6 number of data register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTTC : Number of data to transfer
bits : 0 - 15 (16 bit)
DMA channel 6 peripheral address register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PAC : Peripheral address
bits : 0 - 31 (32 bit)
DMA channel 6 memory address register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC : Memory address
bits : 0 - 31 (32 bit)
DMA channel 1 configuration register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Channel enable
bits : 0 - 0 (1 bit)
EOTIEN : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)
MOTIEN : Half Transfer interrupt enable
bits : 2 - 2 (1 bit)
FOTIEN : Transfer error interrupt enable
bits : 3 - 3 (1 bit)
DOT : Data transfer direction
bits : 4 - 4 (1 bit)
LOOP : Circular mode
bits : 5 - 5 (1 bit)
PLOOP : Peripheral increment mode
bits : 6 - 6 (1 bit)
MLOOP : Memory increment mode
bits : 7 - 7 (1 bit)
PWID : Peripheral size
bits : 8 - 9 (2 bit)
MWID : Memory size
bits : 10 - 11 (2 bit)
PL : Channel Priority level
bits : 12 - 13 (2 bit)
M2MEN : Memory to memory mode
bits : 14 - 14 (1 bit)
DMA channel 7 configuration register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Channel enable
bits : 0 - 0 (1 bit)
EOTIEN : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)
MOTIEN : Half Transfer interrupt enable
bits : 2 - 2 (1 bit)
FOTIEN : Transfer error interrupt enable
bits : 3 - 3 (1 bit)
DOT : Data transfer direction
bits : 4 - 4 (1 bit)
LOOP : Circular mode
bits : 5 - 5 (1 bit)
PLOOP : Peripheral increment mode
bits : 6 - 6 (1 bit)
MLOOP : Memory increment mode
bits : 7 - 7 (1 bit)
PWID : Peripheral size
bits : 8 - 9 (2 bit)
MWID : Memory size
bits : 10 - 11 (2 bit)
PL : Channel Priority level
bits : 12 - 13 (2 bit)
M2MEN : Memory to memory mode
bits : 14 - 14 (1 bit)
DMA channel 7 number of data register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTTC : Number of data to transfer
bits : 0 - 15 (16 bit)
DMA channel 7 peripheral address register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PAC : Peripheral address
bits : 0 - 31 (32 bit)
DMA channel 7 memory address register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC : Memory address
bits : 0 - 31 (32 bit)
DMA channel 1 number of data register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTTC : Number of data to transfer
bits : 0 - 15 (16 bit)
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.