\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTEN : Counter enable
bits : 0 - 0 (1 bit)
NGUE : Update disable
bits : 1 - 1 (1 bit)
UES : Update request source
bits : 2 - 2 (1 bit)
SPMEN : One-pulse mode
bits : 3 - 3 (1 bit)
CNTDIR : Direction
bits : 4 - 4 (1 bit)
CNTMODE : Center-aligned mode selection
bits : 5 - 6 (2 bit)
ARBEN : Auto-reload preload enable
bits : 7 - 7 (1 bit)
CKDR : Clock division
bits : 8 - 9 (2 bit)
status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UDIF : Update interrupt flag
bits : 0 - 0 (1 bit)
CH1CCIF : Capture/compare 1 interrupt flag
bits : 1 - 1 (1 bit)
CH2CCIF : Capture/Compare 2 interrupt flag
bits : 2 - 2 (1 bit)
CH3CCIF : Capture/Compare 3 interrupt flag
bits : 3 - 3 (1 bit)
CH4CCIF : Capture/Compare 4 interrupt flag
bits : 4 - 4 (1 bit)
CCUIF : COM interrupt flag
bits : 5 - 5 (1 bit)
TRGIF : Trigger interrupt flag
bits : 6 - 6 (1 bit)
BRKIF : Break interrupt flag
bits : 7 - 7 (1 bit)
CH1RCF : Capture/Compare 1 overcapture flag
bits : 9 - 9 (1 bit)
CH2RCF : Capture/compare 2 overcapture flag
bits : 10 - 10 (1 bit)
CH3RCF : Capture/Compare 3 overcapture flag
bits : 11 - 11 (1 bit)
CH4RCF : Capture/Compare 4 overcapture flag
bits : 12 - 12 (1 bit)
event generation register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UEG : Update generation
bits : 0 - 0 (1 bit)
CH1CCG : Capture/compare 1 generation
bits : 1 - 1 (1 bit)
CH2CCG : Capture/compare 2 generation
bits : 2 - 2 (1 bit)
CH3CCG : Capture/compare 3 generation
bits : 3 - 3 (1 bit)
CH4CCG : Capture/compare 4 generation
bits : 4 - 4 (1 bit)
CCUEG : Capture/Compare control update generation
bits : 5 - 5 (1 bit)
TEG : Trigger generation
bits : 6 - 6 (1 bit)
BEG : Break generation
bits : 7 - 7 (1 bit)
capture/compare mode register 1 (Compare mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC1MS : Capture/Compare 1 selection
bits : 0 - 1 (2 bit)
OC1FEN : Output Compare 1 fast enable
bits : 2 - 2 (1 bit)
OC1BEN : Output Compare 1 preload enable
bits : 3 - 3 (1 bit)
OC1MS : Output Compare 1 mode
bits : 4 - 6 (3 bit)
OC1CEN : Output Compare 1 clear enable
bits : 7 - 7 (1 bit)
CC2MS : Capture/Compare 2 selection
bits : 8 - 9 (2 bit)
OC2FEN : Output Compare 2 fast enable
bits : 10 - 10 (1 bit)
OC2BEN : Output Compare 2 preload enable
bits : 11 - 11 (1 bit)
OC2MS : Output Compare 2 mode
bits : 12 - 14 (3 bit)
OC2CEN : Output Compare 2 clear enable
bits : 15 - 15 (1 bit)
capture/compare mode register 1 (Capture mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCM1
reset_Mask : 0x0
CC1MS : Capture/Compare 1 selection
bits : 0 - 1 (2 bit)
IC1D : Input capture 1 prescaler
bits : 2 - 3 (2 bit)
IC1FC : Input capture 1 filter
bits : 4 - 7 (4 bit)
CC2MS : Capture/Compare 2 selection
bits : 8 - 9 (2 bit)
IC2D : Input capture 2 prescaler
bits : 10 - 11 (2 bit)
IC2FC : Input capture 2 filter
bits : 12 - 15 (4 bit)
capture/compare mode register 2 (Compare mode)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC3MS : Capture/Compare 3 selection
bits : 0 - 1 (2 bit)
OC3FEN : Output compare 3 fast enable
bits : 2 - 2 (1 bit)
OC3BEN : Output compare 3 preload enable
bits : 3 - 3 (1 bit)
OC3MS : Output compare 3 mode
bits : 4 - 6 (3 bit)
OC3CEN : Output compare 3 clear enable
bits : 7 - 7 (1 bit)
CC4MS : Capture/Compare 4 selection
bits : 8 - 9 (2 bit)
OC4FEN : Output compare 4 fast enable
bits : 10 - 10 (1 bit)
OC4BEN : Output compare 4 preload enable
bits : 11 - 11 (1 bit)
OC4MS : Output compare 4 mode
bits : 12 - 14 (3 bit)
OC4CEN : Output compare 4 clear enable
bits : 15 - 15 (1 bit)
capture/compare mode register 2 (Capture mode)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCM2
reset_Mask : 0x0
CC3MS : Capture/compare 3 selection
bits : 0 - 1 (2 bit)
IC3D : Input capture 3 prescaler
bits : 2 - 3 (2 bit)
IC3FC : Input capture 3 filter
bits : 4 - 7 (4 bit)
CC4MS : Capture/Compare 4 selection
bits : 8 - 9 (2 bit)
IC4D : Input capture 4 prescaler
bits : 10 - 11 (2 bit)
IC4FC : Input capture 4 filter
bits : 12 - 15 (4 bit)
capture/compare enable register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH1CCEN : Capture/Compare 1 output enable
bits : 0 - 0 (1 bit)
CH1CCP : Capture/Compare 1 output Polarity
bits : 1 - 1 (1 bit)
CH1OCNEN : Capture/Compare 1 complementary output enable
bits : 2 - 2 (1 bit)
CH1OCNP : Capture/Compare 1 output Polarity
bits : 3 - 3 (1 bit)
CH2CCEN : Capture/Compare 2 output enable
bits : 4 - 4 (1 bit)
CH2CCP : Capture/Compare 2 output Polarity
bits : 5 - 5 (1 bit)
CH2OCNEN : Capture/Compare 2 complementary output enable
bits : 6 - 6 (1 bit)
CH2OCNP : Capture/Compare 2 output Polarity
bits : 7 - 7 (1 bit)
CH3CCEN : Capture/Compare 3 output enable
bits : 8 - 8 (1 bit)
CH3CCP : Capture/Compare 3 output Polarity
bits : 9 - 9 (1 bit)
CH3OCNEN : Capture/Compare 3 complementary output enable
bits : 10 - 10 (1 bit)
CH3OCNP : Capture/Compare 3 output Polarity
bits : 11 - 11 (1 bit)
CH4CCEN : Capture/Compare 4 output enable
bits : 12 - 12 (1 bit)
CH4CCP : Capture/Compare 3 output Polarity
bits : 13 - 13 (1 bit)
counter
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : counter value
bits : 0 - 15 (16 bit)
prescaler
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Prescaler value
bits : 0 - 15 (16 bit)
auto-reload register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AOUTORLD : Auto-reload value
bits : 0 - 15 (16 bit)
Repeat count register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REPCNT : Auto-reload value
bits : 0 - 15 (16 bit)
capture/compare register 1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH1CC : Capture/Compare 1 value
bits : 0 - 15 (16 bit)
capture/compare register 2
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH2CC : Capture/Compare 2 value
bits : 0 - 15 (16 bit)
capture/compare register 3
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH3CC : Capture/Compare 3 value
bits : 0 - 15 (16 bit)
control register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCBEN : Capture/compare preloaded control
bits : 0 - 0 (1 bit)
CCUS : Capture/compare control update selection
bits : 2 - 2 (1 bit)
CCDS : Capture/compare DMA selection
bits : 3 - 3 (1 bit)
MMFC : Master mode selection
bits : 4 - 6 (3 bit)
TI1IS : TI1 selection
bits : 7 - 7 (1 bit)
CH1ISO : Output Idle state 1
bits : 8 - 8 (1 bit)
CH1NISO : Output Idle state 1
bits : 9 - 9 (1 bit)
CH2ISO : Output Idle state 2
bits : 10 - 10 (1 bit)
CH2NISO : Output Idle state 2
bits : 11 - 11 (1 bit)
CH3ISO : Output Idle state 3
bits : 12 - 12 (1 bit)
CH3NISO : Output Idle state 3
bits : 13 - 13 (1 bit)
CH4ISO : Output Idle state 4
bits : 14 - 14 (1 bit)
capture/compare register 4
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH4CC : Capture/Compare 4 value
bits : 0 - 15 (16 bit)
Brake and dead zone registers
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTS : Dead-time generator setup
bits : 0 - 7 (8 bit)
PROTCFG : Lock configuration
bits : 8 - 9 (2 bit)
IMOS : Off-state selection for Idle mode
bits : 10 - 10 (1 bit)
RMOS : Off-state selection for Run mode
bits : 11 - 11 (1 bit)
BRKEN : Break enable
bits : 12 - 12 (1 bit)
BRKPOL : Break polarity
bits : 13 - 13 (1 bit)
AOEN : Automatic output enable
bits : 14 - 14 (1 bit)
WOEN : Main output enable
bits : 15 - 15 (1 bit)
DMA control register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBA : DMA base address
bits : 0 - 4 (5 bit)
DBL : DMA burst length
bits : 8 - 12 (5 bit)
Consecutive DMA addresses
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAB : DMA register for burst accesses
bits : 0 - 15 (16 bit)
slave mode control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMFC : Slave mode selection
bits : 0 - 2 (3 bit)
ITC : Trigger selection
bits : 4 - 6 (3 bit)
MSMEN : Master/Slave mode
bits : 7 - 7 (1 bit)
ETFC : External trigger filter
bits : 8 - 11 (4 bit)
ETDC : External trigger prescaler
bits : 12 - 13 (2 bit)
ECM2EN : External clock enable
bits : 14 - 14 (1 bit)
ETPC : External trigger polarity
bits : 15 - 15 (1 bit)
DMA/Interrupt enable register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UDIEN : Update interrupt enable
bits : 0 - 0 (1 bit)
CH1CCIEN : Capture/Compare 1 interrupt enable
bits : 1 - 1 (1 bit)
CH2CCIEN : Capture/Compare 2 interrupt enable
bits : 2 - 2 (1 bit)
CH3CCIEN : Capture/Compare 3 interrupt enable
bits : 3 - 3 (1 bit)
CH4CCIEN : Capture/Compare 4 interrupt enable
bits : 4 - 4 (1 bit)
CCUIEN : COM interrupt enable
bits : 5 - 5 (1 bit)
TRGIEN : Trigger interrupt enable
bits : 6 - 6 (1 bit)
BRKIEN : Break interrupt enable
bits : 7 - 7 (1 bit)
UDEN : Update DMA request enable
bits : 8 - 8 (1 bit)
CH1CCDEN : Capture/Compare 1 DMA request enable
bits : 9 - 9 (1 bit)
CH2CCDEN : Capture/Compare 2 DMA request enable
bits : 10 - 10 (1 bit)
CH3CCDEN : Capture/Compare 3 DMA request enable
bits : 11 - 11 (1 bit)
CH4CCDEN : Capture/Compare 4 DMA request enable
bits : 12 - 12 (1 bit)
CMDEN : COM DMA request enable
bits : 13 - 13 (1 bit)
TDEN : Trigger DMA request enable
bits : 14 - 14 (1 bit)
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