\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
Interrupt mask register (EXTI_IMR)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IEN0 : Interrupt Mask on line 0
bits : 0 - 0 (1 bit)
IEN1 : Interrupt Mask on line 1
bits : 1 - 1 (1 bit)
IEN2 : Interrupt Mask on line 2
bits : 2 - 2 (1 bit)
IEN3 : Interrupt Mask on line 3
bits : 3 - 3 (1 bit)
IEN4 : Interrupt Mask on line 4
bits : 4 - 4 (1 bit)
IEN5 : Interrupt Mask on line 5
bits : 5 - 5 (1 bit)
IEN6 : Interrupt Mask on line 6
bits : 6 - 6 (1 bit)
IEN7 : Interrupt Mask on line 7
bits : 7 - 7 (1 bit)
IEN8 : Interrupt Mask on line 8
bits : 8 - 8 (1 bit)
IEN9 : Interrupt Mask on line 9
bits : 9 - 9 (1 bit)
IEN10 : Interrupt Mask on line 10
bits : 10 - 10 (1 bit)
IEN11 : Interrupt Mask on line 11
bits : 11 - 11 (1 bit)
IEN12 : Interrupt Mask on line 12
bits : 12 - 12 (1 bit)
IEN13 : Interrupt Mask on line 13
bits : 13 - 13 (1 bit)
IEN14 : Interrupt Mask on line 14
bits : 14 - 14 (1 bit)
IEN15 : Interrupt Mask on line 15
bits : 15 - 15 (1 bit)
IEN16 : Interrupt Mask on line 16
bits : 16 - 16 (1 bit)
IEN17 : Interrupt Mask on line 17
bits : 17 - 17 (1 bit)
IEN18 : Interrupt Mask on line 18
bits : 18 - 18 (1 bit)
IEN19 : Interrupt Mask on line 19
bits : 19 - 19 (1 bit)
Software interrupt event register (EXTI_SWIER)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWIEN0 : Software Interrupt on line 0
bits : 0 - 0 (1 bit)
SWIEN1 : Software Interrupt on line 1
bits : 1 - 1 (1 bit)
SWIEN2 : Software Interrupt on line 2
bits : 2 - 2 (1 bit)
SWIEN3 : Software Interrupt on line 3
bits : 3 - 3 (1 bit)
SWIEN4 : Software Interrupt on line 4
bits : 4 - 4 (1 bit)
SWIEN5 : Software Interrupt on line 5
bits : 5 - 5 (1 bit)
SWIEN6 : Software Interrupt on line 6
bits : 6 - 6 (1 bit)
SWIEN7 : Software Interrupt on line 7
bits : 7 - 7 (1 bit)
SWIEN8 : Software Interrupt on line 8
bits : 8 - 8 (1 bit)
SWIEN9 : Software Interrupt on line 9
bits : 9 - 9 (1 bit)
SWIEN10 : Software Interrupt on line 10
bits : 10 - 10 (1 bit)
SWIEN11 : Software Interrupt on line 11
bits : 11 - 11 (1 bit)
SWIEN12 : Software Interrupt on line 12
bits : 12 - 12 (1 bit)
SWIEN13 : Software Interrupt on line 13
bits : 13 - 13 (1 bit)
SWIEN14 : Software Interrupt on line 14
bits : 14 - 14 (1 bit)
SWIEN15 : Software Interrupt on line 15
bits : 15 - 15 (1 bit)
SWIEN16 : Software Interrupt on line 16
bits : 16 - 16 (1 bit)
SWIEN17 : Software Interrupt on line 17
bits : 17 - 17 (1 bit)
SWIEN18 : Software Interrupt on line 18
bits : 18 - 18 (1 bit)
SWIEN19 : Software Interrupt on line 19
bits : 19 - 19 (1 bit)
Interrupt Flag Enable register (EXTI_IF)
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IF0 : Pending bit 0
bits : 0 - 0 (1 bit)
IF1 : Pending bit 1
bits : 1 - 1 (1 bit)
IF2 : Pending bit 2
bits : 2 - 2 (1 bit)
IF3 : Pending bit 3
bits : 3 - 3 (1 bit)
IF4 : Pending bit 4
bits : 4 - 4 (1 bit)
IF5 : Pending bit 5
bits : 5 - 5 (1 bit)
IF6 : Pending bit 6
bits : 6 - 6 (1 bit)
IF7 : Pending bit 7
bits : 7 - 7 (1 bit)
IF8 : Pending bit 8
bits : 8 - 8 (1 bit)
IF9 : Pending bit 9
bits : 9 - 9 (1 bit)
IF10 : Pending bit 10
bits : 10 - 10 (1 bit)
IF11 : Pending bit 11
bits : 11 - 11 (1 bit)
IF12 : Pending bit 12
bits : 12 - 12 (1 bit)
IF13 : Pending bit 13
bits : 13 - 13 (1 bit)
IF14 : Pending bit 14
bits : 14 - 14 (1 bit)
IF15 : Pending bit 15
bits : 15 - 15 (1 bit)
IF16 : Pending bit 16
bits : 16 - 16 (1 bit)
IF17 : Pending bit 17
bits : 17 - 17 (1 bit)
IF18 : Pending bit 18
bits : 18 - 18 (1 bit)
IF19 : Pending bit 19
bits : 19 - 19 (1 bit)
Event mask register (EXTI_EMR)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EEN0 : Event Mask on line 0
bits : 0 - 0 (1 bit)
EEN1 : Event Mask on line 1
bits : 1 - 1 (1 bit)
EEN2 : Event Mask on line 2
bits : 2 - 2 (1 bit)
EEN3 : Event Mask on line 3
bits : 3 - 3 (1 bit)
EEN4 : Event Mask on line 4
bits : 4 - 4 (1 bit)
EEN5 : Event Mask on line 5
bits : 5 - 5 (1 bit)
EEN6 : Event Mask on line 6
bits : 6 - 6 (1 bit)
EEN7 : Event Mask on line 7
bits : 7 - 7 (1 bit)
EEN8 : Event Mask on line 8
bits : 8 - 8 (1 bit)
EEN9 : Event Mask on line 9
bits : 9 - 9 (1 bit)
EEN10 : Event Mask on line 10
bits : 10 - 10 (1 bit)
EEN11 : Event Mask on line 11
bits : 11 - 11 (1 bit)
EEN12 : Event Mask on line 12
bits : 12 - 12 (1 bit)
EEN13 : Event Mask on line 13
bits : 13 - 13 (1 bit)
EEN14 : Event Mask on line 14
bits : 14 - 14 (1 bit)
EEN15 : Event Mask on line 15
bits : 15 - 15 (1 bit)
EEN16 : Event Mask on line 16
bits : 16 - 16 (1 bit)
EEN17 : Event Mask on line 17
bits : 17 - 17 (1 bit)
EEN18 : Event Mask on line 18
bits : 18 - 18 (1 bit)
EEN19 : Event Mask on line 19
bits : 19 - 19 (1 bit)
Rising Trigger selection register (EXTI_RTSR)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RT0 : Rising trigger event configuration of line 0
bits : 0 - 0 (1 bit)
RT1 : Rising trigger event configuration of line 1
bits : 1 - 1 (1 bit)
RT2 : Rising trigger event configuration of line 2
bits : 2 - 2 (1 bit)
RT3 : Rising trigger event configuration of line 3
bits : 3 - 3 (1 bit)
RT4 : Rising trigger event configuration of line 4
bits : 4 - 4 (1 bit)
RT5 : Rising trigger event configuration of line 5
bits : 5 - 5 (1 bit)
RT6 : Rising trigger event configuration of line 6
bits : 6 - 6 (1 bit)
RT7 : Rising trigger event configuration of line 7
bits : 7 - 7 (1 bit)
RT8 : Rising trigger event configuration of line 8
bits : 8 - 8 (1 bit)
RT9 : Rising trigger event configuration of line 9
bits : 9 - 9 (1 bit)
RT10 : Rising trigger event configuration of line 10
bits : 10 - 10 (1 bit)
RT11 : Rising trigger event configuration of line 11
bits : 11 - 11 (1 bit)
RT12 : Rising trigger event configuration of line 12
bits : 12 - 12 (1 bit)
RT13 : Rising trigger event configuration of line 13
bits : 13 - 13 (1 bit)
RT14 : Rising trigger event configuration of line 14
bits : 14 - 14 (1 bit)
RT15 : Rising trigger event configuration of line 15
bits : 15 - 15 (1 bit)
RT16 : Rising trigger event configuration of line 16
bits : 16 - 16 (1 bit)
RT17 : Rising trigger event configuration of line 17
bits : 17 - 17 (1 bit)
RT18 : Rising trigger event configuration of line 18
bits : 18 - 18 (1 bit)
RT19 : Rising trigger event configuration of line 19
bits : 19 - 19 (1 bit)
Falling Trigger selection register (EXTI_FTSR)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FT0 : Falling trigger event configuration of line 0
bits : 0 - 0 (1 bit)
FT1 : Falling trigger event configuration of line 1
bits : 1 - 1 (1 bit)
FT2 : Falling trigger event configuration of line 2
bits : 2 - 2 (1 bit)
FT3 : Falling trigger event configuration of line 3
bits : 3 - 3 (1 bit)
FT4 : Falling trigger event configuration of line 4
bits : 4 - 4 (1 bit)
FT5 : Falling trigger event configuration of line 5
bits : 5 - 5 (1 bit)
FT6 : Falling trigger event configuration of line 6
bits : 6 - 6 (1 bit)
FT7 : Falling trigger event configuration of line 7
bits : 7 - 7 (1 bit)
FT8 : Falling trigger event configuration of line 8
bits : 8 - 8 (1 bit)
FT9 : Falling trigger event configuration of line 9
bits : 9 - 9 (1 bit)
FT10 : Falling trigger event configuration of line 10
bits : 10 - 10 (1 bit)
FT11 : Falling trigger event configuration of line 11
bits : 11 - 11 (1 bit)
FT12 : Falling trigger event configuration of line 12
bits : 12 - 12 (1 bit)
FT13 : Falling trigger event configuration of line 13
bits : 13 - 13 (1 bit)
FT14 : Falling trigger event configuration of line 14
bits : 14 - 14 (1 bit)
FT15 : Falling trigger event configuration of line 15
bits : 15 - 15 (1 bit)
FT16 : Falling trigger event configuration of line 16
bits : 16 - 16 (1 bit)
FT17 : Falling trigger event configuration of line 17
bits : 17 - 17 (1 bit)
FT18 : Falling trigger event configuration of line 18
bits : 18 - 18 (1 bit)
FT19 : Falling trigger event configuration of line 19
bits : 19 - 19 (1 bit)
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