\n

TMR

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CTRL1

STS

SCEG

CCM1_Output

CCM1_Input

CCM2_Output

CCM2_Input

CHCTRL

CNT

DIV

AOUTORLD

CH1CC

CH2CC

CH3CC

CTRL2

CCR4 (CH4CC)

DCTRL

DMAB

SMCTRL

DIEN


CTRL1

control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL1 CTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTEN NGUE UES SPMEN CNTDIR CNTMODE ARBEN CKDR

CNTEN : Counter enable
bits : 0 - 0 (1 bit)

NGUE : Update disable
bits : 1 - 1 (1 bit)

UES : Update request source
bits : 2 - 2 (1 bit)

SPMEN : One-pulse mode
bits : 3 - 3 (1 bit)

CNTDIR : Direction
bits : 4 - 4 (1 bit)

CNTMODE : Center-aligned mode selection
bits : 5 - 6 (2 bit)

ARBEN : Auto-reload preload enable
bits : 7 - 7 (1 bit)

CKDR : Clock division
bits : 8 - 9 (2 bit)


STS

status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STS STS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDIF CH1CCIF CH2CCIF CH3CCIF CH4CCIF TRGIF CH1RCF CH2RCF CH3RCF CH4RCF

UDIF : Update interrupt flag
bits : 0 - 0 (1 bit)

CH1CCIF : Capture/compare 1 interrupt flag
bits : 1 - 1 (1 bit)

CH2CCIF : Capture/Compare 2 interrupt flag
bits : 2 - 2 (1 bit)

CH3CCIF : Capture/Compare 3 interrupt flag
bits : 3 - 3 (1 bit)

CH4CCIF : Capture/Compare 4 interrupt flag
bits : 4 - 4 (1 bit)

TRGIF : Trigger interrupt flag
bits : 6 - 6 (1 bit)

CH1RCF : Capture/Compare 1 overcapture flag
bits : 9 - 9 (1 bit)

CH2RCF : Capture/compare 2 overcapture flag
bits : 10 - 10 (1 bit)

CH3RCF : Capture/Compare 3 overcapture flag
bits : 11 - 11 (1 bit)

CH4RCF : Capture/Compare 4 overcapture flag
bits : 12 - 12 (1 bit)


SCEG

event generation register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SCEG SCEG write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEG CH1CCG CH2CCG CH3CCG CH4CCG CCUEG TEG

UEG : Update generation
bits : 0 - 0 (1 bit)

CH1CCG : Capture/compare 1 generation
bits : 1 - 1 (1 bit)

CH2CCG : Capture/compare 2 generation
bits : 2 - 2 (1 bit)

CH3CCG : Capture/compare 3 generation
bits : 3 - 3 (1 bit)

CH4CCG : Capture/compare 4 generation
bits : 4 - 4 (1 bit)

CCUEG : Capture/Compare control update generation
bits : 5 - 5 (1 bit)

TEG : Trigger generation
bits : 6 - 6 (1 bit)


CCM1_Output

capture/compare mode register (output mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCM1_Output CCM1_Output read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC1MS OC1FEN OC1BEN OC1MS OC1CEN CC2MS OC2FEN OC2BEN OC2MS OC2CEN

CC1MS : Capture/Compare 1 selection
bits : 0 - 1 (2 bit)

OC1FEN : Output Compare 1 fast enable
bits : 2 - 2 (1 bit)

OC1BEN : Output Compare 1 preload enable
bits : 3 - 3 (1 bit)

OC1MS : Output Compare 1 mode
bits : 4 - 6 (3 bit)

OC1CEN : Output Compare 1 clear enable
bits : 7 - 7 (1 bit)

CC2MS : Capture/Compare 2 selection
bits : 8 - 9 (2 bit)

OC2FEN : Output Compare 2 fast enable
bits : 10 - 10 (1 bit)

OC2BEN : Output Compare 2 preload enable
bits : 11 - 11 (1 bit)

OC2MS : Output Compare 2 mode
bits : 12 - 14 (3 bit)

OC2CEN : Output Compare 2 clear enable
bits : 15 - 15 (1 bit)


CCM1_Input

capture/compare mode register 1 (input mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCM1_Output
reset_Mask : 0x0

CCM1_Input CCM1_Input read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC1MS IC1D IC1FC CC2MS IC2D IC2FC

CC1MS : Capture/Compare 1 selection
bits : 0 - 1 (2 bit)

IC1D : Input capture 1 prescaler
bits : 2 - 3 (2 bit)

IC1FC : Input capture 1 filter
bits : 4 - 7 (4 bit)

CC2MS : Capture/Compare 2 selection
bits : 8 - 9 (2 bit)

IC2D : Input capture 2 prescaler
bits : 10 - 11 (2 bit)

IC2FC : Input capture 2 filter
bits : 12 - 15 (4 bit)


CCM2_Output

capture/compare mode register (output mode)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCM2_Output CCM2_Output read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC3MS OC3FEN OC3BEN OC3MS OC3CEN CC4MS OC4FEN OC4BEN OC4MS OC4CEN

CC3MS : Capture/Compare 3 selection
bits : 0 - 1 (2 bit)

OC3FEN : Output compare 3 fast enable
bits : 2 - 2 (1 bit)

OC3BEN : Output compare 3 preload enable
bits : 3 - 3 (1 bit)

OC3MS : Output compare 3 mode
bits : 4 - 6 (3 bit)

OC3CEN : Output compare 3 clear enable
bits : 7 - 7 (1 bit)

CC4MS : Capture/Compare 4 selection
bits : 8 - 9 (2 bit)

OC4FEN : Output compare 4 fast enable
bits : 10 - 10 (1 bit)

OC4BEN : Output compare 4 preload enable
bits : 11 - 11 (1 bit)

OC4MS : Output compare 4 mode
bits : 12 - 14 (3 bit)

OC4CEN : Output compare 4 clear enable
bits : 15 - 15 (1 bit)


CCM2_Input

capture/compare mode register 2 (input mode)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCM2_Output
reset_Mask : 0x0

CCM2_Input CCM2_Input read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC3MS IC3D IC3FC CC4MS IC4D IC4FC

CC3MS : Capture/compare 3 selection
bits : 0 - 1 (2 bit)

IC3D : Input capture 3 prescaler
bits : 2 - 3 (2 bit)

IC3FC : Input capture 3 filter
bits : 4 - 7 (4 bit)

CC4MS : Capture/Compare 4 selection
bits : 8 - 9 (2 bit)

IC4D : Input capture 4 prescaler
bits : 10 - 11 (2 bit)

IC4FC : Input capture 4 filter
bits : 12 - 15 (4 bit)


CHCTRL

capture/compare enable register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRL CHCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH1CCEN CH1CCP CH1OCNEN CH1OCNP CH2CCEN CH2CCP CH2OCNEN CH2OCNP CH3CCEN CH3CCP CH3OCNEN CH3OCNP CH4CCEN CH4CCP

CH1CCEN : Capture/Compare 1 output enable
bits : 0 - 0 (1 bit)

CH1CCP : Capture/Compare 1 output Polarity
bits : 1 - 1 (1 bit)

CH1OCNEN : Capture/Compare 1 complementary output enable
bits : 2 - 2 (1 bit)

CH1OCNP : Capture/Compare 1 output Polarity
bits : 3 - 3 (1 bit)

CH2CCEN : Capture/Compare 2 output enable
bits : 4 - 4 (1 bit)

CH2CCP : Capture/Compare 2 output Polarity
bits : 5 - 5 (1 bit)

CH2OCNEN : Capture/Compare 2 complementary output enable
bits : 6 - 6 (1 bit)

CH2OCNP : Capture/Compare 2 output Polarity
bits : 7 - 7 (1 bit)

CH3CCEN : Capture/Compare 3 output enable
bits : 8 - 8 (1 bit)

CH3CCP : Capture/Compare 3 output Polarity
bits : 9 - 9 (1 bit)

CH3OCNEN : Capture/Compare 3 complementary output enable
bits : 10 - 10 (1 bit)

CH3OCNP : Capture/Compare 3 output Polarity
bits : 11 - 11 (1 bit)

CH4CCEN : Capture/Compare 4 output enable
bits : 12 - 12 (1 bit)

CH4CCP : Capture/Compare 3 output Polarity
bits : 13 - 13 (1 bit)


CNT

counter
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNT CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : counter value
bits : 0 - 15 (16 bit)


DIV

prescaler
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIV DIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV

DIV : Prescaler value
bits : 0 - 15 (16 bit)


AOUTORLD

auto-reload register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AOUTORLD AOUTORLD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AOUTORLD

AOUTORLD : Auto-reload value
bits : 0 - 15 (16 bit)


CH1CC

capture/compare register 1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1CC CH1CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH1CC

CH1CC : Capture/Compare 1 value
bits : 0 - 15 (16 bit)


CH2CC

capture/compare register 2
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2CC CH2CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH2CC

CH2CC : Capture/Compare 2 value
bits : 0 - 15 (16 bit)


CH3CC

capture/compare register 3
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3CC CH3CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH3CC

CH3CC : Capture/Compare 3 value
bits : 0 - 15 (16 bit)


CTRL2

control register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL2 CTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MMFC TI1IS

MMFC : Master mode selection
bits : 4 - 6 (3 bit)

TI1IS : TI1 selection
bits : 7 - 7 (1 bit)


CCR4 (CH4CC)

capture/compare register 4
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR4 CCR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH4CC

CH4CC : Capture/Compare 4 value
bits : 0 - 15 (16 bit)


DCTRL

DMA control register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCTRL DCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBA DBL

DBA : DMA base address
bits : 0 - 4 (5 bit)

DBL : DMA burst length
bits : 8 - 12 (5 bit)


DMAB

Consecutive DMA addresses
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAB DMAB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAB

DMAB : DMA register for burst accesses
bits : 0 - 15 (16 bit)


SMCTRL

slave mode control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMCTRL SMCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMFC ITC MSMEN ETFC ETDC ECM2EN ETPC

SMFC : Slave mode selection
bits : 0 - 2 (3 bit)

ITC : Trigger selection
bits : 4 - 6 (3 bit)

MSMEN : Master/Slave mode
bits : 7 - 7 (1 bit)

ETFC : External trigger filter
bits : 8 - 11 (4 bit)

ETDC : External trigger prescaler
bits : 12 - 13 (2 bit)

ECM2EN : External clock enable
bits : 14 - 14 (1 bit)

ETPC : External trigger polarity
bits : 15 - 15 (1 bit)


DIEN

DMA/Interrupt enable register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEN DIEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDIEN CH1CCIEN CH2CCIEN CH3CCIEN CH4CCIEN TRGIEN UDEN CH1CCDEN CH2CCDEN CH3CCDEN CH4CCDEN TDEN

UDIEN : Update interrupt enable
bits : 0 - 0 (1 bit)

CH1CCIEN : Capture/Compare 1 interrupt enable
bits : 1 - 1 (1 bit)

CH2CCIEN : Capture/Compare 2 interrupt enable
bits : 2 - 2 (1 bit)

CH3CCIEN : Capture/Compare 3 interrupt enable
bits : 3 - 3 (1 bit)

CH4CCIEN : Capture/Compare 4 interrupt enable
bits : 4 - 4 (1 bit)

TRGIEN : Trigger interrupt enable
bits : 6 - 6 (1 bit)

UDEN : Update DMA request enable
bits : 8 - 8 (1 bit)

CH1CCDEN : Capture/Compare 1 DMA request enable
bits : 9 - 9 (1 bit)

CH2CCDEN : Capture/Compare 2 DMA request enable
bits : 10 - 10 (1 bit)

CH3CCDEN : Capture/Compare 3 DMA request enable
bits : 11 - 11 (1 bit)

CH4CCDEN : Capture/Compare 4 DMA request enable
bits : 12 - 12 (1 bit)

TDEN : Trigger DMA request enable
bits : 14 - 14 (1 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.