\n
address_offset : 0x0 Bytes (0x0)
size : 0x1001 byte (0x0)
mem_usage : registers
protection :
Interrupt Set-Enable Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA : SETENA
bits : 0 - 31 (32 bit)
Interrupt Set-Enable Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA : SETENA
bits : 0 - 31 (32 bit)
Interrupt Clear-Enable Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRENA : CLRENA
bits : 0 - 31 (32 bit)
Interrupt Clear-Enable Register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRENA : CLRENA
bits : 0 - 31 (32 bit)
Interrupt Set-Pending Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND : SETPEND
bits : 0 - 31 (32 bit)
Interrupt Set-Pending Register
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND : SETPEND
bits : 0 - 31 (32 bit)
Interrupt Clear-Pending Register
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRPEND : CLRPEND
bits : 0 - 31 (32 bit)
Interrupt Clear-Pending Register
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRPEND : CLRPEND
bits : 0 - 31 (32 bit)
Interrupt Active Bit Register
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ACTIVE : ACTIVE
bits : 0 - 31 (32 bit)
Interrupt Active Bit Register
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ACTIVE : ACTIVE
bits : 0 - 31 (32 bit)
Interrupt Controller Type Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTLINESNUM : Total number of interrupt lines in groups
bits : 0 - 3 (4 bit)
Interrupt Priority Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)
IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)
IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)
IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)
Interrupt Priority Register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)
IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)
IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)
IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)
Interrupt Priority Register
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)
IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)
IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)
IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)
Interrupt Priority Register
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)
IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)
IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)
IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)
Interrupt Priority Register
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)
IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)
IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)
IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)
Interrupt Priority Register
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)
IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)
IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)
IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)
Interrupt Priority Register
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)
IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)
IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)
IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)
Interrupt Priority Register
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)
IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)
IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)
IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)
Interrupt Priority Register
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)
IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)
IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)
IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)
Interrupt Priority Register
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)
IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)
IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)
IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)
Interrupt Priority Register
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)
IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)
IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)
IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)
Interrupt Priority Register
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)
IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)
IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)
IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)
Interrupt Priority Register
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)
IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)
IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)
IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)
Interrupt Priority Register
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)
IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)
IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)
IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)
Interrupt Priority Register
address_offset : 0x438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)
IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)
IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)
IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)
Software Triggered Interrupt Register
address_offset : 0xF00 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTID : interrupt to be triggered
bits : 0 - 8 (9 bit)
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