SYS_PDID (PDID)

SYS_IPRST2 (IPRST2)

SYS_REGLCTL (REGLCTL)

SYS_TSCTL (TSCTL)

SYS_TSDATA (TSDATA)

SYS_BODCTL (BODCTL)

SYS_POR18DISAN (POR18DISAN)

SYS_PORCTL (PORCTL)

SYS_VREFCTL (VREFCTL)

SYS_GPA_MFPL (GPA_MFPL)

SYS_GPA_MFPH (GPA_MFPH)

SYS_GPB_MFPL (GPB_MFPL)

SYS_GPB_MFPH (GPB_MFPH)

SYS_RSTSTS (RSTSTS)

SYS_GPC_MFPL (GPC_MFPL)

SYS_GPF_MFPL (GPF_MFPL)

SYS_IPRST0 (IPRST0)

SYS_IPRST1 (IPRST1)

SYS_MODCTL (MODCTL)

SYS_SRAM_BISTCTL (SRAM_BISTCTL)

SYS_SRAM_BISTSTS (SRAM_BISTSTS)

PDID : Part Device Identification Number (Read Only) This register reflects device part number code. Software can read this register to identify which device is used.
bits : 0 - 31 (32 bit)
access : read-only

DAC01RST : DAC01 Controller Reset
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DAC23RST : DAC23 Controller Reset
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BPWMRST : BPWM Controller Reset
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MANCHRST : Manchester Codec Reset
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR4RST : Timer4 Controller Reset
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR5RST : Timer5 Controller Reset
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TSRST : Temperature Sensor Reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REGLCTL : Register Lock Control Code Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value '59h', '16h', '88h' to this field. After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write. REGLCTL[0] Register Lock Control Disable Index
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TSEOC : Temperature Sensor Conversion Finish Flag This bit indicates the end of temperature sensor conversion. Note: Write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write

TSDATA : Temperature Sensor Conversion Data Bits (Read Only) This field present the conversion result of Temperature Sensor, ranges from -40C to 105C. Note: Negative temperature is represented by 2's complement format, and per LSB difference is equivalent to 0.0625C
bits : 16 - 27 (12 bit)
access : read-only

BODEN : Brown-out Detector Enable Bit (Write Protect) Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: Reset by power on reset
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODRSTEN : Brown-out Reset Enable Bit (Write Protect) Note 1: While the Brown-out Detector function is enabled (BODEN is 1) and BOD reset function is enabled (BODRSTEN is 1), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT is 1). While the BOD function is enabled (BODEN is 1) and BOD interrupt function is enabled (BODRSTEN is 0), BOD will assert an interrupt if BODOUT is 1. BOD interrupt will keep untill the BODEN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN to 0). Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. Note 3: Reset by power on reset
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODIF : Brown-out Detector Interrupt Flag Note: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODLPM : Brown-out Detector Low Power Mode (Write Protect) Note 1: The BOD consumes about 2uA in normal mode, the BOD low power mode can reduce the current to about 1/30 but slow the BOD response. Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODOUT : Brown-out Detector Output Status It means the detected voltage is lower than BODVL setting. If the BODEN is 0, BOD function disabled , this bit always responds 0000.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVREN : Low Voltage Reset Enable Bit (Write Protect) The LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default. Note 1: After enabling the bit, the LVR function will be active with 200us delay for LVR output stable (Default). Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODDGSEL : Brown-out Detector Output De-glitch Time Select (Write Protect) Note: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVRDGSEL : LVR Output De-glitch Time Select (Write Protect) Note: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODVL : Brown-out Detector Threshold Voltage Select (Write Protect) Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: Reset by power on reset.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POR18OFFAN : LDO Power-on Reset Enable Bit (Write Protect) After powered on, user can turn off internal analog POR18 circuit to save power by writing 0x5AA5 to this field. The analog POR18 circuit will be active again when this field is set to another value or chip is reset by other reset source, including: nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 15 (16 bit)
access : read-write

POROFF : Power-on Reset Enable Bit (Write Protect) When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 15 (16 bit)
access : read-write

VREFEN : VREF Enable Bit (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VREFSEL : VREF Output Voltage Select (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRELOADEN : VREF Pre-load Enable Bit (Write Protect) This bit is set automatically if software set VREFEN (SYS_VREFCTL[0]) to 1. Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: PRELOADEN should be cleared after 2ms of VREFEN enabled, if VREF capacitor is 4.7uF and VREF initial is 0V. Note 3: PRELOADEN should be cleared after 480us of VREFEN enabled, if VREF capacitor is 1uF and VREF initial is 0V.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCPDIS : VREF Short Circuit Protection Disable Control (Write Protect)
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA0MFP : PA.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PA1MFP : PA.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PA2MFP : PA.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PA3MFP : PA.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PA12MFP : PA.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PA13MFP : PA.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PA14MFP : PA.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PA15MFP : PA.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

PB0MFP : PB.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PB1MFP : PB.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PB2MFP : PB.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PB3MFP : PB.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PB4MFP : PB.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PB5MFP : PB.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PB6MFP : PB.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PB7MFP : PB.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

PB8MFP : PB.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PB9MFP : PB.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PB10MFP : PB.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PB11MFP : PB.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PB12MFP : PB.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PB13MFP : PB.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PB14MFP : PB.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PB15MFP : PB.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

PORF : POR Reset Flag The POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PINRF : NRESET Pin Reset Flag The nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDTRF : WDT Reset Flag The WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source. Note 1: Write 1 to clear this bit to 0. Note 2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset. Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVRF : LVR Reset Flag The LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODRF : BOD Reset Flag The BOD reset flag is set by the 'Reset Signal' from the Brown-Out Detector to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYSRF : System Reset Flag The system reset flag is set by the 'Reset Signal' from the Cortex-M0 Core to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPURF : CPU Reset Flag The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex- M0 Core and Flash Memory Controller (FMC). Note: Write to clear this bit to 0.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPULKRF : CPU Lockup Reset Flag Note 1: Write 1 to clear this bit to 0. Note 2: When CPU lockup happened under ICE is connected, this flag will set to 1 but chip will not reset.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PC1MFP : PC.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PF0MFP : PF.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PF2MFP : PF.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PF3MFP : PF.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

CHIPRST : Chip One-shot Reset (Write Protect) Setting this bit will reset the whole chip, including processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from Flash are also reload. About the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to System Reset section. Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: Reset by power on reset.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPURST : Processor Core One-shot Reset (Write Protect) Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after 2 clock cycles. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDMARST : PDMA Controller Reset (Write Protect) Setting this bit to 1 will generate a reset signal to the PDMA. User needs to set this bit to 0 to release from reset state. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRCRST : CRC Calculation Controller Reset (Write Protect) Set this bit to 1 will generate a reset signal to the CRC calculation controller. User needs to set this bit to 0 to release from the reset state. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIORST : GPIO Controller Reset
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0RST : Timer0 Controller Reset
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1RST : Timer1 Controller Reset
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR2RST : Timer2 Controller Reset
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR3RST : Timer3 Controller Reset
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C0RST : I2C0 Controller Reset
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C1RST : I2C1 Controller Reset
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI0RST : SPI0 Controller Reset
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART0RST : UART0 Controller Reset
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCRST : ADC Controller Reset
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MANCHMODEN0 : Manchester Modulation Function Enable Each of these bits is used to enable Manchester modulation function with BPWM1_CHn output.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MANCHMODEN1 : Manchester Modulation Function Enable Each of these bits is used to enable Manchester modulation function with BPWM1_CHn output.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MANCHMODEN2 : Manchester Modulation Function Enable Each of these bits is used to enable Manchester modulation function with BPWM1_CHn output.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MANCHMODEN3 : Manchester Modulation Function Enable Each of these bits is used to enable Manchester modulation function with BPWM1_CHn output.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MANCHMODEN4 : Manchester Modulation Function Enable Each of these bits is used to enable Manchester modulation function with BPWM1_CHn output.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MANCHMODEN5 : Manchester Modulation Function Enable Each of these bits is used to enable Manchester modulation function with BPWM1_CHn output.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MANCHMODL0 : Manchester Modulation at Data Low Each of these bits is used to select Manchester modulation with BPWM1_CHn at MANCH_TXD data high or low.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MANCHMODL1 : Manchester Modulation at Data Low Each of these bits is used to select Manchester modulation with BPWM1_CHn at MANCH_TXD data high or low.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MANCHMODL2 : Manchester Modulation at Data Low Each of these bits is used to select Manchester modulation with BPWM1_CHn at MANCH_TXD data high or low.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MANCHMODL3 : Manchester Modulation at Data Low Each of these bits is used to select Manchester modulation with BPWM1_CHn at MANCH_TXD data high or low.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MANCHMODL4 : Manchester Modulation at Data Low Each of these bits is used to select Manchester modulation with BPWM1_CHn at MANCH_TXD data high or low.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MANCHMODL5 : Manchester Modulation at Data Low Each of these bits is used to select Manchester modulation with BPWM1_CHn at MANCH_TXD data high or low.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SRBIST : System SRAM BIST Enable Bit (Write Protect) This bit enables BIST test for System SRAM Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDMABIST : PDMA SRAM BIST Enable Bit (Write Protect) This bit enables BIST test for PDMA SRAM Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SRBISTFF : System SRAM BIST Fail Flag
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PDMABISTF : PDMA SRAM BIST Failed Flag
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SRBEND : System SRAM BIST Test Finish
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PDMAEND : PDMA SRAM BIST Test Finish
bits : 23 - 23 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.