\n

CLK

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection :

address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x34 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x40 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x50 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x60 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

Registers

CLK_PWRCTL (PWRCTL)

CLK_CLKSEL0 (CLKSEL0)

CLK_CLKSEL1 (CLKSEL1)

CLK_CLKSEL2 (CLKSEL2)

CLK_CLKDIV0 (CLKDIV0)

CLK_PCLKDIV (PCLKDIV)

CLK_AHBCLK (AHBCLK)

CLK_PLLCTL (PLLCTL)

CLK_STATUS (STATUS)

CLK_CLKOCTL (CLKOCTL)

CLK_APBCLK0 (APBCLK0)

CLK_APBCLK1 (APBCLK1)


CLK_PWRCTL (PWRCTL)

System Power-down Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_PWRCTL CLK_PWRCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIRCEN PDWKDLY PDWKIEN PDWKIF PDEN

HIRCEN : HIRC Enable Bit (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal high speed RC oscillator (HIRC) Disabled

#1 : 1

Internal high speed RC oscillator (HIRC) Enabled

End of enumeration elements list.

PDWKDLY : Enable the Wake-up Delay Counter (Write Protect) When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable. The delayed clock cycle is 512 clock cycles when chip works at internal high speed RC oscillator (HIRC). Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock cycles delay Disabled

#1 : 1

Clock cycles delay Enabled

End of enumeration elements list.

PDWKIEN : Power-down Mode Wake-up Interrupt Enable Bit (Write Protect) Note 1: The interrupt will occur when both PDWKIF and PDWKIEN are high. Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Power-down mode wake-up interrupt Disabled

#1 : 1

Power-down mode wake-up interrupt Enabled

End of enumeration elements list.

PDWKIF : Power-down Mode Wake-up Interrupt Status When set by 'Power-down wake-up event', it indicates that resume from Power-down mode. The flag is set if any wake-up source occurred. Refer to Power Modes and Wake-up Sources section. Note 1: Write 1 to clear the bit to 0. Note 2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.
bits : 6 - 6 (1 bit)
access : read-write

PDEN : System Power-down Enable (Write Protect) When this bit is set to 1, Power-down mode is enabled and chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode. When chip wakes up from Power-down mode, this bit is auto cleared. Users need to set this bit again for next Power-down. In Power-down mode, the HIRC will be disabled, but LIRC are not controlled by Power-down mode. If user disables LIRC before entering Power-down mode, this bit should be set after LIRC is disabled at least 50us. The clocks of peripheral are not controlled by Power-down mode if the peripheral clock source is from LIRC. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Chip operating normally or chip in idle mode because of WFI command

#1 : 1

Chip enters Power-down mode instantly or waits CPU sleep command WFI

End of enumeration elements list.


CLK_CLKSEL0 (CLKSEL0)

Clock Source Select Control Register 0
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKSEL0 CLK_CLKSEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HCLKSEL STCLKSEL

HCLKSEL : HCLK Clock Source Selection (Write Protect) Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: Reset by power on reset.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#010 : 2

Clock source from PLL

#111 : 7

Clock source from HIRC

End of enumeration elements list.

STCLKSEL : Cortex-M0 SysTick Clock Source Selection (Write Protect) Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 5 (3 bit)
access : read-write

Enumeration:

#011 : 3

Clock source from HCLK/2

#111 : 7

Clock source from HIRC/2

End of enumeration elements list.


CLK_CLKSEL1 (CLKSEL1)

Clock Source Select Control Register 1
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKSEL1 CLK_CLKSEL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTSEL WWDTSEL CLKOSEL TMR0SEL TMR1SEL TMR2SEL TMR3SEL UART0SEL

WDTSEL : Watchdog Timer Clock Source Selection (Write Protect) Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: This bit is force to 11 when CONFIG0[31], CONFIG0[4], CONFIG0[3] are all ones.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#10 : 2

Clock source from HCLK/2048

#11 : 3

Clock source from internal low speed RC oscillator (LIRC)

End of enumeration elements list.

WWDTSEL : Window Watchdog Timer Clock Source Selection (Write Protect)
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#10 : 2

Clock source from HCLK/2048

#11 : 3

Clock source from internal low speed RC oscillator (LIRC)

End of enumeration elements list.

CLKOSEL : Clock Divider Clock Source Selection
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

#010 : 2

Clock source from HCLK

#011 : 3

Clock source from internal high speed RC oscillator (HIRC)

#100 : 4

Clock source from internal low speed RC oscillator (LIRC)

#101 : 5

Clock source from internal high speed RC oscillator (HIRC)

#110 : 6

Clock source from PLL

End of enumeration elements list.

TMR0SEL : TIMER0 Clock Source Selection
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#010 : 2

Clock source from PCLK0

#011 : 3

Clock source from external clock T0 pin

#101 : 5

Clock source from internal low speed RC oscillator (LIRC)

#111 : 7

Clock source from internal high speed RC oscillator (HIRC)

End of enumeration elements list.

TMR1SEL : TIMER1 Clock Source Selection
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

#010 : 2

Clock source from PCLK0

#011 : 3

Clock source from external clock T1 pin

#101 : 5

Clock source from internal low speed RC oscillator (LIRC)

#111 : 7

Clock source from internal high speed RC oscillator (HIRC)

End of enumeration elements list.

TMR2SEL : TIMER2 Clock Source Selection
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#010 : 2

Clock source from PCLK1

#011 : 3

Clock source from external clock TM2 pin

#101 : 5

Clock source from internal low speed RC oscillator (LIRC)

#111 : 7

Clock source from internal high speed RC oscillator (HIRC)

End of enumeration elements list.

TMR3SEL : TIMER3 Clock Source Selection
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

#010 : 2

Clock source from PCLK1

#011 : 3

Clock source from external clock TM3 pin

#101 : 5

Clock source from internal low speed RC oscillator (LIRC)

#111 : 7

Clock source from internal high speed RC oscillator (HIRC)

End of enumeration elements list.

UART0SEL : UART0 Clock Source Selection
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

#001 : 1

Clock source from PLL

#011 : 3

Clock source from internal high speed RC oscillator (HIRC)

#100 : 4

Clock source from PCLK0

#101 : 5

Clock source from internal low speed RC oscillator (LIRC)

End of enumeration elements list.


CLK_CLKSEL2 (CLKSEL2)

Clock Source Select Control Register 2
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKSEL2 CLK_CLKSEL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI0SEL BPWM1SEL TMR4SEL TMR5SEL ADCSEL

SPI0SEL : SPI0 Clock Source Selection
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#01 : 1

Clock source from PLL

#10 : 2

Clock source from PCLK1

#11 : 3

Clock source from internal high speed RC oscillator (HIRC)

End of enumeration elements list.

BPWM1SEL : BPWM1 Clock Source Selection The peripheral clock source of BPWM1 is defined by BPWM1SEL.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock source from PLL

#1 : 1

Clock source from PCLK1

End of enumeration elements list.

TMR4SEL : TIMER4 Clock Source Selection
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

#010 : 2

Clock source from PCLK0

#011 : 3

Clock source from external clock TM4 pin

#101 : 5

Clock source from internal low speed RC oscillator (LIRC)

#111 : 7

Clock source from internal high speed RC oscillator (HIRC)

End of enumeration elements list.

TMR5SEL : TIMER5 Clock Source Selection
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#010 : 2

Clock source from PCLK0

#011 : 3

Clock source from external clock TM5 pin

#101 : 5

Clock source from internal low speed RC oscillator (LIRC)

#111 : 7

Clock source from internal high speed RC oscillator (HIRC)

End of enumeration elements list.

ADCSEL : ADC Clock Source Selection
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

#01 : 1

Clock source from PLL

#10 : 2

Clock source from PCLK1

#11 : 3

Clock source from internal high speed RC oscillator (HIRC) clock

End of enumeration elements list.


CLK_CLKDIV0 (CLKDIV0)

Clock Divider Number Register 0
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKDIV0 CLK_CLKDIV0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HCLKDIV UART0DIV ADCDIV

HCLKDIV : HCLK Clock Divide Number From HCLK Clock Source
bits : 0 - 3 (4 bit)
access : read-write

UART0DIV : UART0 Clock Divide Number From UART0 Clock Source
bits : 8 - 11 (4 bit)
access : read-write

ADCDIV : ADC Clock Divide Number From ADC Clock Source
bits : 16 - 23 (8 bit)
access : read-write


CLK_PCLKDIV (PCLKDIV)

APB Clock Divider Register
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_PCLKDIV CLK_PCLKDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APB0DIV APB1DIV

APB0DIV : APB0 Clock Divider APB0 clock can be divided from HCLK Others: Reserved.
bits : 0 - 2 (3 bit)
access : read-write

APB1DIV : APB1 Clock Divider APB1 clock can be divided from HCLK Others: Reserved.
bits : 4 - 6 (3 bit)
access : read-write


CLK_AHBCLK (AHBCLK)

AHB Devices Clock Enable Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_AHBCLK CLK_AHBCLK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDMACKEN ISPCKEN CRCCKEN

PDMACKEN : PDMA Controller Clock Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

PDMA peripheral clock Disabled

#1 : 1

PDMA peripheral clock Enabled

End of enumeration elements list.

ISPCKEN : Flash ISP Controller Clock Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Flash ISP peripheral clock Disabled

#1 : 1

Flash ISP peripheral clock Enabled

End of enumeration elements list.

CRCCKEN : CRC Generator Controller Clock Enable Bit
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

CRC peripheral clock Disabled

#1 : 1

CRC peripheral clock Enabled

End of enumeration elements list.


CLK_PLLCTL (PLLCTL)

PLL Control Register
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_PLLCTL CLK_PLLCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FBDIV INDIV OUTDIV PD BP OE STBSEL

FBDIV : PLL Feedback Divider Control (Write Protect) Refer to the formulas below the table. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 8 (9 bit)
access : read-write

INDIV : PLL Input Divider Control (Write Protect) Refer to the formulas below the table. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 9 - 13 (5 bit)
access : read-write

OUTDIV : PLL Output Divider Control (Write Protect) Refer to the formulas below the table. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 14 - 15 (2 bit)
access : read-write

PD : Power-down Mode (Write Protect) If setting the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

PLL is in normal mode

#1 : 1

PLL is in Power-down mode (default)

End of enumeration elements list.

BP : PLL Bypass Control (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

PLL is in normal mode (default)

#1 : 1

PLL clock output is same as PLL input clock FIN

End of enumeration elements list.

OE : PLL OE Pin Control (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

PLL FOUT Enabled

#1 : 1

PLL FOUT is fixed low

End of enumeration elements list.

STBSEL : PLL Stable Counter Selection (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

PLL stable time is 6144 PLL source clock (suitable for source clock equal to or less than 12 MHz )

#1 : 1

PLL stable time is 16128 PLL source clock (suitable for source clock greater than 12 MHz)

End of enumeration elements list.


CLK_STATUS (STATUS)

Clock Status Monitor Register
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CLK_STATUS CLK_STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLLSTB LIRCSTB HIRCSTB CLKSFAIL

PLLSTB : Internal PLL Clock Source Stable Flag (Read Only)
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal PLL clock is not stable or disabled

#1 : 1

Internal PLL clock is stable and enabled

End of enumeration elements list.

LIRCSTB : LIRC Clock Source Stable Flag (Read Only)
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal low speed RC oscillator (LIRC) clock is not stable or disabled

#1 : 1

Internal low speed RC oscillator (LIRC) clock is stable and enabled

End of enumeration elements list.

HIRCSTB : HIRC Clock Source Stable Flag (Read Only)
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal high speed RC oscillator (HIRC) clock is not stable or disabled

#1 : 1

Internal high speed RC oscillator (HIRC) clock is stable and enabled

End of enumeration elements list.

CLKSFAIL : Clock Switching Fail Flag (Read Only) This bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1. Note: Write 1 to clear the bit to 0.
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

#0 : 0

Clock switching success

#1 : 1

Clock switching failure

End of enumeration elements list.


CLK_CLKOCTL (CLKOCTL)

Clock Output Control Register
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKOCTL CLK_CLKOCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FREQSEL CLKOEN DIV1EN

FREQSEL : Clock Output Frequency Selection The formula of output frequency is Fin is the input clock frequency. Fout is the frequency of divider output clock. N is the 4-bit value of FREQSEL[3:0].
bits : 0 - 3 (4 bit)
access : read-write

CLKOEN : Clock Output Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock Output function Disabled

#1 : 1

Clock Output function Enabled

End of enumeration elements list.

DIV1EN : Clock Output Divide One Enable Bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock Output will output clock with source frequency divided by FREQSEL

#1 : 1

Clock Output will output clock with source frequency

End of enumeration elements list.


CLK_APBCLK0 (APBCLK0)

APB Devices Clock Enable Control Register 0
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_APBCLK0 CLK_APBCLK0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTCKEN TMR0CKEN TMR1CKEN TMR2CKEN TMR3CKEN CLKOCKEN I2C0CKEN I2C1CKEN SPI0CKEN UART0CKEN ADCCKEN

WDTCKEN : Watchdog Timer Clock Enable Bit (Write Protect) Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: This bit is reset by power on reset, Watchdog reset or software chip reset.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Watchdog timer clock Disabled

#1 : 1

Watchdog timer clock Enabled

End of enumeration elements list.

TMR0CKEN : Timer0 Clock Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer0 clock Disabled

#1 : 1

Timer0 clock Enabled

End of enumeration elements list.

TMR1CKEN : Timer1 Clock Enable Bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer1 clock Disabled

#1 : 1

Timer1 clock Enabled

End of enumeration elements list.

TMR2CKEN : Timer2 Clock Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer2 clock Disabled

#1 : 1

Timer2 clock Enabled

End of enumeration elements list.

TMR3CKEN : Timer3 Clock Enable Bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer3 clock Disabled

#1 : 1

Timer3 clock Enabled

End of enumeration elements list.

CLKOCKEN : CLKO Clock Enable Bit
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

CLKO clock Disabled

#1 : 1

CLKO clock Enabled

End of enumeration elements list.

I2C0CKEN : I2C0 Clock Enable Bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C0 clock Disabled

#1 : 1

I2C0 clock Enabled

End of enumeration elements list.

I2C1CKEN : I2C1 Clock Enable Bit
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C1 clock Disabled

#1 : 1

I2C1 clock Enabled

End of enumeration elements list.

SPI0CKEN : SPI0 Clock Enable Bit
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI0 clock Disabled

#1 : 1

SPI0 clock Enabled

End of enumeration elements list.

UART0CKEN : UART0 Clock Enable Bit
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART0 clock Disabled

#1 : 1

UART0 clock Enabled

End of enumeration elements list.

ADCCKEN : ADC Clock Enable Bit
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

ADC clock Disabled

#1 : 1

ADC clock Enabled

End of enumeration elements list.


CLK_APBCLK1 (APBCLK1)

APB Devices Clock Enable Control Register 1
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_APBCLK1 CLK_APBCLK1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAC01CKEN DAC23CKEN BPWM1CKEN MANCHCKEN TMR4CKEN TMR5CKEN

DAC01CKEN : DAC01 Clock Enable Bit
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

DAC01 clock Disabled

#1 : 1

DAC01 clock Enabled

End of enumeration elements list.

DAC23CKEN : DAC23 Clock Enable Bit
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

DAC23 clock Disabled

#1 : 1

DAC23 clock Enabled

End of enumeration elements list.

BPWM1CKEN : BPWM1 Clock Enable Bit
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

BPWM1 clock Disabled

#1 : 1

BPWM1 clock Enabled

End of enumeration elements list.

MANCHCKEN : Manchester Codec Clock Enable Bit
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Manchester Codec clock Disabled

#1 : 1

Manchester Codec clock Enabled

End of enumeration elements list.

TMR4CKEN : Timer4 Clock Enable Bit
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer4 clock Disabled

#1 : 1

Timer4 clock Enabled

End of enumeration elements list.

TMR5CKEN : Timer5 Clock Enable Bit
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer5 clock Disabled

#1 : 1

Timer5 clock Enabled

End of enumeration elements list.



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