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Manchester

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :

address_offset : 0xC Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection :

Registers

MANCH_CTL (CTL)

MANCH_DMAC (DMAC)

MANCH_INTEN (INTEN)

MANCH_STS (STS)

MANCH_BITCNT (BITCNT)

MANCH_TXDAT (TXDAT)

MANCH_RXDAT (RXDAT)

MANCH_MTXDAT (MTXDAT)

MANCH_PREAM (PREAM)

MANCH_FIFOCTL (FIFOCTL)


MANCH_CTL (CTL)

Manchester Function Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MANCH_CTL MANCH_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODESEL DEGSEL MECT LSB TXINV RXINV RBNULEN CRBNULEN DEGDIV MTXE2TEN MANCHTEN BITREFDIV

MODESEL : Manchester Mode Selection Note: All the change of function setting shall be during Manchester Controller disabled.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

Manchester function is disabled

#01 : 1

Mode 1 modulation signal format is selected

#10 : 2

Mode 2 modulation signal format is selected

#11 : 3

The other modulation signal format is selected. (The register of MANCH_PREAM shall be set according to its frame information.)

End of enumeration elements list.

DEGSEL : Received Deglitch Selection The bits field is used to define how much width of glitch would be filtered.
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

#000 : 0

disable to the Manchester deglitch selection

#001 : 1

Filter the glitches that the width is 0.25us or less

#010 : 2

Filter the glitches that the width is 0.50us or less

#011 : 3

Filter the glitches that the width is 0.75us or less

#100 : 4

Filter the glitches that the width is 1.00us or less

#101 : 5

Filter the glitches that the width is 1.25us or less

End of enumeration elements list.

MECT : Manchester Encoding Type Level 0: the signal is half cycle high and transfer to half cycle low Level 1: the signal is half cycle low and transfer to half cycle high. Note: Please refer to Figure 6.165.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

G.E Thomas format

#1 : 1

IEEE 802.3 format

End of enumeration elements list.

LSB : Manchester Code LSB First Note: This bit should be configured before MODSEL
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Manchester code is MSB first

#1 : 1

Manchester code is LSB first

End of enumeration elements list.

TXINV : Transmit Signal Invert
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

The transmitting data is not inverted

#1 : 1

The transmitting data is inverted

End of enumeration elements list.

RXINV : Receive Signal Invert
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

The received data is not inverted

#1 : 1

The received data is inverted

End of enumeration elements list.

RBNULEN : Received Bit Clock Number Auto Upload Enable Bit
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

RBITNUM is not updated by CRBITNUM at each data frame beginning

#1 : 1

RBITNUM is updated by CRBITNUM at each data frame beginning

End of enumeration elements list.

CRBNULEN : Current Received Bit Clock Number Auto Upload Enable Bit
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

CRBITNUM is not updated in each received byte during message receiving period

#1 : 1

CRBITNUM is updated in each received byte during message receiving period

End of enumeration elements list.

DEGDIV : Manchester Deglitch Clock Divider The bits field indicates the deglitched clock frequency. The detail is described in Deglitch Selection section.
bits : 12 - 14 (3 bit)
access : read-write

MTXE2TEN : Manchester Coded Edge Output Enable Bit
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

Manchester coded edge signal outputs to Timer Controller Disabled

#1 : 1

Manchester coded edge signal outputs to Timer Controller Enabled

End of enumeration elements list.

MANCHTEN : Manchester Transmit Enable
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

Manchester Transmit Disabled

#1 : 1

Manchester Transmit Enabled. It will be cleared to 0 after the data frame transmission done

End of enumeration elements list.

BITREFDIV : Manchester Bit Reference Clock Divider The bits field indicates the reference clock frequency for Manchester bit sample. For example, if the PCLK0 is 72 MHz, the BITREFDIV can be set as 0x23 (BITREFDIV+1). It will generate 2 MHz reference clock frequency and the Manchester transmitting or receiving data is sampled with the reference divided clock. Note 1: The BITREFDIV minimum value is 0x03. Note 2: It is suggested that minimize the BITREFDIV value to make the TBITNUM or RTIBNUM value be greater than 0x64.
bits : 20 - 31 (12 bit)
access : read-write


MANCH_DMAC (DMAC)

Manchester DMA Control Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MANCH_DMAC MANCH_DMAC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTXDMAEN TXDMAEN RXDMAEN

MTXDMAEN : Manchester Code Transmit DMA Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Manchester Code Transmit DMA Disabled

#1 : 1

Manchester Code Transmit DMA Enabled

End of enumeration elements list.

TXDMAEN : Transmit DMA Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Transmit DMA Disabled

#1 : 1

Transmit DMA Enabled

End of enumeration elements list.

RXDMAEN : Received DMA Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Received DMA Disabled

#1 : 1

Received DMA Enabled

End of enumeration elements list.


MANCH_INTEN (INTEN)

Manchester Interrupt Enable Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MANCH_INTEN MANCH_INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDONEIE RXDONEIE RXOVERIE BITERRIE IDLERRIE

TXDONEIE : Transmit Done Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Transmit frame done interrupt Disabled

#1 : 1

Transmit frame done interrupt Enabled

End of enumeration elements list.

RXDONEIE : Receive Frame Done Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Receive frame done interrupt Disabled

#1 : 1

Receive frame done interrupt Enabled

End of enumeration elements list.

RXOVERIE : Receive FIFO Overflow Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Receive FIFO overflow interrupt Disabled

#1 : 1

Receive FIFO overflow interrupt Enabled

End of enumeration elements list.

BITERRIE : Bit Detect Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

The Manchester bit error detected interrupt Disabled

#1 : 1

The Manchester bit error detected interrupt Enabled

End of enumeration elements list.

IDLERRIE : IDLE Pattern Error Interrupt Enable Bit
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

The Idle pattern error detected interrupt Disabled

#1 : 1

The Idle pattern error detected interrupt Enabled

End of enumeration elements list.


MANCH_STS (STS)

Manchester Status Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MANCH_STS MANCH_STS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDONE RXDONE RXOVER BITERR PRENERR TXUNDER IDLERR TXEMPTY TXFULL RXEMPTY RXFULL MTXEMPTY MTXFULL RXCNT RXBUSY

TXDONE : Transmit Frame Done Note: When the MANCHTEN is set, this bit will keep 0 until the data frame transmission is done.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Transmit frame is not done

#1 : 1

Transmit frame is done

End of enumeration elements list.

RXDONE : Receive Frame Done Note: This bit can be cleared by writing 1 to it.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Receive frame is not done

#1 : 1

Receive frame is done

End of enumeration elements list.

RXOVER : Receive FIFO Overflow Note: This bit can be cleared by writing 1 to it.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

The receive FIFO is not overflow

#1 : 1

The receive FIFO is overflow

End of enumeration elements list.

BITERR : Manchester Bit Error Note: This bit can be cleared by writing 1 to it.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

The Manchester bit error is not detected

#1 : 1

The Manchester bit error is detected. If the counter between two receive edge is greater than (RBITNUM + bit error tolerance) or less than (RBITNUM - bit error tolerance)

End of enumeration elements list.

PRENERR : Preamble Number Error Note: This bit can be cleared by writing 1 to it.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

The receive preamble number error is not detected

#1 : 1

The receive preamble number error is detected

End of enumeration elements list.

TXUNDER : Transmit FIFO Underrun Note: This bit can be cleared by writing 1 to it.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

The transmit FIFO is not underrun

#1 : 1

The transmit FIFO is underrun

End of enumeration elements list.

IDLERR : IDLE Error Note: This bit can be cleared by writing 1 to it.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

The receive Idle pattern error is not detected

#1 : 1

The receive Idle pattern error is detected

End of enumeration elements list.

TXEMPTY : Transmit FIFO Empty
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

The transmit FIFO is not empty

#1 : 1

The transmit FIFO is empty

End of enumeration elements list.

TXFULL : Transmit FIFO Full
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

The transmit FIFO is not full

#1 : 1

The transmit FIFO is full

End of enumeration elements list.

RXEMPTY : Received FIFO Empty
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

The received FIFO is not empty

#1 : 1

The received FIFO is empty

End of enumeration elements list.

RXFULL : Received FIFO Full
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

The received FIFO is not full

#1 : 1

The received FIFO is full

End of enumeration elements list.

MTXEMPTY : Manchester Transmit Encoded FIFO Empty
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

The Manchester transmit encoded FIFO is not empty

#1 : 1

The Manchester transmit encoded FIFO is empty

End of enumeration elements list.

MTXFULL : Manchester Transmit Encoded FIFO Full
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

The Manchester transmit encoded FIFO is not full

#1 : 1

The Manchester transmit encoded FIFO is full

End of enumeration elements list.

RXCNT : Receive Frame Data Current Count
bits : 16 - 23 (8 bit)
access : read-write

RXBUSY : Receive Busy Flag
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

The received bus is not busy

#1 : 1

The received bus is busy

End of enumeration elements list.


MANCH_BITCNT (BITCNT)

Manchester Bit Count Register
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MANCH_BITCNT MANCH_BITCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBITNUM RBITNUM CRBITNUM RBERRTN

TBITNUM : Manchester Transmit Reference Clock Number per Bit The bits field indicates the number of reference clock (Bit_Ref_Clock) for transmit bit. Note 1: The value of this bits field cannot be 0x00. Note 2: It is suggested the TBITNUM value is not less than 0x64.
bits : 0 - 7 (8 bit)
access : read-write

RBITNUM : Manchester Receive Reference Clock Number per Bit The bits field indicates the number of reference clock (Bit_Ref_Clock) for received bit. If there is not BITERR event, user can refer to the CRBITNUM to revise the RBITNUM. Note 1: The value of this bits field cannot be 0x00 and the tolerance value must be not 3% than the received input bit rate. Otherwise, it cannot receive the correct input data on time. Note 2: The bits can be updated at the start of next data frame if the RBNULEN is set to 1. Note 3: It is suggested that the RBITNUM value is not less than 0x64.
bits : 8 - 15 (8 bit)
access : read-write

CRBITNUM : Manchester Current Receive Reference Frequency Number per Bit (Read Only) The bits field indicates the current number of reference frequency (Bit_Ref_Clock) for each received bit.
bits : 16 - 23 (8 bit)
access : read-only

RBERRTN : Manchester Receive Bit Error Tolerance Number The bits field indicates the tolerance range of RBITNUM for received bit to detect the bit error event.
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

#000 : 0

1/4 RBITNUM as the bit error tolerance

#001 : 1

1/8 RBITNUM as the bit error tolerance

#010 : 2

1/16 RBITNUM as the bit error tolerance

#011 : 3

1/32 RBITNUM as the bit error tolerance

#100 : 4

1/64 RBITNUM as the bit error tolerance

#101 : 5

1/128 RBITNUM as the bit error tolerance

End of enumeration elements list.


MANCH_TXDAT (TXDAT)

Manchester Transmit Data Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MANCH_TXDAT MANCH_TXDAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDAT

TXDAT : Manchester Transmit Data The bits field indicates the transmit data.
bits : 0 - 7 (8 bit)
access : read-write


MANCH_RXDAT (RXDAT)

Manchester Receive Data Register
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MANCH_RXDAT MANCH_RXDAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDAT

RXDAT : Manchester Receive Data The bits field indicates the received data.
bits : 0 - 7 (8 bit)
access : read-only


MANCH_MTXDAT (MTXDAT)

Manchester Transmit Encoded Data Register
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MANCH_MTXDAT MANCH_MTXDAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTXDAT

MTXDAT : Manchester Encoded Data The bits field indicates the current Manchester encoded data in FIFO.
bits : 0 - 15 (16 bit)
access : read-only


MANCH_PREAM (PREAM)

Manchester Preamble Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MANCH_PREAM MANCH_PREAM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREAMBLE PRENUM IDLEPAT FMTNUM

PREAMBLE : Preamble Format The bits field defines the preamble pattern in the modulation signal format. If MODESEL is 2'b10, the PREAMBLE will be set as 0x7E.
bits : 0 - 7 (8 bit)
access : read-write

PRENUM : Preamble Number The bits field defines the number of preamble in the modulation signal format. 00000: means there are 32 preamble patterns. 00001: means there is 1 preamble pattern. 00010: means there are 2 preamble patterns. 00011: means there are 3 preamble patterns. and so on If MODESEL is 2'b01, the PRENUM will be set as 0x5. If MODESEL is 2'b10, the PRENUM will be set as 0x4.
bits : 8 - 12 (5 bit)
access : read-write

IDLEPAT : Idle Pattern The bits field indicates the bus idle pattern. If it is 0x00, it indicates that the bus idle default is low. If it is 0xFF, it indicates that the bus idle default is high. Except the bus idle state is LOW, the bits field must be set before the Controller is Enabled.
bits : 16 - 23 (8 bit)
access : read-write

FMTNUM : Modulation Format Transmit Number The bits field defines the number of transmitted byte number in current selected mode. If MODESEL is 0x1, the FMTNUM will be forced as 0x1E. If MODESEL is 0x2, the FMTNUM will be forced as 0x40. If MODESEL is 0x3, the modulation transmit number will be FMTNUM. Note 1: If FMTNUM is 0x00, which indicates the transmit number is 256 Bytes. Note 2: The value of FMTNUM must be greater than PRENUM Note 3: The minimum value of FMTNUM must be greater than 1.
bits : 24 - 31 (8 bit)
access : read-write


MANCH_FIFOCTL (FIFOCTL)

Manchester FIFO Control Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MANCH_FIFOCTL MANCH_FIFOCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCLR RXCLR TXFCNT RXFCNT MTXFCNT

TXCLR : Transmit FIFO Clear
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Both of Transmit FIFO and Manchester Transmit encoded FIFO are not cleared

#1 : 1

Both of Transmit FIFO and Manchester Transmit encoded FIFO are cleared

End of enumeration elements list.

RXCLR : Received FIFO Clear Note: The received control includes the FIFO and receive state machine. For example, if there is noise in the bus, the Manchester Controller will report BITERR flag when it detects the bit width greater than the setting. If the number of bit error event is greater than the software threshold, then set RXCLR to reset the receive state machine. The Manchester Controller will re-detect the IDLEPAT again.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Received control is not cleared

#1 : 1

Received control is cleared

End of enumeration elements list.

TXFCNT : Transmitted FIFO Count (Read Only) The bits field indicates the current counter number of transmitted FIFO for transmitting data.
bits : 8 - 10 (3 bit)
access : read-only

RXFCNT : Received FIFO Count (Read Only) The bits field indicates the current counter number of received FIFO for decoded data.
bits : 12 - 14 (3 bit)
access : read-only

MTXFCNT : Manchester Transmit Encoded FIFO Count (Read Only) The bits field indicates the current counter number of transmitted encoded FIFO for encoded data.
bits : 16 - 18 (3 bit)
access : read-only



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