Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x40 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection :
DAC2 Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACEN : DAC Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
DAC Disabled
#1 : 1
DAC Enabled
End of enumeration elements list.
DACIEN : DAC Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
DAC interrupt Disabled
#1 : 1
DAC interrupt Enabled
End of enumeration elements list.
DMAEN : DMA Mode Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA mode Disabled
#1 : 1
DMA mode Enabled
End of enumeration elements list.
DMAURIEN : DMA Under-run Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA under-run interrupt Disabled
#1 : 1
DMA under-run interrupt Enabled
End of enumeration elements list.
TRGEN : Trigger Mode Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
DAC event trigger mode Disabled
#1 : 1
DAC event trigger mode Enabled
End of enumeration elements list.
TRGSEL : Trigger Source Selection
bits : 5 - 7 (3 bit)
access : read-write
Enumeration:
#000 : 0
Software trigger
#001 : 1
Timer 2 trigger
#010 : 2
Timer 0 trigger
#011 : 3
Timer 1 trigger
#100 : 4
Timer 3 trigger
#101 : 5
Timer 4 trigger
#110 : 6
BPWM 1 trigger
#111 : 7
Timer 5 trigger
End of enumeration elements list.
BYPASS : Bypass Buffer Mode
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output voltage buffer Enabled
#1 : 1
Output voltage buffer Disabled
End of enumeration elements list.
LALIGN : DAC Data Left-aligned Enabled Bit
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Right alignment
#1 : 1
Left alignment
End of enumeration elements list.
ETRGSEL : External Pin Trigger Selection
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 0
Low level trigger
#01 : 1
High level trigger
#10 : 2
Falling edge trigger
#11 : 3
Rising edge trigger
End of enumeration elements list.
BWSEL : DAC Data Bit-width Selection
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 0
Data is 12 bits
#01 : 1
Data is 8 bits
End of enumeration elements list.
GRPEN : DAC Group Mode Enable Bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
DAC2 and DAC3 are not grouped
#1 : 1
DAC2 and DAC3 are grouped
End of enumeration elements list.
RETEN : DAC Reset Retention Select (Write Protect)
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: This bit only exists in DAC0 control register to control 4 DAC retention.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
DAC controller registers reset by POR, NRESET, WDT, LVR, BOD, Lockup, CHIP and MCU reset sources
#1 : 1
DAC controller registers reset by POR, LVR, BOD and Lockup reset sources
End of enumeration elements list.
DAC2 Status Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FINISH : DAC Conversion Complete Finish Flag
Note: This bit is set to 1 when conversion time counter counts to SETTLET. It is cleared to 0 when DAC starts a new conversion. Write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
DAC is in conversion state
#1 : 1
DAC conversion finish
End of enumeration elements list.
DMAUDR : DMA Under-run Interrupt Flag
Note: Write 1 to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No DMA under-run error condition occurred
#1 : 1
DMA under-run error condition occurred
End of enumeration elements list.
BUSY : DAC Busy Flag (Read Only)
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
DAC is ready for next conversion
#1 : 1
DAC is busy in conversion
End of enumeration elements list.
DAC2 Timing Control Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETTLET : DAC Output Conversion Cycles
User software needs to write appropriate value to these bits to meet DAC conversion settling time based on PCLK (APB clock) speed.
For example, DAC controller clock speed is 72 MHz and DAC conversion setting time is 1 us, and SETTLET value must be greater than 0x48.
Note: The DAC output Conversion cycles is SETTLET + 1 PCLK cycles.
bits : 0 - 9 (10 bit)
access : read-write
DAC2 Software Trigger Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWTRG : Software Trigger
Note: Writing this bit will generate one shot pulse and this bit is cleared to 0 by hardware automatically reading this bit will always get 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Software trigger Disabled
#1 : 1
Software trigger Enabled
End of enumeration elements list.
DAC3 Control Register
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACEN : DAC Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
DAC Disabled
#1 : 1
DAC Enabled
End of enumeration elements list.
DACIEN : DAC Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
DAC interrupt Disabled
#1 : 1
DAC interrupt Enabled
End of enumeration elements list.
DMAEN : DMA Mode Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA mode Disabled
#1 : 1
DMA mode Enabled
End of enumeration elements list.
DMAURIEN : DMA Under-run Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA under-run interrupt Disabled
#1 : 1
DMA under-run interrupt Enabled
End of enumeration elements list.
TRGEN : Trigger Mode Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
DAC event trigger mode Disabled
#1 : 1
DAC event trigger mode Enabled
End of enumeration elements list.
TRGSEL : Trigger Source Selection
bits : 5 - 7 (3 bit)
access : read-write
Enumeration:
#000 : 0
Software trigger
#001 : 1
Timer 2 trigger
#010 : 2
Timer 0 trigger
#011 : 3
Timer 1 trigger
#100 : 4
Timer 3 trigger
#101 : 5
Timer 4 trigger
#110 : 6
BPWM 1 trigger
#111 : 7
Timer 5 trigger
End of enumeration elements list.
BYPASS : Bypass Buffer Mode
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output voltage buffer Enabled
#1 : 1
Output voltage buffer Disabled
End of enumeration elements list.
LALIGN : DAC Data Left-aligned Enable Control
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Right alignment
#1 : 1
Left alignment
End of enumeration elements list.
ETRGSEL : External Pin Trigger Selection
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 0
Low level trigger
#01 : 1
High level trigger
#10 : 2
Falling edge trigger
#11 : 3
Rising edge trigger
End of enumeration elements list.
BWSEL : DAC Data Bit-width Selection
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 0
Data is 12 bits
#01 : 1
Data is 8 bits
End of enumeration elements list.
DAC3 Software Trigger Control Register
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWTRG : Software Trigger
Note: Writing this bit will generate one shot pulse and this bit is cleared to 0 by hardware automatically reading this bit will always get 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Software trigger Disabled
#1 : 1
Software trigger Enabled
End of enumeration elements list.
DAC3 Data Holding Register
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACDAT : DAC 12-bit Holding Data
These bits are written by user software which specifies 12-bit conversion data for DAC output. The unused bits (DAC3_DAT[3:0] in left-alignment mode and DAC3_DAT[15:12] in right alignment mode) are ignored by DAC controller hardware.
12 bit left alignment: user has to load data into DAC3_DAT[15:4] bits.
12 bit right alignment: user has to load data into DAC3_DAT[11:0] bits.
bits : 0 - 15 (16 bit)
access : read-write
DAC3 Data Output Register
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATOUT : DAC 12-bit Output Data
These bits are current digital data for DAC output conversion.
It is loaded from DAC3_DAT register and user cannot write it directly.
bits : 0 - 11 (12 bit)
access : read-only
DAC3 Status Register
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FINISH : DAC Conversion Complete Finish Flag
Note: This bit set to 1 when conversion time counter counts to SETTLET. It is cleared to 0 when DAC starts a new conversion. Write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
DAC is in conversion state
#1 : 1
DAC conversion finished
End of enumeration elements list.
DMAUDR : DMA Under-run Interrupt Flag
Note: Write 1 to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No DMA under-run error condition occurred
#1 : 1
DMA under-run error condition occurred
End of enumeration elements list.
BUSY : DAC Busy Flag (Read Only)
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
DAC is ready for the next conversion
#1 : 1
DAC is busy in conversion
End of enumeration elements list.
DAC3 Timing Control Register
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETTLET : DAC Output Conversion Cycles
User software needs to write appropriate value to these bits to meet DAC conversion settling time based on PCLK (APB clock) speed.
For example, DAC controller clock speed is 72 MHz and DAC conversion settling time is 1 us, and SETTLET value must be greater than 0x48.
Note: The DAC output conversion cycles is SETTLET + 1 PCLK cycles.
bits : 0 - 9 (10 bit)
access : read-write
DAC2 Data Holding Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACDAT : DAC 12-bit Holding Data
These bits are written by user software which specifies 12-bit conversion data for DAC output. The unused bits (DAC2_DAT[3:0] in left-alignment mode and DAC2_DAT[15:12] in right alignment mode) are ignored by DAC controller hardware.
12 bit left alignment: user has to load data into DAC2_DAT[15:4] bits.
12 bit right alignment: user has to load data into DAC2_DAT[11:0] bits.
bits : 0 - 15 (16 bit)
access : read-write
DAC2 Data Output Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATOUT : DAC 12-bit Output Data
These bits are current digital data for DAC output conversion.
It is loaded from DAC2_DAT register and user cannot write it directly.
bits : 0 - 11 (12 bit)
access : read-only
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