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DAC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x1C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x40 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x60 Bytes (0x0)
size : 0x80 byte (0x0)
mem_usage : registers
protection :

Registers

DAC0_CTL

DAC0_STATUS

DAC0_TCTL

DAC0_ADGCTL

DAC0_SWTRG

DAC1_CTL

DAC1_SWTRG

DAC1_DAT

DAC1_DATOUT

DAC1_STATUS

DAC1_TCTL

DAC_ADCTL0 (ADCTL0)

DAC_ADCTL1 (ADCTL1)

DAC_ADCTL2 (ADCTL2)

DAC_ADCTL3 (ADCTL3)

DAC_ADCTL4 (ADCTL4)

DAC_ADCTL5 (ADCTL5)

DAC_ADCTL6 (ADCTL6)

DAC_ADCTL7 (ADCTL7)

DAC0_DAT

DAC_ADCTL8 (ADCTL8)

DAC_ADCTL9 (ADCTL9)

DAC_ADCTL10 (ADCTL10)

DAC_ADCTL11 (ADCTL11)

DAC_ADCTL12 (ADCTL12)

DAC_ADCTL13 (ADCTL13)

DAC_ADCTL14 (ADCTL14)

DAC_ADCTL15 (ADCTL15)

DAC_ADCTL16 (ADCTL16)

DAC_ADCTL17 (ADCTL17)

DAC_ADCTL18 (ADCTL18)

DAC_ADCTL19 (ADCTL19)

DAC_ADCTL20 (ADCTL20)

DAC_ADCTL21 (ADCTL21)

DAC_ADCTL22 (ADCTL22)

DAC_ADCTL23 (ADCTL23)

DAC0_DATOUT

DAC_ADCTL24 (ADCTL24)

DAC_ADCTL25 (ADCTL25)

DAC_ADCTL26 (ADCTL26)

DAC_ADCTL27 (ADCTL27)

DAC_ADCTL28 (ADCTL28)

DAC_ADCTL29 (ADCTL29)

DAC_ADCTL30 (ADCTL30)

DAC_ADCTL31 (ADCTL31)


DAC0_CTL

DAC0 Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC0_CTL DAC0_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACEN DACIEN DMAEN DMAURIEN TRGEN TRGSEL BYPASS LALIGN ETRGSEL BWSEL GRPEN RETEN

DACEN : DAC Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

DAC Disabled

#1 : 1

DAC Enabled

End of enumeration elements list.

DACIEN : DAC Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

DAC interrupt Disabled

#1 : 1

DAC interrupt Enabled

End of enumeration elements list.

DMAEN : DMA Mode Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA mode Disabled

#1 : 1

DMA mode Enabled

End of enumeration elements list.

DMAURIEN : DMA Under-run Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA under-run interrupt Disabled

#1 : 1

DMA under-run interrupt Enabled

End of enumeration elements list.

TRGEN : Trigger Mode Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

DAC event trigger mode Disabled

#1 : 1

DAC event trigger mode Enabled

End of enumeration elements list.

TRGSEL : Trigger Source Selection
bits : 5 - 7 (3 bit)
access : read-write

Enumeration:

#000 : 0

Software trigger

#001 : 1

Timer 2 trigger

#010 : 2

Timer 0 trigger

#011 : 3

Timer 1 trigger

#100 : 4

Timer 3 trigger

#101 : 5

Timer 4 trigger

#110 : 6

BPWM 1 trigger

#111 : 7

Timer 5 trigger

End of enumeration elements list.

BYPASS : Bypass Buffer Mode
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Output voltage buffer Enabled

#1 : 1

Output voltage buffer Disabled

End of enumeration elements list.

LALIGN : DAC Data Left-aligned Enabled Bit
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Right alignment

#1 : 1

Left alignment

End of enumeration elements list.

ETRGSEL : External Pin Trigger Selection
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

#00 : 0

Low level trigger

#01 : 1

High level trigger

#10 : 2

Falling edge trigger

#11 : 3

Rising edge trigger

End of enumeration elements list.

BWSEL : DAC Data Bit-width Selection
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

#00 : 0

Data is 12 bits

#01 : 1

Data is 8 bits

End of enumeration elements list.

GRPEN : DAC Group Mode Enable Bit
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

DAC0 and DAC1 are not grouped

#1 : 1

DAC0 and DAC1 are grouped

End of enumeration elements list.

RETEN : DAC Reset Retention Select (Write Protect) Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: This bit only exists in DAC0 control register to control 4 DAC retention.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

DAC controller registers reset by POR, NRESET, WDT, LVR, BOD, Lockup, CHIP and MCU reset sources

#1 : 1

DAC controller registers reset by POR, LVR, BOD and Lockup reset sources

End of enumeration elements list.


DAC0_STATUS

DAC0 Status Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC0_STATUS DAC0_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FINISH DMAUDR BUSY

FINISH : DAC Conversion Complete Finish Flag Note: This bit is set to 1 when conversion time counter counts to SETTLET. It is cleared to 0 when DAC starts a new conversion. Write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

DAC is in conversion state

#1 : 1

DAC conversion finish

End of enumeration elements list.

DMAUDR : DMA Under-run Interrupt Flag Note: Write 1 to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No DMA under-run error condition occurred

#1 : 1

DMA under-run error condition occurred

End of enumeration elements list.

BUSY : DAC Busy Flag (Read Only)
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

#0 : 0

DAC is ready for next conversion

#1 : 1

DAC is busy in conversion

End of enumeration elements list.


DAC0_TCTL

DAC0 Timing Control Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC0_TCTL DAC0_TCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETTLET

SETTLET : DAC Output Conversion Cycles User software needs to write appropriate value to these bits to meet DAC conversion settling time based on PCLK (APB clock) speed. For example, DAC controller clock speed is 72 MHz and DAC conversion setting time is 1 us, and SETTLET value must be greater than 0x48. Note: The DAC output conversion cycles is SETTLET + 1 PCLK cycles
bits : 0 - 9 (10 bit)
access : read-write


DAC0_ADGCTL

DAC0 Auto Data Generator Control Register
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC0_ADGCTL DAC0_ADGCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AUTOEN CPOSEL SAMPSEL

AUTOEN : DAC Auto Data Generation Mode Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

DAC auto data generation mode Disabled

#1 : 1

DAC auto data generation mode Enabled

End of enumeration elements list.

CPOSEL : Carrier Polarity Selection
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Auto data update for DAC when MANCH_TXD data high

#1 : 1

Auto data update for DAC when MANCH_TXD data is low

End of enumeration elements list.

SAMPSEL : Sample Points Step Selection
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 0

No samples

#01 : 1

8 sample points per MANCH_TXD carrier cycle

#10 : 2

16 sample points per MANCH_TXD carrier cycle

#11 : 3

32 sample points per MANCH_TXD carrier cycle

End of enumeration elements list.


DAC0_SWTRG

DAC0 Software Trigger Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC0_SWTRG DAC0_SWTRG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWTRG

SWTRG : Software Trigger Note: Writing this bit will generate one shot pulse and this bit is cleared to 0 by hardware automatically reading this bit will always get 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Software trigger Disabled

#1 : 1

Software trigger Enabled

End of enumeration elements list.


DAC1_CTL

DAC1 Control Register
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC1_CTL DAC1_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACEN DACIEN DMAEN DMAURIEN TRGEN TRGSEL BYPASS LALIGN ETRGSEL BWSEL

DACEN : DAC Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

DAC Disabled

#1 : 1

DAC Enabled

End of enumeration elements list.

DACIEN : DAC Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

DAC interrupt Disabled

#1 : 1

DAC interrupt Enabled

End of enumeration elements list.

DMAEN : DMA Mode Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA mode Disabled

#1 : 1

DMA mode Enabled

End of enumeration elements list.

DMAURIEN : DMA Under-run Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA under-run interrupt Disabled

#1 : 1

DMA under-run interrupt Enabled

End of enumeration elements list.

TRGEN : Trigger Mode Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

DAC event trigger mode Disabled

#1 : 1

DAC event trigger mode Enabled

End of enumeration elements list.

TRGSEL : Trigger Source Selection
bits : 5 - 7 (3 bit)
access : read-write

Enumeration:

#000 : 0

Software trigger

#001 : 1

Timer 2 trigger

#010 : 2

Timer 0 trigger

#011 : 3

Timer 1 trigger

#100 : 4

Timer 3 trigger

#101 : 5

Timer 4 trigger

#110 : 6

BPWM 1 trigger

#111 : 7

Timer 5 trigger

End of enumeration elements list.

BYPASS : Bypass Buffer Mode
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Output voltage buffer Enabled

#1 : 1

Output voltage buffer Disabled

End of enumeration elements list.

LALIGN : DAC Data Left-aligned Enable Control
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Right alignment

#1 : 1

Left alignment

End of enumeration elements list.

ETRGSEL : External Pin Trigger Selection
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

#00 : 0

Low level trigger

#01 : 1

High level trigger

#10 : 2

Falling edge trigger

#11 : 3

Rising edge trigger

End of enumeration elements list.

BWSEL : DAC Data Bit-width Selection
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

#00 : 0

Data is 12 bits

#01 : 1

Data is 8 bits

End of enumeration elements list.


DAC1_SWTRG

DAC1 Software Trigger Control Register
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC1_SWTRG DAC1_SWTRG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWTRG

SWTRG : Software Trigger Note: Writing this bit will generate one shot pulse and this bit is cleared to 0 by hardware automatically Reading this bit will always get 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Software trigger Disabled

#1 : 1

Software trigger Enabled

End of enumeration elements list.


DAC1_DAT

DAC1 Data Holding Register
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC1_DAT DAC1_DAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACDAT

DACDAT : DAC 12-bit Holding Data These bits are written by user software which specifies 12-bit conversion data for DAC output. The unused bits (DAC1_DAT[3:0] in left-alignment mode and DAC1_DAT[15:12] in right alignment mode) are ignored by DAC controller hardware. 12-bit left alignment: user has to load data into DAC1_DAT[15:4] bits. 12-bit right alignment: user has to load data into DAC1_DAT[11:0] bits.
bits : 0 - 15 (16 bit)
access : read-write


DAC1_DATOUT

DAC1 Data Output Register
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DAC1_DATOUT DAC1_DATOUT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATOUT

DATOUT : DAC 12-bit Output Data These bits are current digital data for DAC output conversion. It is loaded from DAC1_DAT register and user cannot write it directly.
bits : 0 - 11 (12 bit)
access : read-only


DAC1_STATUS

DAC1 Status Register
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC1_STATUS DAC1_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FINISH DMAUDR BUSY

FINISH : DAC Conversion Complete Finish Flag Note: This bit set to 1 when conversion time counter counts to SETTLET. It is cleared to 0 when DAC starts a new conversion. Write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

DAC is in conversion state

#1 : 1

DAC conversion finished

End of enumeration elements list.

DMAUDR : DMA Under-run Interrupt Flag Note: Write 1 to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No DMA under-run error condition occurred

#1 : 1

DMA under-run error condition occurred

End of enumeration elements list.

BUSY : DAC Busy Flag (Read Only)
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

#0 : 0

DAC is ready for the next conversion

#1 : 1

DAC is busy in conversion

End of enumeration elements list.


DAC1_TCTL

DAC1 Timing Control Register
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC1_TCTL DAC1_TCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETTLET

SETTLET : DAC Output Conversion Cycles User software needs to write appropriate value to these bits to meet DAC conversion settling time based on PCLK (APB clock) speed. For example, DAC controller clock speed is 72 MHz and DAC conversion settling time is 1 us, and SETTLET value must be greater than 0x48. Note: The DAC output conversion cycles is SETTLET + 1 PCLK cycles
bits : 0 - 9 (10 bit)
access : read-write


DAC_ADCTL0 (ADCTL0)

DAC Auto Data Control Register0
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_ADCTL0 DAC_ADCTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AUTODATA

AUTODATA : Data Input of Auto Data Generation Function User software needs to write appropriate data value to these bits for DAC auto data generation.
bits : 0 - 11 (12 bit)
access : read-write


DAC_ADCTL1 (ADCTL1)

DAC Auto Data Control Register1
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_ADCTL1 DAC_ADCTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAC_ADCTL2 (ADCTL2)

DAC Auto Data Control Register2
address_offset : 0x68 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_ADCTL2 DAC_ADCTL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAC_ADCTL3 (ADCTL3)

DAC Auto Data Control Register3
address_offset : 0x6C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_ADCTL3 DAC_ADCTL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAC_ADCTL4 (ADCTL4)

DAC Auto Data Control Register4
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_ADCTL4 DAC_ADCTL4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAC_ADCTL5 (ADCTL5)

DAC Auto Data Control Register5
address_offset : 0x74 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_ADCTL5 DAC_ADCTL5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAC_ADCTL6 (ADCTL6)

DAC Auto Data Control Register6
address_offset : 0x78 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_ADCTL6 DAC_ADCTL6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAC_ADCTL7 (ADCTL7)

DAC Auto Data Control Register7
address_offset : 0x7C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_ADCTL7 DAC_ADCTL7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAC0_DAT

DAC0 Data Holding Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC0_DAT DAC0_DAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACDAT

DACDAT : DAC 12-bit Holding Data These bits are written by user software which specifies 12-bit conversion data for DAC output. The unused bits (DAC0_DAT[3:0] in left-alignment mode and DAC0_DAT[15:12] in right alignment mode) are ignored by DAC controller hardware. 12-bit left alignment: user has to load data into DAC0_DAT[15:4] bits. 12-bit right alignment: user has to load data into DAC0_DAT[11:0] bits.
bits : 0 - 15 (16 bit)
access : read-write


DAC_ADCTL8 (ADCTL8)

DAC Auto Data Control Register8
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_ADCTL8 DAC_ADCTL8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAC_ADCTL9 (ADCTL9)

DAC Auto Data Control Register9
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_ADCTL9 DAC_ADCTL9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAC_ADCTL10 (ADCTL10)

DAC Auto Data Control Register10
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_ADCTL10 DAC_ADCTL10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAC_ADCTL11 (ADCTL11)

DAC Auto Data Control Register11
address_offset : 0x8C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_ADCTL11 DAC_ADCTL11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAC_ADCTL12 (ADCTL12)

DAC Auto Data Control Register12
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_ADCTL12 DAC_ADCTL12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAC_ADCTL13 (ADCTL13)

DAC Auto Data Control Register13
address_offset : 0x94 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_ADCTL13 DAC_ADCTL13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAC_ADCTL14 (ADCTL14)

DAC Auto Data Control Register14
address_offset : 0x98 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_ADCTL14 DAC_ADCTL14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAC_ADCTL15 (ADCTL15)

DAC Auto Data Control Register15
address_offset : 0x9C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_ADCTL15 DAC_ADCTL15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAC_ADCTL16 (ADCTL16)

DAC Auto Data Control Register16
address_offset : 0xA0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_ADCTL16 DAC_ADCTL16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAC_ADCTL17 (ADCTL17)

DAC Auto Data Control Register17
address_offset : 0xA4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_ADCTL17 DAC_ADCTL17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAC_ADCTL18 (ADCTL18)

DAC Auto Data Control Register18
address_offset : 0xA8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_ADCTL18 DAC_ADCTL18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAC_ADCTL19 (ADCTL19)

DAC Auto Data Control Register19
address_offset : 0xAC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_ADCTL19 DAC_ADCTL19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAC_ADCTL20 (ADCTL20)

DAC Auto Data Control Register20
address_offset : 0xB0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_ADCTL20 DAC_ADCTL20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAC_ADCTL21 (ADCTL21)

DAC Auto Data Control Register21
address_offset : 0xB4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_ADCTL21 DAC_ADCTL21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAC_ADCTL22 (ADCTL22)

DAC Auto Data Control Register22
address_offset : 0xB8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_ADCTL22 DAC_ADCTL22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAC_ADCTL23 (ADCTL23)

DAC Auto Data Control Register23
address_offset : 0xBC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_ADCTL23 DAC_ADCTL23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAC0_DATOUT

DAC0 Data Output Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DAC0_DATOUT DAC0_DATOUT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATOUT

DATOUT : DAC 12-bit Output Data These bits are current digital data for DAC output conversion. It is loaded from DAC0_DAT register and user cannot write it directly.
bits : 0 - 11 (12 bit)
access : read-only


DAC_ADCTL24 (ADCTL24)

DAC Auto Data Control Register24
address_offset : 0xC0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_ADCTL24 DAC_ADCTL24 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAC_ADCTL25 (ADCTL25)

DAC Auto Data Control Register25
address_offset : 0xC4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_ADCTL25 DAC_ADCTL25 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAC_ADCTL26 (ADCTL26)

DAC Auto Data Control Register26
address_offset : 0xC8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_ADCTL26 DAC_ADCTL26 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAC_ADCTL27 (ADCTL27)

DAC Auto Data Control Register27
address_offset : 0xCC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_ADCTL27 DAC_ADCTL27 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAC_ADCTL28 (ADCTL28)

DAC Auto Data Control Register28
address_offset : 0xD0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_ADCTL28 DAC_ADCTL28 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAC_ADCTL29 (ADCTL29)

DAC Auto Data Control Register29
address_offset : 0xD4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_ADCTL29 DAC_ADCTL29 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAC_ADCTL30 (ADCTL30)

DAC Auto Data Control Register30
address_offset : 0xD8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_ADCTL30 DAC_ADCTL30 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAC_ADCTL31 (ADCTL31)

DAC Auto Data Control Register31
address_offset : 0xDC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_ADCTL31 DAC_ADCTL31 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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