FMC_ISPCTL (ISPCTL)

FMC_ISPTRG (ISPTRG)

FMC_ISPADDR (ISPADDR)

FMC_ISPSTS (ISPSTS)

FMC_CYCCTL (CYCCTL)

FMC_ISPDAT (ISPDAT)

FMC_MPDAT0 (MPDAT0)

FMC_MPDAT1 (MPDAT1)

FMC_MPDAT2 (MPDAT2)

FMC_MPDAT3 (MPDAT3)

FMC_ISPCMD (ISPCMD)

FMC_MPSTS (MPSTS)

FMC_MPADDR (MPADDR)

FMC_XOMR0STS (XOMR0STS)

FMC_XOMR1STS (XOMR1STS)

FMC_XOMR2STS (XOMR2STS)

FMC_XOMR3STS (XOMR3STS)

FMC_XOMSTS (XOMSTS)

ISPEN : ISP Enable Bit (Write Protect) ISP function enable bit. Set this bit to enable ISP function. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BS : Boot Select (Write Protect) When MBS in CONFIG0 is 1, set/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

APUEN : APROM Update Enable Bit (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFGUEN : CONFIG Update Enable Bit (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LDUEN : LDROM Update Enable Bit (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISPFF : ISP Fail Flag (Write Protect) This bit is set by hardware when a triggered ISP meets any of the following conditions: This bit needs to be cleared by writing 1 to it. APROM writes to itself if APUEN is set to 0. LDROM writes to itself if LDUEN is set to 0. CONFIG is erased/programmed if CFGUEN is set to 0. Erase or Program command at brown-out detected Destination address is illegal, such as over an available range. Invalid ISP commands The base and size of new XOM regions is wrong, overlap or writed twice The input setting of XOM page erase function is wrong The active XOM regions is accessed (except for chip erase, page erase, checksum and read CID/DID) The XOM setting page is accessed (except for chip erase, word program and read) Violate the load code read protection Checksum or Flash All One Verification is not executed in their valid range Bank erase is not executed in APROM Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 6 - 6 (1 bit)
access : read-write

INTEN : Secure ISP INT Enable Bit (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register.Before using INT,user needs to clear the INTFLAG(FMC_ISPSTS[24]) make sure INT happen at correct time.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISPGO : ISP Start Trigger (Write Protect) Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISPADDR : ISP Address The M471V/M471K series is equipped with embedded Flash. ISPADDR[1:0] must be kept 00 for ISP 32-bit operation. ISPADDR[2:0] must be kept 000 for ISP 64-bit operation. For CRC32 Checksum Calculation command, this field is the Flash starting address for checksum calculation, 2 Kbytes alignment is necessary for CRC32 checksum calculation. For Flash32-bit Program, ISP address needs word alignment (4-byte). For Flash 64-bit Program, ISP address needs double word alignment (8-byte).
bits : 0 - 31 (32 bit)
access : read-write

ISPBUSY : ISP Busy Flag (Read Only) Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CBS : Boot Selection of CONFIG (Read Only) This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened.
bits : 1 - 2 (2 bit)
access : read-only

Enumeration:

End of enumeration elements list.

FCYCDIS : Flash Access Cycle Auto-tuning Disable Flag (Read Only) This bit is set if Flash access cycle auto-tunning function is disabled. The auto-tunning function is disabled by FADIS(FMC_CYCCTL[8]) or HIRC clock is not ready.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PGFF : Flash Program with Fast Verification Flag (Read Only) This bit is set if data is mismatched at ISP programming verification. This bit is clear by performing ISP Flash erase or ISP read CID operation
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ISPFF : ISP Fail Flag (Write Protect) This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions: APROM writes to itself if APUEN is set to 0. LDROM writes to itself if LDUEN is set to 0. CONFIG is erased/programmed if CFGUEN is set to 0. Erase or Program command at brown-out detected Destination address is illegal, such as over an available range. Invalid ISP commands The base and size of new XOM regions is wrong, overlap or writed twice The input setting of XOM page erase function is wrong The active XOM regions is accessed (except for chip erase, page erase, checksum and read CID/DID) The XOM setting page is accessed (except for chip erase, word program and read) Violate the load code read protection Checksum or Flash All One Verification is not executed in their valid range Bank erase is not executed in APROM Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 6 - 6 (1 bit)
access : read-write

ALLONE : Flash All-one Verification Flag This bit is set by hardware if all of Flash bits are 1, and clear if Flash bits are not all 1 after 'Run Flash All-One Verification' complete this bit also can be clear by writing 1
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VECMAP : Vector Page Mapping Address (Read Only) All access to 0x0000_0000~0x0000_01FF is remapped to the Flash memory address {VECMAP[14:0], 9'h000} ~ {VECMAP[14:0], 9'h1FF}
bits : 9 - 23 (15 bit)
access : read-only

INTFLAG : ISP Interuppt Flag Note: This function needs to be enabled by FMC_ISPCTRL[24].
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CYCLE : Flash Access Cycle Control (Write Protect) This register is updated by software.User needs to check the speed of HCLK and set the cycle 0 The optimized HCLK working frequency range is 192 MHz Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FADIS : Flash Access Cycle Auto-tuning Disable Bit (Write Protect) Set this bit to disable Flash access cycle auto-tuning function Note: This bit is write protected. Refer to the SYS_REGLCTL register. When FMC is doing auto-tuning, we considered as an ISP operation need to monitor busy flag.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISPDAT : ISP Data Write data to this register before ISP program operation. Read data from this register after ISP read operation.
bits : 0 - 31 (32 bit)
access : read-write

ISPDAT0 : ISP Data 0 This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data.
bits : 0 - 31 (32 bit)
access : read-write

ISPDAT1 : ISP Data 1 This register is the second 32-bit data for 64-bit/multi-word programming.
bits : 0 - 31 (32 bit)
access : read-write

ISPDAT2 : ISP Data 2 This register is the third 32-bit data for multi-word programming.
bits : 0 - 31 (32 bit)
access : read-write

ISPDAT3 : ISP Data 3 This register is the fourth 32-bit data for multi-word programming.
bits : 0 - 31 (32 bit)
access : read-write

CMD : ISP Command ISP command table is shown below: The other commands are invalid.
bits : 0 - 6 (7 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MPBUSY : ISP Multi-word Program Busy Flag (Read Only) Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished. This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PPGO : ISP Multi-program Status (Read Only)
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ISPFF : ISP Fail Flag (Read Only) This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions: APROM writes to itself if APUEN is set to 0. LDROM writes to itself if LDUEN is set to 0. CONFIG is erased/programmed if CFGUEN is set to 0. Erase or Program command at brown-out detected Destination address is illegal, such as over an available range. Invalid ISP commands The base and size of new XOM regions is wrong, overlap or writed twice The input setting of XOM page erase function is wrong The active XOM regions is accessed (except for chip erase, page erase, checksum and read CID/DID) The XOM setting page is accessed (except for chip erase, word program and read) Violate the load code read protection Checksum or Flash All One Verification is not executed in their valid range Bank erase is not executed in APROM
bits : 2 - 2 (1 bit)
access : read-only

D0 : ISP DATA 0 Flag (Read Only) This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to Flash complete.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

D1 : ISP DATA 1 Flag (Read Only) This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to Flash complete.
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

D2 : ISP DATA 2 Flag (Read Only) This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to Flash complete.
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

D3 : ISP DATA 3 Flag (Read Only) This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to Flash complete.
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

MPADDR : ISP Multi-word Program Address MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1. MPADDR will keep the final ISP address when ISP multi-word program is complete.
bits : 0 - 31 (32 bit)
access : read-only

SIZE : XOM Region 0 Size (Page-aligned) SIZE is the page number of XOM Region 0.
bits : 0 - 7 (8 bit)
access : read-only

BASE : XOM Region 0 Base Address (Page-aligned) BASE is the base address of XOM Region 0.
bits : 8 - 31 (24 bit)
access : read-only

SIZE : XOM Region 1 Size (Page-aligned) SIZE is the page number of XOM Region 1.
bits : 0 - 7 (8 bit)
access : read-only

BASE : XOM Region 1 Base Address (Page-aligned) BASE is the base address of XOM Region 1.
bits : 8 - 31 (24 bit)
access : read-only

SIZE : XOM Region 2 Size (Page-aligned) SIZE is the page number of XOM Region 2.
bits : 0 - 7 (8 bit)
access : read-only

BASE : XOM Region 2 Base Address (Page-aligned) BASE is the base address of XOM Region 2.
bits : 8 - 31 (24 bit)
access : read-only

SIZE : XOM Region 3 Size (Page-aligned) SIZE is the page number of XOM Region 3.
bits : 0 - 7 (8 bit)
access : read-only

BASE : XOM Region 3 Base Address (Page-aligned) BASE is the base address of XOM Region 3.
bits : 8 - 31 (24 bit)
access : read-only

XOMR0ON : XOM Region 0 On XOM Region 0 active status.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

XOMR1ON : XOM Region 1 On XOM Region 1 active status.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

XOMR2ON : XOM Region 2 On XOM Region 2 active status.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

XOMR3ON : XOM Region 3 On XOM Region 3 active status.
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

XOMPEF : XOM Page Erase Function Fail XOM page erase function status. If XOMPEF is set to 1, user needs to erase XOM region again.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.