Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x10 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :
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size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x180 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x200 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x280 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x400 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :
SysTick Control and Status Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : System Tick Counter Enabled
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The counter is disabled
#1 : 1
The counter will operate in a multi-shot manner
End of enumeration elements list.
TICKINT : Enables SYST Exception Request
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to zero has occurred
#1 : 1
Counting down to 0 will cause SysTick exception to be pended. Clearing the SysTick current value register by a register write in software will not cause SysTick to be pended
End of enumeration elements list.
CLKSRC : System Tick Clock Source Selection
If no external clock provided, this bit will read as 1 and ignore writes.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
clock source is (optional) external reference clock
#1 : 1
core clock used for SysTick
End of enumeration elements list.
COUNTFLAG : System Tick Count Flag
Returns 1 if timer counted to 0 since last time this register was read.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Cleared on read or by a write to the Current Value register
#1 : 1
Set by a count transition from 1 to 0
End of enumeration elements list.
IRQ0 ~ IRQ15 Set-Enable Control Register
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA : Interrupt Set-Enable Bit
The NVIC_ISER register enables interrupts, and shows what interrupts are enabled. Each bit represents an interrupt number from IRQ0 ~ IRQ15 (Vector number from 16 ~ 31).
Write Operation:
bits : 0 - 15 (16 bit)
access : read-write
Enumeration:
0 : 0
No effect.
Interrupt Disabled
1 : 1
Interrupt Enabled
End of enumeration elements list.
SysTick Reload Value Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD : System Tick Reload Value
Value to load into the Current Value register when the counter reaches 0.
To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 200 clock pulses, set RELOAD to 199.
bits : 0 - 23 (24 bit)
access : read-write
SysTick Current Value Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CURRENT : System Tick Current Counter Value
This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0.
bits : 0 - 23 (24 bit)
access : read-write
IRQ0 ~ IRQ15 Clear-Enable Control Register
address_offset : 0x180 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRENA : Interrupt Clear-Enable Bit
The NVIC_ICER register disables interrupts, and shows what interrupts are enabled. Each bit represents an interrupt number from IRQ0 ~ IRQ15 (Vector number from 16 ~ 31).
Write Operation:
bits : 0 - 15 (16 bit)
access : read-write
Enumeration:
0 : 0
No effect.
Interrupt Disabled
1 : 1
Interrupt Disabled.
Interrupt Enabled
End of enumeration elements list.
IRQ0 ~ IRQ15 Set-Pending Control Register
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND : Interrupt Set-Pending Bit
The NVIC_ISPR register forces interrupts into the pending state, and shows what interrupts are pending. Each bit represents an interrupt number from IRQ0 ~ IRQ15 (Vector number from 16 ~ 31).
Write Operation:
bits : 0 - 15 (16 bit)
access : read-write
Enumeration:
0 : 0
No effect.
Interrupt is not pending
1 : 1
Changes interrupt state to pending.
Interrupt is pending
End of enumeration elements list.
IRQ0 ~ IRQ15 Clear-Pending Control Register
address_offset : 0x280 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRPEND : Interrupt Clear-Pending Bit
The NVIC_ICPR register removes the pending state of associated interrupts, and shows what interrupts are pending. Each bit represents an interrupt number from IRQ0 ~ IRQ15 (Vector number from 16 ~ 31).
Write Operation:
bits : 0 - 15 (16 bit)
access : read-write
Enumeration:
0 : 0
No effect.
Interrupt is not pending
1 : 1
Removes pending state of an interrupt.
Interrupt is pending
End of enumeration elements list.
IRQ0 ~ IRQ3 Priority Control Register
address_offset : 0x400 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : Priority Of IRQ0
0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write
PRI_1 : Priority Of IRQ1
0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write
PRI_2 : Priority Of IRQ2
0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write
PRI_3 : Priority Of IRQ3
0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write
IRQ4 ~ IRQ7 Priority Control Register
address_offset : 0x404 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_4 : Priority Of IRQ4
0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write
PRI_5 : Priority Of IRQ5
0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write
PRI_6 : Priority Of IRQ6
0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write
PRI_7 : Priority Of IRQ7
0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write
IRQ8 ~ IRQ11 Priority Control Register
address_offset : 0x408 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_8 : Priority Of IRQ8
0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write
PRI_9 : Priority Of IRQ9
0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write
PRI_10 : Priority Of IRQ10
0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write
PRI_11 : Priority Of IRQ11
0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write
IRQ12 ~ IRQ15 Priority Control Register
address_offset : 0x40C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_12 : Priority Of IRQ12
0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write
PRI_13 : Priority Of IRQ13
0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write
PRI_14 : Priority Of IRQ14
0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write
PRI_15 : Priority Of IRQ15
0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write
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