Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
User Configuration Memory
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCK : Security Lock
When flash data is locked,(1) only device ID, CONFIG can be read by Writer and ICP thru serial debug interface. Other data are locked as 0xFFFFFFFF.(2) ISP can read data in legal address regardless of LOCK bit value. (3) SWD interface cannot access internal RAM and Flash
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flash data are locked
#1 : 1
Flash data are not locked
End of enumeration elements list.
PRTB : Protection On 8K Bytes Flash
This bit is effective only for the part of 72KB flash.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
ISP function only can operate on the 64KB Flash (address: 0x0000~0xFFFF) and CONFIG, and cannot operate on the 8KB Flash (address: 0x10000~0x11FFF)
#1 : 1
ISP function can operate on the whole 72KB Flash (address: 0x00000~0x11FFF) and CONFIG
End of enumeration elements list.
CSPI0_FT : Fine Timing Control for SPI0 Data Receiving After Power On
The delay timing selected by CSPI0_CT can be further tuned finely by CSPI0_FT.
Note: The extra delay is implemented by delay chains. The accuracy of delay time would base on process deviation.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Receiving data clock has extra 7.5nS delay
#01 : 1
Receiving data clock has extra 5.0nS delay,
#10 : 2
Receiving data clock has extra 2.5nS delay,
#11 : 3
Receiving data clock has no extra delay,
End of enumeration elements list.
CSPI0_CT : Coarse Timing Control for SPI0 Data Receiving After Power On
These bits are used to adjust receiving clock for latching serial-in data correctly in high speed transmission mode.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Receiving data clock is same as the SPI0_CLK
#01 : 1
Receiving data clock is delayed 2 half SPI0_CLK clock cycle,
#10 : 2
Receiving data clock is delayed 3 half SPI0_CLK clock cycle,
#11 : 3
Receiving data clock is delayed 1 half SPI0_CLK clock cycle ,
End of enumeration elements list.
CVDTV : Voltage Detector Threshold Voltage Selection
bits : 21 - 21 (1 bit)
access : read-write
CVDEN : Voltage Detector Enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable Voltage Detector after power on
#1 : 1
Disable Voltage Detector after power on
End of enumeration elements list.
CWDTEN : Watchdog Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Watchdog is disabled after power on
#1 : 1
Watchdog is enabled after power on
End of enumeration elements list.
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