CTRL

NVIC_ISER

LOAD

VAL

NVIC_ICER

NVIC_ISPR

NVIC_ICPR

NVIC_IPR0

NVIC_IPR1

NVIC_IPR2

NVIC_IPR3

NVIC_IPR4

NVIC_IPR5

NVIC_IPR6

NVIC_IPR7

CPUID

ICSR

AIRCR

SCR

SHPR2

SHPR3

ENABLE : ENABLE
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TICKINT : Enables SysTick Exception Request
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKSRC : Clock Source
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

COUNTFLAG : Count Flag Returns 1 if timer counted to 0 since last time this register was read.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SETENA : Set-Enable Control Enable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47). Writing 1 will enable the associated interrupt. Writing 0 has no effect. The register reads back the current enable state.
bits : 0 - 31 (32 bit)
access : read-write

RELOAD : SysTick Reload Value to load into the Current Value register when the counter reaches 0. To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 200 clock pulses, set RELOAD to 199.
bits : 0 - 23 (24 bit)
access : read-write

CURRENT : Current Counter Value This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0 and also clear the COUNTFLAG bit.
bits : 0 - 23 (24 bit)
access : read-write

CLRENA : Clear-Enable Control Disable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47). Writing 1 will disable the associated interrupt. Writing 0 has no effect. The register reads back with the current enable state.
bits : 0 - 31 (32 bit)
access : read-write

SETPEND : Set-Pending Control Writing 1 to a bit forces pending state of the associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47). Writing 0 has no effect. The register reads back with the current pending state.
bits : 0 - 31 (32 bit)
access : read-write

CLRPEND : Clear-Pending Control Writing 1 to a bit to clear the pending state of associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47). Writing 0 has no effect. The register reads back with the current pending state.
bits : 0 - 31 (32 bit)
access : read-write

PRI_0 : Priority of IRQ0 0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write

PRI_1 : Priority of IRQ1 0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write

PRI_2 : Priority of IRQ2 0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write

PRI_3 : Priority of IRQ3 0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write

PRI_4 : Priority of IRQ4 0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write

PRI_5 : Priority of IRQ5 0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write

PRI_6 : Priority of IRQ6 0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write

PRI_7 : Priority of IRQ7 0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write

PRI_8 : Priority of IRQ8 0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write

PRI_9 : Priority of IRQ9 0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write

PRI_10 : Priority of IRQ10 0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write

PRI_11 : Priority of IRQ11 0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write

PRI_12 : Priority of IRQ12 0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write

PRI_13 : Priority of IRQ13 0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write

PRI_14 : Priority of IRQ14 0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write

PRI_15 : Priority of IRQ15 0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write

PRI_16 : Priority of IRQ16 0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write

PRI_17 : Priority of IRQ17 0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write

PRI_18 : Priority of IRQ18 0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write

PRI_19 : Priority of IRQ19 0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write

PRI_20 : Priority of IRQ20 0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write

PRI_21 : Priority of IRQ21 0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write

PRI_22 : Priority of IRQ22 0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write

PRI_23 : Priority of IRQ23 0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write

PRI_24 : Priority of IRQ24 0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write

PRI_25 : Priority of IRQ25 0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write

PRI_26 : Priority of IRQ26 0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write

PRI_27 : Priority of IRQ27 0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write

PRI_28 : Priority of IRQ28 0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write

PRI_29 : Priority of IRQ29 0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write

PRI_30 : Priority of IRQ30 0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write

PRI_31 : Priority of IRQ31 0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write

REVISION : Revision Reads as 0x0
bits : 0 - 3 (4 bit)
access : read-only

PARTNO : Part Number Reads as 0xC20.
bits : 4 - 15 (12 bit)
access : read-only

PART : ARMv6-M Parts Reads as 0xC for ARMv6-M parts
bits : 16 - 19 (4 bit)
access : read-only

IMPLEMENTER : Implementer Code Assigned By ARM ARM = 0x41.
bits : 24 - 31 (8 bit)
access : read-only

VECTACTIVE : Vector Active 0: Thread mode Value > 1: the exception number for the current executing exception.
bits : 0 - 8 (9 bit)
access : read-write

VECTPENDING : Vector Pending Indicates the exception number for the highest priority pending exception. The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier. A value of zero indicates no pending exceptions.
bits : 12 - 20 (9 bit)
access : read-write

ISRPENDING : ISR Pending Indicates if an external configurable (NVIC generated) interrupt is pending.
bits : 22 - 22 (1 bit)
access : read-write

ISRPREEMPT : ISR Preemptive If set, a pending exception will be serviced on exit from the debug halt state.
bits : 23 - 23 (1 bit)
access : read-write

PENDSTCLR : Clear A pending SysTick Write 1 to clear a pending SysTick.
bits : 25 - 25 (1 bit)
access : read-write

PENDSTSET : Set A pending SysTick Reads back with current state (1 if Pending, 0 if not).
bits : 26 - 26 (1 bit)
access : read-write

PENDSVCLR : Clear A Pending PendSV Interrupt Write 1 to clear a pending PendSV interrupt.
bits : 27 - 27 (1 bit)
access : read-write

PENDSVSET : Set A Pending PendSV Interrupt This is normally used to request a context switch. Reads back with current state (1 if Pending, 0 if not).
bits : 28 - 28 (1 bit)
access : read-write

NMIPENDSET : NMI Pending Set Control Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered. Reads back with current state (1 if Pending, 0 if not).
bits : 31 - 31 (1 bit)
access : read-write

VECTCLRACTIVE : Clear All Active Vector Clears all active state information for fixed and configurable exceptions. The effect of writing a 1 to this bit if the processor is not halted in Debug, is UNPREDICTABLE.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYSRESETREQ : System Reset Request Writing 1 to this bit asserts a signal to request a reset by the external system.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ENDIANESS : Endianess Read Only. Reads 0 indicating little endian machine.
bits : 15 - 15 (1 bit)
access : read-write

VECTKEY : Vector Key The value 0x05FA must be written to this register, otherwise a write to register is UNPREDICTABLE.
bits : 16 - 31 (16 bit)
access : read-write

SLEEPONEXIT : Sleep On Exception When set to 1, the core can enter a sleep state on an exception return to Thread mode. This is the mode and exception level entered at reset, the base level of execution. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.
bits : 1 - 1 (1 bit)
access : read-write

SLEEPDEEP : Sleep Deep Control Controls whether the processor uses sleep or deep sleep as its low power mode: The SLEEPDEEP flag is also used in conjunction with PWRCON register to enter deeper power-down states than purely core sleep states.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SEVONPEND : Send Event On Pending Bit When enabled, interrupt transitions from Inactive to Pending are included in the list of wakeup events for the WFE instruction. When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRI_11 : Priority Of System Handler 11 - SVCall 0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write

PRI_14 : Priority Of System Handler 14 - PendSV 0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write

PRI_15 : Priority Of System Handler 15 - SysTick 0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write