PWRCON

CLKSEL0

CLKSEL1

CLKDIV

CLKSEL2

CLKSLEEP

PFLAGCON

DBGPD

AHBCLK

APBCLK

DPDSTATE

XTAL32K_EN : External 32.768 kHz Crystal Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OSC49M_EN : OSC49M Oscillator Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OSC16K_EN : OSC16K Oscillator Enable Bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STOP : Stop Reserved - do not set to '1'
bits : 9 - 9 (1 bit)
access : read-write

STANDBY_PD : Standby Power Down (SPD) Bit Set to '1' and issue WFI/WFE instruction to enter SPD mode.
bits : 10 - 10 (1 bit)
access : read-write

DEEP_PD : Deep Power Down (DPD) Bit Set to '1' and issue WFI/WFE instruction to enter DPD mode.
bits : 11 - 11 (1 bit)
access : read-write

PIN_ENB : Wakeup Pin Enabled Control Determines whether WAKEUP pin is enabled in DPD mode.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OSC16K_ENB : OSC16K Enabled Control Determines whether OSC16K is enabled in DPD mode. If OSC16K is disabled, device cannot wake from DPD with TIMER_SEL delay.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIMER_SEL : Select Wakeup Timer TIMER_SEL[0] = 1: WAKEUP after 128 OSC16K clocks (12.8 ms) TIMER_SEL[1] = 1: WAKEUP after 256 OSC16K clocks (25.6 ms) TIMER_SEL[2] = 1: WAKEUP after 512 OSC16K clocks (51.2 ms) TIMER_SEL[3] = 1: WAKEUP after 1024 OSC16K clocks (102.4ms)
bits : 20 - 23 (4 bit)
access : read-write

PIN_WAKE : Pin Wakeup Flag Read Only. This flag indicates that wakeup of device was requested with a high to low transition of the WAKEUP pin. Flag is cleared when DPD mode is entered.
bits : 24 - 24 (1 bit)
access : read-write

TIMER_WAKE : Timer Wakeup Flag Read Only. This flag indicates that wakeup of device was requested with TIMER count of the 16Khz oscillator. Flag is cleared when DPD mode is entered.
bits : 25 - 25 (1 bit)
access : read-write

POI_WAKE : POI Wakeup Flag Read Only. This flag indicates that wakeup of device was requested with a power-on reset. Flag is cleared when DPD mode is entered.
bits : 26 - 26 (1 bit)
access : read-write

TIMER_SEL_RD : Current Wakeup Timer Setting Read-Only. Read back of the current WAKEUP timer setting. This value is updated with TIMER_SEL upon entering DPD mode.
bits : 28 - 31 (4 bit)
access : read-write

HCLK_S : HCLK Clock Source Select Ensure that related clock sources (pre-select and new-select) are enabled before updating register. These bits are protected, to write to bits first perform the unlock sequence (see Protected Register Lock Key Register (REGLOCK)) 000 = clock source from internal OSC48M oscillator. 001 = clock source from external 32kHz crystal clock 010 = clock source from internal 16 kHz oscillator clock Others = reserved
bits : 0 - 2 (3 bit)
access : read-write

STCLK_S : MCU Cortex_M0 SysTick Clock Source Select These bits are protected, to write to bits first perform the unlock sequence (see Protected Register Lock Key Register (REGLOCK)) 000 = clock source from 16 kHz internal clock 001 = clock source from external 32kHz crystal clock 010 = clock source from 16 kHz internal oscillator divided by 2 011 = clock source from OSC49M internal oscillator divided by 2 1xx = clock source from HCLK / 2 (Default) Note that to use STCLK_S as source of SysTic timer the CLKSRC bit of SysTick->CTRL must be set to 0.
bits : 3 - 5 (3 bit)
access : read-write

OSCFSel : OSC48M Frequency Select Determines which trim setting to use for OSC48M internal oscillator. Oscillator is factory trimmed within 1% to:
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDG_S : WDG CLK Clock Source Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DPWM_S : Differential Speaker Driver PWM Clock Source Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0_S : TIMER0 Clock Source Select 000 = clock source from internal 16 kHz oscillator 001 = clock source from external 32kHz crystal clock 010 = clock source from HCLK 011 = clock source from external pin (GPIOA[14]) 1xx = clock source from internal OSC48M oscillator clock
bits : 8 - 10 (3 bit)
access : read-write

TMR1_S : TIMER1 Clock Source Select 000 = clock source from internal 16 kHz oscillator 001 = clock source from external 32kHz crystal clock 010 = clock source from HCLK 011 = clock source from external pin (GPIOA[15]) 1xx = clock source from internal OSC48M oscillator clock
bits : 12 - 14 (3 bit)
access : read-write

PWM01_S : PWM0 And PWM1 Clock Source Select PWM0 and PWM1 uses the same clock source, and prescaler
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HCLK_N : HCLK Clock Divide Number From HCLK Clock Source The HCLK clock frequency = (HCLK clock source frequency) / (HCLK_N + 1)
bits : 0 - 3 (4 bit)
access : read-write

UART_N : UART Clock Divide Number From UART Clock Source The UART clock frequency = (UART clock source frequency ) / (UART_N + 1)
bits : 8 - 11 (4 bit)
access : read-write

ADC_N : ADC Clock Divide Number From ADC Clock Source The ADC clock frequency = (ADC clock source frequency ) / (ADC_N + 1)
bits : 16 - 23 (8 bit)
access : read-write

I2S_S : I2S Clock Source Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPU_EN : CPU Clock Sleep Enable (HCLK) Must be left as '1' for normal operation.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDMA_EN : PDMA Controller Sleep Clock Enable Control
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISP_EN : Flash ISP Controller Sleep Clock Enable Control
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDG_EN : Watchdog Sleep Clock Enable Control
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTC_EN : Real-Time- Sleep Clock APB Interface Clock Control
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0_EN : Timer0 Sleep Clock Enable Control
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1_EN : Timer1 Sleep Clock Enable Control
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C0_EN : I2C0 Sleep Clock Enable Control
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI0_EN : SPI0 Sleep Clock Enable Control
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DPWM_EN : Differential PWM Speaker Driver Sleep Clock Enable Control
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART0_EN : UART0 Sleep Clock Enable Control
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BIQALC_EN : Biquad filter/ALC block Sleep Clock Enable Control
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRC_EN : Cyclic Redundancy Check Sleep Block Clock Enable Control
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM01_EN : PWM Block Sleep Clock Enable Control
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACMP_EN : Analog Comparator Sleep Clock Enable Control
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SBRAM_EN : Standby RAM Sleep Clock Enable Control
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADC_EN : Audio Analog-Digital-Converter (ADC) Sleep Clock Enable Control
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2S_EN : I2S Sleep Clock Enable Control
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ANA_EN : Analog Block Sleep Clock Enable Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DS_FLAG : Deep Sleep Flag This flag is set if core logic was placed in Deep Sleep mode. Write '1' to clear flag.
bits : 0 - 0 (1 bit)
access : read-write

STOP_FLAG : Stop Flag This flag is set if core logic was stopped but not powered down. Write '1' to clear flag.
bits : 1 - 1 (1 bit)
access : read-write

PD_FLAG : Powered Down Flag This flag is set if core logic was powered down to Standby (SPD). Write '1' to clear flag.
bits : 2 - 2 (1 bit)
access : read-write

DISABLE_PD : Disable Power Down
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ICE_CLK : ICE_CLK Pin State Read Only. Current state of ICE_CLK pin.
bits : 6 - 6 (1 bit)
access : read-write

ICE_DAT : ICE_DAT Pin State Read Only. Current state of ICE_DAT pin.
bits : 7 - 7 (1 bit)
access : read-write

CPU_EN : CPU Clock Enable (HCLK) Must be left as '1' for normal operation.
bits : 0 - 0 (1 bit)
access : read-write

PDMA_EN : PDMA Controller Clock Enable Control
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISP_EN : Flash ISP Controller Clock Enable Control
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDG_EN : Watchdog Clock Enable Control
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTC_EN : Real-Time-Clock APB Interface Clock Control
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0_EN : Timer0 Clock Enable Control
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1_EN : Timer1 Clock Enable Control
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C0_EN : I2C0 Clock Enable Control
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI0_EN : SPI0 Clock Enable Control
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DPWM_EN : Differential PWM Speaker Driver Clock Enable Control
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART0_EN : UART0 Clock Enable Control
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BIQALC_EN : Biquad Filter And Automatic Level Control Block Clock Enable Control
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRC_EN : Cyclic Redundancy Check Block Clock Enable Control
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM01_EN : PWM Block Clock Enable Control
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACMP_EN : Analog Comparator Clock Enable Control
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SBRAM_EN : Standby RAM Clock Enable Control
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADC_EN : Audio Analog-Digital-Converter (ADC) Clock Enable Control
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2S_EN : I2S Clock Enable Control
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ANA_EN : Analog Block Clock Enable Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DPD_STATE_WR : DPD State Write To set the DPDSTATE register, write value to this register. Data is latched on next DPD event.
bits : 0 - 7 (8 bit)
access : read-write

DPD_STATE_RD : DPD State Read Back Read back of DPDSTATE register. This register was preserved from last DPD event .
bits : 8 - 15 (8 bit)
access : read-write