\n

RTC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x34 byte (0x0)
mem_usage : registers
protection :

Registers

INIR

CLR

TSSR

DWR

TAR

CAR

LIR

RIER

RIIR

TTR

AER

FCR

TLR


INIR

RTC Initialization Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INIR INIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Active INIR

Active : RTC Active Status (Read only) 0: RTC is in reset state 1: RTC is in normal active state.
bits : 0 - 0 (1 bit)
access : read-only

INIR : RTC Initialization After a power-on reset (POR) RTC block should be initialized by writing 0xA5EB1357 to INIR. This will force a hardware reset then release all logic and counters.
bits : 1 - 31 (31 bit)
access : read-write


CLR

Calendar Load Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLR CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 _1DAY _10DAY _1MON _10MON _1YEAR _10YEAR

_1DAY : 1-Day Calendar Digit (0~9)
bits : 0 - 3 (4 bit)
access : read-write

_10DAY : 10-Day Calendar Digit (0~3)
bits : 4 - 5 (2 bit)
access : read-write

_1MON : 1-Month Calendar Digit (0~9)
bits : 8 - 11 (4 bit)
access : read-write

_10MON : 10-Month Calendar Digit (0~1)
bits : 12 - 12 (1 bit)
access : read-write

_1YEAR : 1-Year Calendar Digit (0~9)
bits : 16 - 19 (4 bit)
access : read-write

_10YEAR : 10-Year Calendar Digit (0~9)
bits : 20 - 23 (4 bit)
access : read-write


TSSR

Time Scale Selection Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TSSR TSSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HR24

HR24 : 24-Hour / 12-Hour Mode Selection Determines whether TLR and TAR are in 24-hour mode or 12-hour mode The range of 24-hour time scale is between 0 and 23. 12-hour time scale: 01(AM01), 02(AM02), 03(AM03), 04(AM04), 05(AM05), 06(AM06) 07(AM07), 08(AM08), 09(AM09), 10(AM10), 11(AM11), 12(AM12) 21(PM01), 22(PM02), 23(PM03), 24(PM04), 25(PM05), 26(PM06) 27(PM07), 28(PM08), 29(PM09), 30(PM10), 31(PM11), 32(PM12)
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

select 12-hour time scale with AM and PM indication

#1 : 1

select 24-hour time scale

End of enumeration elements list.


DWR

Day of the Week Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DWR DWR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DWR

DWR : Day of the Week Register 0 (Sunday), 1 (Monday), 2 (Tuesday), 3 (Wednesday) 4 (Thursday), 5 (Friday), 6 (Saturday)
bits : 0 - 2 (3 bit)
access : read-write


TAR

Time Alarm Register
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAR TAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 _1SEC _10SEC _1MIN _10MIN _1HR _10HR

_1SEC : 1 Sec Time Digit of Alarm Setting (0~9)
bits : 0 - 3 (4 bit)
access : read-write

_10SEC : 10 Sec Time Digit of Alarm Setting (0~5)
bits : 4 - 6 (3 bit)
access : read-write

_1MIN : 1 Min Time Digit of Alarm Setting (0~9)
bits : 8 - 11 (4 bit)
access : read-write

_10MIN : 10 Min Time Digit of Alarm Setting (0~5)
bits : 12 - 14 (3 bit)
access : read-write

_1HR : 1 Hour Time Digit of Alarm Setting (0~9)
bits : 16 - 19 (4 bit)
access : read-write

_10HR : 10 Hour Time Digit of Alarm Setting (0~3)
bits : 20 - 21 (2 bit)
access : read-write


CAR

Calendar Alarm Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAR CAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 _1DAY _10DAY _1MON _10MON _1YEAR _10YEAR

_1DAY : 1-Day Calendar Digit of Alarm Setting (0~9)
bits : 0 - 3 (4 bit)
access : read-write

_10DAY : 10-Day Calendar Digit of Alarm Setting (0~3)
bits : 4 - 5 (2 bit)
access : read-write

_1MON : 1-Month Calendar Digit of Alarm Setting (0~9)
bits : 8 - 11 (4 bit)
access : read-write

_10MON : 10-Month Calendar Digit of Alarm Setting (0~1)
bits : 12 - 12 (1 bit)
access : read-write

_1YEAR : 1-Year Calendar Digit of Alarm Setting (0~9)
bits : 16 - 19 (4 bit)
access : read-write

_10YEAR : 10-Year Calendar Digit of Alarm Setting (0~9)
bits : 20 - 23 (4 bit)
access : read-write


LIR

Leap year Indicator Register
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LIR LIR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LIR

LIR : Leap Year Indication Register (read only)
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Current year is not a leap year

#1 : 1

Current year is leap year

End of enumeration elements list.


RIER

RTC Interrupt Enable Register
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RIER RIER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIER TIER

AIER : Alarm Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

RTC Alarm Interrupt is disabled

#1 : 1

RTC Alarm Interrupt is enabled

End of enumeration elements list.

TIER : Time-Tick Interrupt and Wakeup-by-Tick Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

RTC Time-Tick Interrupt is disabled

#1 : 1

RTC Time-Tick Interrupt is enabled

End of enumeration elements list.


RIIR

RTC Interrupt Indicator Register
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RIIR RIIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AI TI

AI : RTC Alarm Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Indicates no Alarm Interrupt condition

#1 : 1

Indicates RTC Alarm Interrupt generated

End of enumeration elements list.

TI : RTC Time-Tick Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Indicates no Time-Tick Interrupt condition

#1 : 1

Indicates RTC Time-Tick Interrupt generated

End of enumeration elements list.


TTR

RTC Time Tick Register
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TTR TTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TTR TWKE

TTR : Time Tick Register The RTC time tick period for Periodic Time-Tick Interrupt request. Time Tick (second) : 1 / (2^TTR) Note: This register can be read back after the RTC is active.
bits : 0 - 2 (3 bit)
access : read-write

TWKE : RTC Timer Wakeup CPU Function Enable Bit If TWKE is set before CPU is in power-down mode, when a RTC Time-Tick or Alarm Match occurs, CPU will wake up.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable Wakeup CPU function

#1 : 1

Enable the Wakeup function

End of enumeration elements list.


AER

RTC Access Enable Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AER AER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AER ENF

AER : RTC Register Access Enable Password (Write only) 0xA965 = Enable RTC access Others = Disable RTC access
bits : 0 - 15 (16 bit)
access : write-only

ENF : RTC Register Access Enable Flag (Read only) This bit will be set after AER[15:0] register is set to 0xA965, it will clear automatically in 512 RTC clock cycles or AER[15:0] ! = 0xA965. The effect of AER.ENF on access to each register is given Table 572. Table 572 AER.ENF Register Access Effect. Register : ENF = 1 : ENF = 0 INIR : R/W : R/W FCR : R/W : - TLR : R/W : R CLR : R/W : R TSSR : R/W : R/W DWR : R/W : R TAR : R/W : - CAR : R/W : - LIR : R : R RIER : R/W : R/W RIIR : R/W : R/W TTR : R/W : -
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

#0 : 0

RTC register read/write disable

#1 : 1

RTC register read/write enable

End of enumeration elements list.


FCR

RTC Frequency Compensation Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FCR FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRACTION INTEGER

FRACTION : Fractional Part Formula = (fraction part of detected value) x 60 Refer to 5.8.4.4 for the examples.
bits : 0 - 5 (6 bit)
access : read-write

INTEGER : Integer Part Register should contain the value (INT(Factual) - 32761) Ex: Integer part of detected value = 32772, FCR.INTEGER = 32772-32761 = 11 (1011b) The range between 32761 and 32776
bits : 8 - 11 (4 bit)
access : read-write


TLR

Time Load Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TLR TLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 _1SEC _10SEC _1MIN _10MIN _1HR _10HR

_1SEC : 1 Sec Time Digit (0~9)
bits : 0 - 3 (4 bit)
access : read-write

_10SEC : 10 Sec Time Digit (0~5)
bits : 4 - 6 (3 bit)
access : read-write

_1MIN : 1 Min Time Digit (0~9)
bits : 8 - 11 (4 bit)
access : read-write

_10MIN : 10 Min Time Digit (0~5)
bits : 12 - 14 (3 bit)
access : read-write

_1HR : 1 Hour Time Digit (0~9)
bits : 16 - 19 (4 bit)
access : read-write

_10HR : 10 Hour Time Digit (0~3)
bits : 20 - 21 (2 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.