CNTRL

RX0

RX1

TX0

TX1

VARCLK

DMA

DIVIDER

SSR

GO_BUSY : Go and Busy Status NOTE: All registers should be set before writing 1 to this GO_BUSY bit. When a transfer is in progress, writing to any register of the SPI master/slave core has no effect.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RX_NEG : Receive At Negative Edge
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TX_NEG : Transmit At Negative Edge
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TX_BIT_LEN : Transmit Bit Length This field specifies how many bits are transmitted in one transmit/receive. Up to 32 bits can be transmitted. TX_BIT_LEN = 0x01 --- 1 bit TX_BIT_LEN = 0x02 --- 2 bits ---- TX_BIT_LEN = 0x1f --- 31 bits TX_BIT_LEN = 0x00 --- 32 bits
bits : 3 - 7 (5 bit)
access : read-write

TX_NUM : Transmit/Receive Word Numbers This field specifies how many transmit/receive word numbers should be executed in one transfer.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LSB : LSB First
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKP : Clock Polarity
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SLEEP : Suspend Interval (Master Only) These four bits provide configurable suspend interval between two successive transmit/receive transactions in a transfer. The suspend interval is from the last falling clock edge of the current transaction to the first rising clock edge of the successive transaction if CLKP = 0. If CLKP = 1, the interval is from the rising clock edge to the falling clock edge. The default value is 0x0. When TX_NUM = 00b, setting this field has no effect on transfer except as determined by REORDER[0] setting. The suspend interval is determined according to the following equation: (SLEEP[3:0] + 2) * period of SCLK
bits : 12 - 15 (4 bit)
access : read-write

IF : Interrupt Flag NOTE: This bit is cleared by writing 1 to itself.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IE : Interrupt Enable
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SLAVE : Master Slave Mode Control
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BYTE_SLEEP : Insert Sleep Interval Between Bytes This function is only valid for 32bit transfers (TX_BIT_LEN = 0). If set then a pause of (SLEEP+2) SCLK cycles is inserted between each byte transmitted.
bits : 19 - 19 (1 bit)
access : read-write

BYTE_ENDIAN : Byte Endian Reorder Function This function changes the order of bytes sent/received to be least significant physical byte first.
bits : 20 - 20 (1 bit)
access : read-write

FIFO : FIFO Mode
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TWOB : Two Bits Transfer Mode Note that when enabled in master mode, MOSI0 data comes from TX[0] and MOSI1 data from TX[1]. Likewise RX[0] receives bit stream from MISO0 and RX[1] from MISO1. Note that when enabled, the setting of TX_NUM must be programmed as 0x00
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VARCLK_EN : Variable Clock Enable (Master Only) Note that when enabled, the setting of TX_BIT_LEN must be programmed as 0x10 (16 bits mode)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RX_EMPTY : Receive FIFO Empty Status
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RX_FULL : Receive FIFO Full Status
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TX_EMPTY : Transmit FIFO Empty Status
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TX_FULL : Transmit FIFO Full Status
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMA_ASS_BURST : Enable DMA Automatic SS function When enabled, interface will automatically generate a SS signal for an entire PDMA access transaction.
bits : 28 - 28 (1 bit)
access : read-write

RX : Data Receive Register The Data Receive Registers hold the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field in the SPI_CNTRL register. For example, if Tx_BIT_LEN is set to 0x08 and Tx_NUM is set to 0x0, bit Rx0[7:0] holds the received data. NOTE: The Data Receive Registers are read only registers.
bits : 0 - 31 (32 bit)
access : read-only

Tx : Data Transmit Register The Data Transmit Registers hold the data to be transmitted in the next transfer. Valid bits depend on the transmit bit length field in the CNTRL register. For example, if Tx_BIT_LEN is set to 0x08 and the Tx_NUM is set to 0x0, the bit Tx0[7:0] will be transmitted in next transfer. If Tx_BIT_LEN is set to 0x00 and Tx_NUM is set to 0x1, the core will perform two 32-bit transmit/receive successive using the same setting (the order is Tx0[31:0], Tx1[31:0]).
bits : 0 - 31 (32 bit)
access : write-only

VARCLK : Variable Clock Pattern The value in this field is the frequency pattern of the SPI clock. If the bit field of VARCLK is '0', the output frequency of SCLK is given by the value of DIVIDER. If the bit field of VARCLK is '1', the output frequency of SCLK is given by the value of DIVIDER2. Refer to register DIVIDER. Refer to Variable Serial Clock Frequency paragraph for detailed description.
bits : 0 - 31 (32 bit)
access : read-write

Tx_DMA_GO : Transmit DMA Start Set this bit to 1 will start the transmit DMA process. SPI module will issue request to DMA module automatically. If using DMA mode to transfer data, remember not to set GO_BUSY bit of SPI_CNTRL register. The DMA controller inside SPI module will set it automatically whenever necessary.
bits : 0 - 0 (1 bit)
access : read-write

Rx_DMA_GO : Receive DMA Start Set this bit to 1 will start the receive DMA process. SPI module will issue request to DMA module automatically.
bits : 1 - 1 (1 bit)
access : read-write

DIVIDER : Clock Divider Register (master only) The value in this field is the frequency division of the system clock, PCLK, to generate the serial clock on the output SCLK. The desired frequency is obtained according to the following equation: Fsclk = Fpclk / ((DIVIDER+1) * 2) In slave mode, the period of SPI clock driven by a master shall satisfy Fsclk < = (Fpclk / 5) In other words, the maximum frequency of SCLK clock is one fifth of the SPI peripheral clock.
bits : 0 - 15 (16 bit)
access : read-write

DIVIDER2 : Clock Divider 2 Register (master only) The value in this field is the 2nd frequency divider of the system clock, PCLK, to generate the serial clock on the output SCLK. The desired frequency is obtained according to the following equation: Fsclk = Fpclk / ((DIVIDER2+1) * 2)
bits : 16 - 31 (16 bit)
access : read-write

SSR : Slave Select Register (Master only) If ASS bit is cleared, writing 1 to any bit location of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state. If ASS bit is set, writing 1 to any bit location of this field will select appropriate SPISSx0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. (The active level of SPISSx0/1 is specified in SS_LVL). Note: SPISSx0 is always defined as device/slave select input signal in slave mode.
bits : 0 - 1 (2 bit)
access : read-write

SS_LVL : Slave Select Active Level It defines the active level of device/slave select signal (SPISSx0/1).
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ASS : Automatic Slave Select (Master only)
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SS_LTRIG : Slave Select Level Trigger (Slave only)
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LTRIG_FLAG : Level Trigger Flag When the SS_LTRIG bit is set in slave mode, this bit can be read to indicate the received bit number is met the requirement or not. Note: This bit is READ only
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.