Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :
Timer Control and Status Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRESCALE : Pre-scale Counter
Clock input is divided by PRESCALE+1 before it is fed to the counter. If PRESCALE = 0, then there is no scaling.
bits : 0 - 7 (8 bit)
access : read-write
TDR_EN : Data Latch Enable
When TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit up-counter value as the timer is counting.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer Data Register update disable
#1 : 1
Timer Data Register update enable
End of enumeration elements list.
CACT : Timer Active Status Bit (Read only)
This bit indicates the counter status of timer.
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
Timer is not active
#1 : 1
Timer is active
End of enumeration elements list.
CRST : Counter Reset Bit
Set this bit will reset the timer counter, prescale and also force CEN to 0.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset Timer's prescale counter, internal 24-bit up-counter and CEN bit
End of enumeration elements list.
MODE : Timer Operating Mode
bits : 27 - 28 (2 bit)
access : read-write
Enumeration:
0 : 0
The timer is operating in the one-shot mode. The associated interrupt signal is generated once (if IE is enabled) and CEN is automatically cleared by hardware
1 : 1
The timer is operating in the periodic mode. The associated interrupt signal is generated periodically (if IE is enabled)
2 : 2
Reserved
3 : 3
The timer is operating in continuous counting mode. The associated interrupt signal is generated when TDR = TCMPR (if IE is enabled) however, the 24-bit up-counter counts continuously without reset
End of enumeration elements list.
IE : Interrupt Enable Bit
If timer interrupt is enabled, the timer asserts its interrupt signal when the count is equal to TCMPR.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable TIMER Interrupt
#1 : 1
Enable TIMER Interrupt
End of enumeration elements list.
CEN : Counter Enable Bit
Note1: Setting CEN = 1 enables 24-bit counter. It continues count from last value.
Note2: This bit is auto-cleared by hardware in one-shot mode (MODE = 00b) when the timer interrupt is generated (IE = 1b).
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Stops/Suspends counting
#1 : 1
Starts counting
End of enumeration elements list.
Timer Compare Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCMP : Timer Comparison Value
TCMP is a 24-bit comparison register. When the 24-bit up-counter is enabled and its value is equal to TCMP value, a Timer Interrupt is requested if the timer interrupt is enabled with TCSR.IE = 1. The TCMP value defines the timer cycle time.
Time out period = (Period of timer clock input) * (8-bit PRESCALE + 1) * (24-bit TCMP)
NOTE1: Never set TCMP to 0x000 or 0x001. Timer will not function correctly.
NOTE2: Regardless of CEN state, whenever a new value is written to this register, TIMER will restart counting using this new value and abort previous count.
bits : 0 - 24 (25 bit)
access : read-write
Timer Interrupt Status Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIF : Timer Interrupt Flag
This bit indicates the interrupt status of Timer.
TIF bit is set by hardware when the 24-bit counter matches the timer comparison value (TCMP). It is cleared by writing 1.
bits : 0 - 0 (1 bit)
access : read-write
Timer Data Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDR : Timer Data Register
When TCSR.TDR_EN is set to 1, the internal 24-bit timer up-counter value will be latched into TDR. User can read this register for the up-counter value.
bits : 0 - 23 (24 bit)
access : read-write
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