DATA

MCR

MSR

FSR

ISR

TOR

BAUD

IRCR

LINCON

FUNSEL

IER

FCR

LCR

_8_bitReceivedData : Receive FIFO Register Reading this register will return data from the receive data FIFO. By reading this register, the UART will return the 8-bit data received from Rx pin (LSB first).
bits : 0 - 7 (8 bit)
access : read-write

RTS_SET : RTS (Request-To-Send) Signal If IER.AUTO_RTS_EN = 0, this bit controls whether RTS pin is active or not.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LBME : Loopback Mode Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTS_ACT : Request-to-Send (RTS) Active Trigger Level This bit can change the RTS trigger level.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTS_ST : RTS Pin State (read only) This bit is the pin status of RTS.
bits : 13 - 13 (1 bit)
access : read-only

DCTSF : Detect CTS State Change Flag This bit is set whenever CTS input has state change. It will generate Modem interrupt to CPU when IER.MS_IEN = 1 NOTE: This bit is cleared by writing 1 to itself.
bits : 0 - 0 (1 bit)
access : read-write

CTS_ST : CTS Pin Status (read only) This bit is the pin status of CTS.
bits : 4 - 4 (1 bit)
access : read-only

CTS_ACT : Clear-to-Send (CTS) Active Trigger Level This bit can change the CTS trigger level.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RX_OVF_IF : Rx Overflow Error Interrupt Flag If the Rx FIFO (UART0->DATA) is full, and an additional byte is received by the UART, an overflow condition will occur and set this bit to logic 1. It will also generate a BUF_ERR_IF event and interrupt if enabled. NOTE: This bit is cleared by writing 1 to itself.
bits : 0 - 0 (1 bit)
access : read-write

PEF : Parity Error Flag This bit is set to logic 1 whenever the received character does not have a valid parity bit , and is reset whenever the CPU writes 1 to this bit.
bits : 4 - 4 (1 bit)
access : read-write

FEF : Framing Error Flag This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit.
bits : 5 - 5 (1 bit)
access : read-write

BIF : Break Interrupt Flag This bit is set to a logic 1 whenever the receive data input (Rx) is held in the space state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). It is reset whenever the CPU writes 1 to this bit.
bits : 6 - 6 (1 bit)
access : read-write

RX_POINTER : Rx FIFO pointer (Read Only) This field returns the Rx FIFO buffer pointer. It is the number of bytes available for read in the Rx FIFO. When UART receives one byte from external device, RX_POINTER is incremented. When one byte of Rx FIFO is read by CPU, RX_POINTER is decremented.
bits : 8 - 13 (6 bit)
access : read-only

RX_EMPTY : Receive FIFO Empty (Read Only) This bit indicates whether the Rx FIFO is empty or not. When the last byte of Rx FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
bits : 14 - 14 (1 bit)
access : read-only

RX_FULL : Receive FIFO Full (Read Only) This bit indicates whether the Rx FIFO is full or not. This bit is set when Rx FIFO is full otherwise it is cleared by hardware.
bits : 15 - 15 (1 bit)
access : read-only

TX_POINTER : Tx FIFO Pointer (Read Only) This field returns the Tx FIFO buffer pointer. When CPU writes a byte into the Tx FIFO, TX_POINTER is incremented. When a byte from Tx FIFO is transferred to the Transmit Shift Register, TX_POINTER is decremented.
bits : 16 - 21 (6 bit)
access : read-only

TX_EMPTY : Transmit FIFO Empty (Read Only) This bit indicates whether the Tx FIFO is empty or not. When the last byte of Tx FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared after writing data to FIFO (Tx FIFO not empty).
bits : 22 - 22 (1 bit)
access : read-only

TX_FULL : Transmit FIFO Full (Read Only) This bit indicates whether the Tx FIFO is full or not.
bits : 23 - 23 (1 bit)
access : read-only

TX_OVF_IF : Tx Overflow Error Interrupt Flag If the Tx FIFO (UART0->DATA) is full, an additional write to UART0->DATA will cause an overflow condition and set this bit to logic 1. It will also generate a BUF_ERR_IF event and interrupt if enabled. NOTE: This bit is cleared by writing 1 to itself.
bits : 24 - 24 (1 bit)
access : read-write

TE : Transmitter Empty (Read Only) Bit is set by hardware when Tx FIFO is empty and the STOP bit of the last byte has been transmitted. Bit is cleared automatically when Tx FIFO is not empty or the last byte transmission has not completed. NOTE: This bit is read only.
bits : 28 - 28 (1 bit)
access : read-only

RDA_IF : Receive Data Available Interrupt Flag (Read Only) When the number of bytes in the Rx FIFO equals FCR.RFITL then the RDA_IF will be set. If IER.RDA_IEN is enabled, the RDA interrupt will be generated. NOTE: This bit is read only and it will be cleared when the number of unread bytes of Rx FIFO drops below the threshold level (RFITL).
bits : 0 - 0 (1 bit)
access : read-only

THRE_IF : Transmit Holding Register Empty Interrupt Flag (Read Only) This bit is set when the last data of Tx FIFO is transferred to Transmitter Shift Register. If IER.THRE_IEN is enabled, the THRE interrupt will be generated. NOTE: This bit is read only and it will be cleared when writing data into the Tx FIFO.
bits : 1 - 1 (1 bit)
access : read-only

RLS_IF : Receive Line Status Interrupt Flag (Read Only) This bit is set when the Rx receive data has a parity, framing or break error (at least one of, FSR.BIF, FSR.FEF and FSR.PEF, is set). If IER.RLS_IEN is enabled, the RLS interrupt will be generated. NOTE: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
bits : 2 - 2 (1 bit)
access : read-only

MODEM_IF : MODEM Interrupt Flag (Read Only) NOTE: This bit is read only and reset when bit MSR.DCTSF is cleared by a write 1.
bits : 3 - 3 (1 bit)
access : read-only

TOUT_IF : Time Out Interrupt Flag (Read Only) This bit is set when the Rx FIFO is not empty and no activity occurs in the Rx FIFO and the time out counter equal to TOIC. If IER.TOUT_IEN is enabled a CPU interrupt request will be generated. NOTE: This bit is read only and user can read FIFO to clear it.
bits : 4 - 4 (1 bit)
access : read-only

BUF_ERR_IF : Buffer Error Interrupt Flag (Read Only) This bit is set when either the Tx or Rx FIFO overflows (FSR.TX_OVF_IF or FSR.RX_OVF_IF is set). When BUF_ERR_IF is set, the serial transfer may be corrupted. If IER.BUF_ERR_IEN is enabled a CPU interrupt request will be generated. NOTE: This bit is cleared when both FSR.TX_OVF_IF and FSR.RX_OVF_IF are cleared.
bits : 5 - 5 (1 bit)
access : read-only

LIN_Rx_Break_IF : LIN Bus Rx Break Field Detected Flag This bit is set when LIN controller detects a break field. This bit is cleared by writing a 1.
bits : 7 - 7 (1 bit)
access : read-write

RDA_INT : Receive Data Available Interrupt Indicator to Interrupt Controller Logical AND of IER.RDA_IEN and RDA_IF.
bits : 8 - 8 (1 bit)
access : read-write

THRE_INT : Transmit Holding Register Empty Interrupt Indicator to Interrupt Controller Logical AND of IER.THRE_IEN and THRE_IF.
bits : 9 - 9 (1 bit)
access : read-write

RLS_INT : Receive Line Status Interrupt Indicator to Interrupt Controller Logical AND of IER.RLS_IEN and RLS_IF.
bits : 10 - 10 (1 bit)
access : read-write

MODEM_INT : MODEM Status Interrupt Indicator to Interrupt Logical AND of IER.MS_IEN and MODEM_IF.
bits : 11 - 11 (1 bit)
access : read-write

TOUT_INT : Time Out Interrupt Indicator to Interrupt Controller Logical AND of IER.RTO_IEN and TOUT_IF.
bits : 12 - 12 (1 bit)
access : read-write

BUF_ERR_INT : Buffer Error Interrupt Indicator to Interrupt Controller Logical AND of IER.BUF_ERR_IEN and BUF_ERR_IF.
bits : 13 - 13 (1 bit)
access : read-write

LIN_Rx_Break_INT : LIN Bus Rx Break Field Detected Interrupt Indicator to Interrupt Controller Logical AND of IER.LIN_RX_BRK_IEN and LIN_Rx_Break_IF.
bits : 15 - 15 (1 bit)
access : read-write

DMAmodeBits : DMA Mode Bits DMA mode equivalent following interrupt indicators and flags. See Table 5107 and normal mode descriptions below. In DMA mode (either DMA transmit or receive requests are active) these bits are generated rather than the normal use bits below.
bits : 16 - 31 (16 bit)
access : read-write

TOIC : Time Out Interrupt Comparator The time out counter resets and starts counting whenever the Rx FIFO receives a new data word. Once the content of time out counter (TOUT_CNT) is equal to that of time out interrupt comparator (TOIC), a receiver time out interrupt (TOUT_INT) is generated if IER.RTO_IEN is set. A new incoming data word or RX FIFO empty clears TOUT_IF. The period of the time out counter is the baud rate.
bits : 0 - 6 (7 bit)
access : read-write

BRD : Baud Rate Divider Refer to Table 5111 for more information.
bits : 0 - 15 (16 bit)
access : read-write

DIVX : Divider X The baud rate divider M = DIVX+1.
bits : 24 - 27 (4 bit)
access : read-write

DIVX_ONE : Divider X equal 1 0: M = DIVX+1, with restriction DIVX ≥ 8. 1: M = 1, with restriction BRD[15:0] ≥ 3. Refer to Table 5111 for more information.
bits : 28 - 28 (1 bit)
access : read-write

DIVX_EN : Divider X Enable The baud rate equation is: Baud Rate = UART_CLK / [ M * (BRD + 2) ] The default value of M is 16. Refer to Table 5111 for more information. NOTE: When in IrDA mode, this bit must disabled.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TX_SELECT : Transmit/Receive Selection
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LOOPBACK : IrDA Loopback Test Mode Loopback Tx to Rx.
bits : 2 - 2 (1 bit)
access : read-write

TX_INV_EN : Transmit inversion enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RX_INV_EN : Receive Inversion Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LINBCNT : UART LIN Break Field Length Count This field indicates a 4-bit LIN Tx break field count. NOTE: This break field length is LINBCNT + 2
bits : 0 - 3 (4 bit)
access : read-write

LIN_RX_EN : LIN RX Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LIN_TX_EN : LIN TX Break Mode Enable NOTE: When Tx break field transfer operation finished, this bit will be cleared automatically.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LIN_EN : Enable LIN Function Note that IrDA and LIN functions are mutually exclusive: both cannot be active at same time.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IrDA_EN : Enable IrDA Function
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RDA_IEN : Receive Data Available Interrupt Enable.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

THRE_IEN : Transmit FIFO Register Empty Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RLS_IEN : Receive Line Status Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MS_IEN : Modem Status Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTO_IEN : Receive Time out Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUF_ERR_IEN : Buffer Error Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LIN_RX_BRK_IEN : LIN RX Break Field Detected Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TOC_EN : Time-Out Counter Enable
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AUTO_RTS_EN : RTS Auto Flow Control Enable When RTS auto-flow is enabled, if the number of bytes in the Rx FIFO equals FCR.RTS_TRIG_LEVEL, the UART will de-assert the RTS signal.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AUTO_CTS_EN : CTS Auto Flow Control Enable When CTS auto-flow is enabled, the UART will send data to external device when CTS input is asserted (UART will not send data to device until CTS is asserted).
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMA_TX_EN : Transmit DMA Enable If enabled, the UART will request DMA service when space is available in transmit FIFO.
bits : 14 - 14 (1 bit)
access : read-write

DMA_RX_EN : Receive DMA Enable If enabled, the UART will request DMA service when data is available in receive FIFO.
bits : 15 - 15 (1 bit)
access : read-write

RFR : Receive FIFO Reset When RFR is set, all the bytes in the receive FIFO are cleared and receive internal state machine is reset. Note: This bit will auto-clear after 3 UART engine clock cycles.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TFR : Transmit FIFO Reset When TFR is set, all the bytes in the transmit FIFO are cleared and transmit internal state machine is reset. Note: This bit will auto-clear after 3 UART engine clock cycles.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RFITL : Receive FIFO Interrupt (RDA_INT) Trigger Level When the number of bytes in the receive FIFO equals the RFITL then the RDA_IF will be set and, if enabled, an RDA_INT interrupt will generated. Value : INTR_RDA Trigger Level (Bytes) 0 : 1 1 : 4 2 : 8
bits : 4 - 7 (4 bit)
access : read-write

RTS_TRIG_LEVEL : RTS Trigger Level for Auto-flow Control Sets the FIFO trigger level when auto-flow control will de-assert RTS (request-to-send). Value : Trigger Level (Bytes) 0 : 1 1 : 4 2 : 8
bits : 16 - 19 (4 bit)
access : read-write

WLS : Word Length Select 0 (5bits), 1(6bits), 2(7bits), 3(8bits)
bits : 0 - 1 (2 bit)
access : read-write

NSB : Number of STOP bits
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PBE : Parity Bit Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EPE : Even Parity Enable This bit has effect only when PBE (parity bit enable) is set.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPE : Stick Parity Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BCB : Break Control Bit When this bit is set to logic 1, the serial data output (Tx) is forced to the 'Space' state (logic 0). Normal condition is serial data output is 'Mark' state. This bit acts only on Tx and has no effect on the transmitter logic.
bits : 6 - 6 (1 bit)
access : read-write