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CRC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :

Registers

CRC_EN (EN)

CRC_IN (IN)

CRC_OUT (OUT)


CRC_EN (EN)

CRC Enable Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRC_EN CRC_EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEN LSB

LEN : CRC Packet Length Indicates number of bytes of CRC input to process. CRC calculation will stop once input number of bytes = LEN+1. Maximum packet size is 512 bytes, for LEN = 511. Writing any value to this register will flush all previous calculations and restart a new CRC calculation.
bits : 0 - 8 (9 bit)
access : read-write

LSB : CRC LSB mode Determines whether CRC Generator processes input words (32bit/4Bytes) LSB (least significant byte) first or MSB (most significant byte) first. For example if LSB = 1, and 0x01020304 is written to CRC_IN, bytes will be processed in order 0x04, 0x03, 0x02, 0x01. If LSB = 0, then order would be 0x01, 0x02, 0x3, 0x04. Writing any value to this register will flush all previous calculations and restart a new CRC calculation.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

CRC input is MSB first (default)

#1 : 1

CRC input is LSB first

End of enumeration elements list.


CRC_IN (IN)

CRC Input Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRC_IN CRC_IN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRC_IN

CRC_IN : CRC Input The string of bytes to perform CRC calculation on. When LSB = 0, CRC performs calculation byte by byte in the order CRC_IN[31:24], CRC_IN[23:16], CRC_IN[15:8], CRC_IN[7:0]. When LSB = 1, CRC performs calculation byte by byte in the order CRC_IN[7:0], CRC_IN[15:8], CRC_IN[23:16], CRC_IN[31:24]. If number of input bytes exceeds CRC Packet Length (CRC_EN[8:0]+1), any additional input bytes will be ignored. The CRC generator takes four clock cycles to process the CRC input. Software must ensure that at least four clock cycles occur between writes of CRC_IN. Compiled assembly language can be examined to ensure this requirement is met.
bits : 0 - 31 (32 bit)
access : read-write


CRC_OUT (OUT)

CRC Output Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CRC_OUT CRC_OUT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRC_OUT

CRC_OUT : CRC Output The result of CRC computation. The result is valid four clock cycles after last CRC_IN input data is written to CRC generator.
bits : 0 - 15 (16 bit)
access : read-only



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