ADCOUT

INT

ADCPDMA

ADCMPR0

ADCMPR1

EN

CLK_DIV

DEC

ADCOUT : ADC Audio Data FIFO Read A read of this register will read data from the audio FIFO and increment the read pointer. A read past empty will repeat the last data. Can be used with FIFO_IE_LEV interrupt to determine if valid data is present in FIFO.
bits : 0 - 15 (16 bit)
access : read-only

FIFO_IE_LEV : FIFO Interrupt Level Determines at what level the ADC FIFO will generate a servicing interrupt to the CPU. Interrupt will be generated when number of words present in ADC FIFO is > FIFO_IE_LEV.
bits : 0 - 2 (3 bit)
access : read-write

IE : Interrupt Enable If set to '1' an interrupt is generated whenever FIFO level exceeds that set in FIFO_IE_LEV.
bits : 31 - 31 (1 bit)
access : read-write

RxDmaEn : Enable ADC PDMA Receive Channel Enable ADC PDMA. If set, then ADC will request PDMA service when data is available.
bits : 0 - 0 (1 bit)
access : read-write

CMPEN : Compare Enable Set this bit to 1 to enable compare CMPD with FIFO data output.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPIE : Compare Interrupt Enable If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPF bit will be asserted, if CMPIE is set to 1, a compare interrupt request is generated.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPCOND : Compare Condition Note: When the internal counter reaches the value (CMPMATCNT +1), the CMPF bit will be set.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPF : Compare Flag When the conversion result meets condition in ADCMPR0 this bit is set to 1. It is cleared by writing 1 to self.
bits : 7 - 7 (1 bit)
access : read-write

CMPMATCNT : Compare Match Count When the A/D FIFO result matches the compare condition defined by CMPCOND, the internal match counter will increase by 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set.
bits : 8 - 11 (4 bit)
access : read-write

CMPD : Comparison Data 16 bit value to compare to FIFO output word.
bits : 16 - 31 (16 bit)
access : read-write

CMPEN : Compare Enable Set this bit to 1 to enable compare CMPD with FIFO data output.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPIE : Compare Interrupt Enable If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPF bit will be asserted, if CMPIE is set to 1, a compare interrupt request is generated.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPCOND : Compare Condition Note: When the internal counter reaches the value (CMPMATCNT +1), the CMPF bit will be set.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPF : Compare Flag When the conversion result meets condition in ADCMPR0 this bit is set to 1. It is cleared by writing 1 to self.
bits : 7 - 7 (1 bit)
access : read-write

CMPMATCNT : Compare Match Count When the A/D FIFO result matches the compare condition defined by CMPCOND, the internal match counter will increase by 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set.
bits : 8 - 11 (4 bit)
access : read-write

CMPD : Comparison Data 16 bit value to compare to FIFO output word.
bits : 16 - 31 (16 bit)
access : read-write

EN : ADC Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLK_DIV : ADC Clock Divider This register determines the clock division ration between the incoming ADC_CLK (= HCLK by default) and the Delta-Sigma sampling clock of the ADC. This together with the over-sampling ratio (OSR) determines the audio sample rate of the converter. CLK_DIV should be set to give a SD_CLK frequency in the range of 1.024-6.144MHz. CLK_DIV must be greater than 2. SD_CLK frequency = HCLK / CLK_DIV
bits : 0 - 7 (8 bit)
access : read-write

OSR : Decimation Over-Sampling Ratio This term determines the over-sampling ratio of the decimation filter. Valid values are: 0: OSR = 64 1: OSR = 128 2: OSR = 192 3: OSR = 384
bits : 0 - 3 (4 bit)
access : read-write

GAIN : CIC Filter Additional Gain This should normally remain default 0. Can be set to non-zero values to provide additional digital gain from the decimation filter. An additional gain is applied to signal of GAIN/2.
bits : 16 - 19 (4 bit)
access : read-write