Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection :
DPWM Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Freq : DPWM Modulation Frequency
This parameter controls the carrier modulation frequency of the PWM signal as a proportion of DPWM_CLK.
Freq : DPWM_CLK Division : Frequency for DPWM_CLK = 98.304MHZ
0 : 228 : 431158
1 : 156 : 630154
2 : 76 : 1293474
3 : 52 : 1890462
4 : 780 : 126031
5 : 524 : 187603
6 : 396 : 248242
7 : 268 : 366806
bits : 0 - 2 (3 bit)
access : read-write
Deadtime : DPWM Driver Deadtime Control
Enabling this bit will insert an additional clock cycle deadtime into the switching of PMOS and NMOS driver transistors.
bits : 3 - 3 (1 bit)
access : read-write
Dither : DPWM Signal Dither Control
To prevent structured noise on PWM output due to DC offsets in the input signal it is possible to add random dither to the PWM signal. These bits control the dither:
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : 0
No dither
1 : 1
+/- 1 bit dither
3 : 3
+/- 2 bit dither
End of enumeration elements list.
Enable : DPWM Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable DPWM, SPK pins are tri-state, CIC filter is reset, FIFO pointers are reset (FIFO data is not reset)
#1 : 1
Enable DPWM, SPK pins are enabled and driven, data is taken from FIFO
End of enumeration elements list.
DPWM Zero Order Hold Division Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZOH_DIV : DPWM Zero Order Hold, Down-Sampling Divisor
The input sample rate of the DPWM is set by HCLK frequency and the divisor set in this register by the following formula:
Fs = HCLK/ZOH_DIV/64
Valid range is 1 to 255. Default is 48, which gives a sample rate of 16kHz for a 49.152MHz (default) HCLK.
bits : 0 - 7 (8 bit)
access : read-write
DPWM FIFO Status Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FULL : FIFO Full
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
FIFO is not full
#1 : 1
FIFO is full
End of enumeration elements list.
EMPTY : FIFO Empty
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
FIFO is not empty
#1 : 1
FIFO is empty
End of enumeration elements list.
DPWM PDMA Control Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EnablePDMA : Enable DPWM DMA Interface
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable PDMA. No requests will be made to PDMA controller
#1 : 1
Enable PDMA. Block will request data from PDMA controller whenever FIFO is not empty
End of enumeration elements list.
DPWM FIFO Input
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FIFO : DPWM FIFO Audio Data Input
A write to this register pushes data onto the DPWM FIFO and increments the write pointer. This is the address that PDMA writes audio data to.
bits : 0 - 15 (16 bit)
access : write-only
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