\n

ACMP

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :

Registers

CMPCR0

CMPCR1

CMPSR

CMPSEL


CMPCR0

Analog Comparator 0 Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPCR0 CMPCR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPEN CMPIE CMPCN

CMPEN : Comparator Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

CMPIE : CMP0 Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable CMP0 interrupt function

#1 : 1

Enable CMP0 interrupt function

End of enumeration elements list.

CMPCN : Comparator0 Negative Input Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

VBG, Bandgap reference voltage = 1.2V

#1 : 1

VMID reference voltage = VCCA/2

End of enumeration elements list.


CMPCR1

Analog Comparator 1 Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPCR1 CMPCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPEN CMPIE CMPCN

CMPEN : Comparator Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

CMPIE : CMP1 Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable CMP1interrupt function

#1 : 1

Enable CMP1 interrupt function

End of enumeration elements list.

CMPCN : Comparator1 Negative Input Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOB[7]

#1 : 1

VBG, Bandgap reference voltage = 1.2V

End of enumeration elements list.


CMPSR

Comparator Status Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPSR CMPSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPF0 CMPF1 CO0 CO1

CMPF0 : Compare 0 Flag This bit is set by hardware whenever the comparator output changes state. This bit will cause a hardware interrupt if enabled. This bit is cleared by writing 1 to itself.
bits : 0 - 0 (1 bit)
access : read-write

CMPF1 : Compare 1 Flag This bit is set by hardware whenever the comparator output changes state. This bit will cause a hardware interrupt if enabled. This bit is cleared by writing 1 to itself.
bits : 1 - 1 (1 bit)
access : read-write

CO0 : Comparator0 Output Synchronized to the APB clock to allow reading by software. Cleared when the comparator is disabled (CMP0EN = 0).
bits : 2 - 2 (1 bit)
access : read-write

CO1 : Comparator1 Output Synchronized to the APB clock to allow reading by software. Cleared when the comparator is disabled (CMP1EN = 0).
bits : 3 - 3 (1 bit)
access : read-write


CMPSEL

Comparator Select Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPSEL CMPSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPSEL

CMPSEL : Comparator0 GPIO Selection GPIOB[CMPSEL] is the active analog GPIO input selected to Comparator 0 positive input.
bits : 0 - 2 (3 bit)
access : read-write



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