VMID

LDOSET

LDOPD

MICBSEL

MICBEN

VSET

TMPOWER

TMANALOG

AMUX

PGAEN

SIGCTRL

PGAGAIN

ISRC

TRIM

CAPS_CTRL

CAPS_CNT

FREQ_CTRL

FREQ_CNT

PULLDOWN : VMID Pulldown
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDLORES : Power Down Low (4.8kΩ) Resistance Reference
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDHIRES : Power Down High (360kΩ) Resistance Reference
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LDOSET : Select LDO Output Voltage Note that maximum I/O pad operation speed only specified for voltage >2.4V.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PD : Power Down LDO When powered down no current delivered to VD33.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DISCH : Discharge
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SEL : Select Microphone Bias Voltage MICBMODE = 0 0: 90% VCCA 1: 65% VCCA 2: 75% VCCA 3: 50% VCCA MICBMODE = 1 0: 2.4V 1: 1.7V 2: 2.0V 3: 1.3V
bits : 0 - 1 (2 bit)
access : read-write

REF : Select Reference Source For MICBIAS Generator VMID provides superior noise performance for MICBIAS generation and should be used unless fixed voltage is absolutely necessary, then noise performance can be sacrificed and bandgap voltage used as reference.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MICBEN : Enable Microphone Bias Generator
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MUXN_SEL : Selects Connection Of GPIOB[7:0] To PGA_INN, Negative Input Of PGA If MUXN_SEL[n] = 1 then GPIOB[n] is connected to PGA_INN.
bits : 0 - 7 (8 bit)
access : read-write

MUXP_SEL : Selects Connection Of GPIOB[7,5,3,1] To PGA_INP, Positive Input Of PGA 1000b: GPIOB[7] connected to PGA_INP 0100b: GPIOB[5] connected to PGA_INP 0010b: GPIOB[3] connected to PGA_INP 0001b: GPIOB[1] connected to PGA_INP
bits : 8 - 11 (4 bit)
access : read-write

TEMP_SEL : Select PTAT Current I_PTAT, to PGA_INN, negative input to PGA, for temperature measurement.
bits : 12 - 12 (1 bit)
access : read-write

MIC_SEL : Select MICP/MICN To PGA Inputs
bits : 13 - 13 (1 bit)
access : read-write

EN : Enable The Analog Multiplexer
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REF_SEL : Select Reference For Analog Path Signal path is normally referenced to VMID (VCCA/2). To use an absolute reference this can be set to VBG = 1.2V.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_PGA : Power Up Control For PGA Amplifier This amplifier must be powered up for signal path operation.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_BOOST : Power Up Control For Boost Stage Amplifier This amplifier must be powered up for signal path operation.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOOSTGAIN : Boost Stage Gain Setting
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_ZCD : Power Up And Enable Control For Zero Cross Detect Comparator When enabled PGA gain settings will only be updated when ADC input signal crosses zero signal threshold. To operate ZCD the ALC peripheral clock (SYSCLK.BIQALC_EN) must also be enabled and BIQ->BIQ_CTRL.RSTn = 1 to allow ZCD clocks to be generated.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_BUFPGA : Power Up Control For PGA Reference Buffer This block must be powered up for signal path operation.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_BUFADC : Power Up Control For ADC Reference Buffer This block must be powered up for signal path operation.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_IBGEN : Power Up Control For Current Bias Generation This block must be powered up for signal path operation.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_MOD : Power Up ADC ΣΔ Modulator This block must be powered up for ADC operation.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MUTE_PGA : PGA Mute Control
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MUTE_IPBOOST : Boost Stage Mute Control
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GAIN : Select The PGA Gain Setting From -12dB to 35.25dB in 0.75dB step size. 0x00 is lowest gain setting at -12dB and 0x3F is largest gain at 35.25dB.
bits : 0 - 5 (6 bit)
access : read-write

GAIN_READ : Current PGA Gain Read Only. May be different from GAIN register when AGC is enabled and is controlling the PGA gain.
bits : 8 - 13 (6 bit)
access : read-write

EN : Enable Current Source to GPIOB[x] Individually enable current source to GPIOB pins. Each GPIOB pin has a separate current source.
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VAL : Current Source Value Select master current for source generation
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OSCTRIM : Oscillator Trim Reads current oscillator trim setting. Read Only.
bits : 0 - 7 (8 bit)
access : read-write

COARSE : COARSE Current COARSE range setting of the oscillator. Read Only
bits : 8 - 15 (8 bit)
access : read-write

SUPERFINE : Superfine The SUPERFINE trim setting is an 8bit signed integer. It adjusts the master oscillator by dithering the FINE trim setting between the current setting and one setting above (values 1,127) or below (values -1, -128) the current trim setting. Each step effectively moves the frequency 1/128th of the full FINE trim step size.
bits : 16 - 23 (8 bit)
access : read-write

LOW_TIME : Output Low Time Number of PCLK cycles to discharge external capacitor.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CYCLE_CNT : Number of Relaxation Cycles Peripheral performs 2^(CYCLE_CNT) relaxation cycles before generating interrupt.
bits : 2 - 4 (3 bit)
access : read-write

REF_CLK_MD : Reference Clock Mode
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLK_DIV : Reference Clock Divider Circuit can be used to generate a reference clock output of SDCLK/2/(CLK_DIV+1) instead of a Capacitive Touch Sensing reset signal.
bits : 8 - 15 (8 bit)
access : read-write

RST_CNT : Reset Count 0: Release/Activate CAP_CNT 1: Set high to reset CAP_CNT.
bits : 29 - 29 (1 bit)
access : read-write

INT_EN : Interrupt Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EN : Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPS_CNT : Counter Read Back Value Of Capacitive Touch Sensing Block
bits : 0 - 23 (24 bit)
access : read-only

FM_SEL : Reference Clock Source 00b: OSC16K, 01b: OSC32K (default), 1xb: I2S_WS - can be GPIOA[4,8,12] according to GPA_ALT register, configure I2S in SLAVE mode to enable.
bits : 0 - 1 (2 bit)
access : read-write

FM_DONE : Measurement Done
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FM_CYCLE : Frequency Measurement Cycles Number of reference clock periods plus one to measure target clock (PCLK). For example if reference clock is OSC32K (T is 30.5175us), set FM_CYCLE to 7, then measurement period would be 30.5175*(7+1), 244.1us.
bits : 16 - 23 (8 bit)
access : read-write

GO : GO
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FREQ_CNT : Frequency Measurement Count When FM_DONE = 1 and G0 = 1, this is number of PCLK periods counted for frequency measurement. The frequency will be PCLK = FREQ_CNT * Fref /(FM_CYCLE+1) Hz Maximum resolution of measurement is Fref /(FM_CYCLE+1)*2 Hz
bits : 0 - 15 (16 bit)
access : read-only