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address_offset : 0x0 Bytes (0x0)
size : 0x308 byte (0x0)
mem_usage : registers
protection :
FIFO Access Port
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFO : FIFO access port.
bits : 0 - 31 (32 bit)
access : read-write
Current FIFO Pointers
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFOSIZ : The number of bytes currently in the FIFO.
bits : 0 - 7 (8 bit)
access : read-write
FIFOREM : The number of bytes remaining in the FIFO (i.e. 128-FIFOSIZ if FULLDUP = 0 or 64-FIFOSIZ if FULLDUP = 1)).
bits : 16 - 39 (24 bit)
access : read-write
Transfer Length
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TLNGTH : Remaining transfer length.
bits : 0 - 11 (12 bit)
access : read-write
FIFO Threshold Configuration
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFORTHR : FIFO read threshold.
bits : 0 - 6 (7 bit)
access : read-write
FIFOWTHR : FIFO write threshold.
bits : 8 - 22 (15 bit)
access : read-write
I/O Clock Configuration
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSEL : Select the input clock frequency.
bits : 8 - 18 (11 bit)
access : read-write
Enumeration:
0 : MIN_PWR
Selects the minimum power clock. This setting should be used whenever the IOMSTR is not active.
1 : HFRC
Selects the HFRC as the input clock.
2 : HFRC_DIV2
Selects the HFRC / 2 as the input clock.
3 : HFRC_DIV4
Selects the HFRC / 4 as the input clock.
4 : HFRC_DIV8
Selects the HFRC / 8 as the input clock.
5 : HFRC_DIV16
Selects the HFRC / 16 as the input clock.
6 : HFRC_DIV32
Selects the HFRC / 32 as the input clock.
7 : HFRC_DIV64
Selects the HFRC / 64 as the input clock.
End of enumeration elements list.
DIV3 : Enable divide by 3.
bits : 11 - 22 (12 bit)
access : read-write
Enumeration:
0 : DIS
Select divide by 1.
1 : EN
Select divide by 3.
End of enumeration elements list.
DIVEN : Enable clock division by TOTPER.
bits : 12 - 24 (13 bit)
access : read-write
Enumeration:
0 : DIS
Disable TOTPER division.
1 : EN
Enable TOTPER division.
End of enumeration elements list.
LOWPER : Clock low count minus 1.
bits : 16 - 39 (24 bit)
access : read-write
TOTPER : Clock total count minus 1.
bits : 24 - 55 (32 bit)
access : read-write
Command Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : This register holds the I/O Command
bits : 0 - 31 (32 bit)
access : read-write
Command Repeat Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDRPT : These bits hold the Command repeat count.
bits : 0 - 4 (5 bit)
access : read-write
Status Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERR : This bit indicates if an error interrupt has occurred.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : ERROR
An error has been indicated by the IOM.
End of enumeration elements list.
CMDACT : This bit indicates if the I/O Command is active.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : ACTIVE
An I/O command is active.
End of enumeration elements list.
IDLEST : This bit indicates if the I/O state machine is IDLE.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
1 : IDLE
The I/O state machine is in the idle state.
End of enumeration elements list.
I/O Master Configuration
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IFCSEL : This bit selects the I/O interface.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : I2C
Selects I2C interface for the I/O Master.
1 : SPI
Selects SPI interface for the I/O Master.
End of enumeration elements list.
SPOL : This bit selects SPI polarity.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : CLK_BASE_0
The base value of the clock is 0.
1 : CLK_BASE_1
The base value of the clock is 1.
End of enumeration elements list.
SPHA : This bit selects SPI phase.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : SAMPLE_LEADING_EDGE
Sample on the leading (first) clock edge.
1 : SAMPLE_TRAILING_EDGE
Sample on the trailing (second) clock edge.
End of enumeration elements list.
FULLDUP : This bit selects full duplex mode.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : NORMAL
128 byte FIFO in half duplex mode.
1 : FULLDUP
64 byte FIFO in full duplex mode.
End of enumeration elements list.
STARTRD : This bit selects the preread timing.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : PRERD0
0 read delay cycles.
1 : PRERD1
1 read delay cycles.
2 : PRERD2
2 read delay cycles.
3 : PRERD3
3 read delay cycles.
End of enumeration elements list.
WTFC : This bit enables write mode flow control.
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : DIS
Write mode flow control disabled.
1 : EN
Write mode flow control enabled.
End of enumeration elements list.
RDFC : This bit enables read mode flow control.
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : DIS
Read mode flow control disabled.
1 : EN
Read mode flow control enabled.
End of enumeration elements list.
MOSIINV : This bit invewrts MOSI when flow control is enabled.
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
0 : NORMAL
MOSI is set to 0 in read mode and 1 in write mode.
1 : INVERT
MOSI is set to 1 in read mode and 0 in write mode.
End of enumeration elements list.
FCDEL : This bit must be left at the default value of 0.
bits : 11 - 22 (12 bit)
access : read-write
WTFCIRQ : This bit selects the write mode flow control signal.
bits : 12 - 24 (13 bit)
access : read-write
Enumeration:
0 : MISO
MISO is used as the write mode flow control signal.
1 : IRQ
IRQ is used as the write mode flow control signal.
End of enumeration elements list.
WTFCPOL : This bit selects the write flow control signal polarity.
bits : 13 - 26 (14 bit)
access : read-write
Enumeration:
0 : HIGH
Flow control signal high creates flow control.
1 : LOW
Flow control signal low creates flow control.
End of enumeration elements list.
RDFCPOL : This bit selects the read flow control signal polarity.
bits : 14 - 28 (15 bit)
access : read-write
Enumeration:
0 : HIGH
Flow control signal high creates flow control.
1 : LOW
Flow control signal low creates flow control.
End of enumeration elements list.
IFCEN : This bit enables the IO Master.
bits : 31 - 62 (32 bit)
access : read-write
Enumeration:
0 : DIS
Disable the IO Master.
1 : EN
Enable the IO Master.
End of enumeration elements list.
IO Master Interrupts: Enable
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDCMP : This is the Command Complete interrupt.
bits : 0 - 0 (1 bit)
access : read-write
THR : This is the FIFO Threshold interrupt.
bits : 1 - 2 (2 bit)
access : read-write
FUNDFL : This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO when empty (i.e. while FIFOSIZ less than 4).
bits : 2 - 4 (3 bit)
access : read-write
FOVFL : This is the Write FIFO Overflow interrupt. An attempt was made to write the FIFO while it was full (i.e. while FIFOSIZ > 124).
bits : 3 - 6 (4 bit)
access : read-write
NAK : This is the I2C NAK interrupt. The expected ACK from the slave was not received by the IOM.
bits : 4 - 8 (5 bit)
access : read-write
WTLEN : This is the WTLEN interrupt.
bits : 5 - 10 (6 bit)
access : read-write
IACC : This is the illegal FIFO access interrupt. An attempt was made to read the FIFO during a write CMD. Or an attempt was made to write the FIFO on a read CMD.
bits : 6 - 12 (7 bit)
access : read-write
ICMD : This is the illegal command interrupt. Software attempted to issue a CMD while another CMD was already in progress. Or an attempt was made to issue a non-zero-length write CMD with an empty FIFO.
bits : 7 - 14 (8 bit)
access : read-write
START : This is the START command interrupt. A START from another master was detected. Software must wait for a STOP before proceeding.
bits : 8 - 16 (9 bit)
access : read-write
STOP : This is the STOP command interrupt. A STOP bit was detected by the IOM.
bits : 9 - 18 (10 bit)
access : read-write
ARB : This is the arbitration loss interrupt. This error occurs if another master collides with an IO Master transfer. Generally, the IOM started an operation but found SDA already low.
bits : 10 - 20 (11 bit)
access : read-write
IO Master Interrupts: Status
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDCMP : This is the Command Complete interrupt.
bits : 0 - 0 (1 bit)
access : read-write
THR : This is the FIFO Threshold interrupt.
bits : 1 - 2 (2 bit)
access : read-write
FUNDFL : This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO when empty (i.e. while FIFOSIZ less than 4).
bits : 2 - 4 (3 bit)
access : read-write
FOVFL : This is the Write FIFO Overflow interrupt. An attempt was made to write the FIFO while it was full (i.e. while FIFOSIZ > 124).
bits : 3 - 6 (4 bit)
access : read-write
NAK : This is the I2C NAK interrupt. The expected ACK from the slave was not received by the IOM.
bits : 4 - 8 (5 bit)
access : read-write
WTLEN : This is the WTLEN interrupt.
bits : 5 - 10 (6 bit)
access : read-write
IACC : This is the illegal FIFO access interrupt. An attempt was made to read the FIFO during a write CMD. Or an attempt was made to write the FIFO on a read CMD.
bits : 6 - 12 (7 bit)
access : read-write
ICMD : This is the illegal command interrupt. Software attempted to issue a CMD while another CMD was already in progress. Or an attempt was made to issue a non-zero-length write CMD with an empty FIFO.
bits : 7 - 14 (8 bit)
access : read-write
START : This is the START command interrupt. A START from another master was detected. Software must wait for a STOP before proceeding.
bits : 8 - 16 (9 bit)
access : read-write
STOP : This is the STOP command interrupt. A STOP bit was detected by the IOM.
bits : 9 - 18 (10 bit)
access : read-write
ARB : This is the arbitration loss interrupt. This error occurs if another master collides with an IO Master transfer. Generally, the IOM started an operation but found SDA already low.
bits : 10 - 20 (11 bit)
access : read-write
IO Master Interrupts: Clear
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDCMP : This is the Command Complete interrupt.
bits : 0 - 0 (1 bit)
access : read-write
THR : This is the FIFO Threshold interrupt.
bits : 1 - 2 (2 bit)
access : read-write
FUNDFL : This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO when empty (i.e. while FIFOSIZ less than 4).
bits : 2 - 4 (3 bit)
access : read-write
FOVFL : This is the Write FIFO Overflow interrupt. An attempt was made to write the FIFO while it was full (i.e. while FIFOSIZ > 124).
bits : 3 - 6 (4 bit)
access : read-write
NAK : This is the I2C NAK interrupt. The expected ACK from the slave was not received by the IOM.
bits : 4 - 8 (5 bit)
access : read-write
WTLEN : This is the WTLEN interrupt.
bits : 5 - 10 (6 bit)
access : read-write
IACC : This is the illegal FIFO access interrupt. An attempt was made to read the FIFO during a write CMD. Or an attempt was made to write the FIFO on a read CMD.
bits : 6 - 12 (7 bit)
access : read-write
ICMD : This is the illegal command interrupt. Software attempted to issue a CMD while another CMD was already in progress. Or an attempt was made to issue a non-zero-length write CMD with an empty FIFO.
bits : 7 - 14 (8 bit)
access : read-write
START : This is the START command interrupt. A START from another master was detected. Software must wait for a STOP before proceeding.
bits : 8 - 16 (9 bit)
access : read-write
STOP : This is the STOP command interrupt. A STOP bit was detected by the IOM.
bits : 9 - 18 (10 bit)
access : read-write
ARB : This is the arbitration loss interrupt. This error occurs if another master collides with an IO Master transfer. Generally, the IOM started an operation but found SDA already low.
bits : 10 - 20 (11 bit)
access : read-write
IO Master Interrupts: Set
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDCMP : This is the Command Complete interrupt.
bits : 0 - 0 (1 bit)
access : read-write
THR : This is the FIFO Threshold interrupt.
bits : 1 - 2 (2 bit)
access : read-write
FUNDFL : This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO when empty (i.e. while FIFOSIZ less than 4).
bits : 2 - 4 (3 bit)
access : read-write
FOVFL : This is the Write FIFO Overflow interrupt. An attempt was made to write the FIFO while it was full (i.e. while FIFOSIZ > 124).
bits : 3 - 6 (4 bit)
access : read-write
NAK : This is the I2C NAK interrupt. The expected ACK from the slave was not received by the IOM.
bits : 4 - 8 (5 bit)
access : read-write
WTLEN : This is the WTLEN interrupt.
bits : 5 - 10 (6 bit)
access : read-write
IACC : This is the illegal FIFO access interrupt. An attempt was made to read the FIFO during a write CMD. Or an attempt was made to write the FIFO on a read CMD.
bits : 6 - 12 (7 bit)
access : read-write
ICMD : This is the illegal command interrupt. Software attempted to issue a CMD while another CMD was already in progress. Or an attempt was made to issue a non-zero-length write CMD with an empty FIFO.
bits : 7 - 14 (8 bit)
access : read-write
START : This is the START command interrupt. A START from another master was detected. Software must wait for a STOP before proceeding.
bits : 8 - 16 (9 bit)
access : read-write
STOP : This is the STOP command interrupt. A STOP bit was detected by the IOM.
bits : 9 - 18 (10 bit)
access : read-write
ARB : This is the arbitration loss interrupt. This error occurs if another master collides with an IO Master transfer. Generally, the IOM started an operation but found SDA already low.
bits : 10 - 20 (11 bit)
access : read-write
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