SOC_IDENTITY

SYS_CONFIG0

SYS_CONFIG1

IIDR

PIDR4

PIDR0

PIDR1

PIDR2

PIDR3

CIDR0

CIDR1

CIDR2

CIDR3

SOC_IMPLEMENTATOR : JEP106 code of the company that implemented the SoC
bits : 0 - 11 (12 bit)

SOC_REVISION : IMPL_DEF value used to distinguish minor revisions of the SoC.
bits : 12 - 27 (16 bit)

SOC_VARIANT : IMPL_DEF value variant or major revision of the SoC.
bits : 16 - 35 (20 bit)

SOC_PRODUCT_ID : IMPL_DEF value identifying the SoC.
bits : 20 - 51 (32 bit)

NUM_VM_BANK : Number of Volatile Memory Banks.
bits : 0 - 3 (4 bit)

VM_ADDR_WIDTH : Volatile Memory Bank Address Width, where the size of each bank is equal to 2VM_ADDR_WIDTH bytes.
bits : 4 - 12 (9 bit)

HAS_CRYPTO : CryptoCell Included.
bits : 9 - 18 (10 bit)

Enumeration:

End of enumeration elements list.

HAS_CSS : Include CoreSight SoC-600 based Debug infrastructure.
bits : 10 - 20 (11 bit)

Enumeration:

End of enumeration elements list.

PI_LEVEL : Power Infrastructure Level
bits : 11 - 23 (13 bit)

Enumeration:

End of enumeration elements list.

CPU0_TYPE : CPU 0 Core Type
bits : 16 - 34 (19 bit)

Enumeration:

End of enumeration elements list.

CPU0_HAS_SYSTCM : CPU 0 has System TCM. Note that this is not the CPU's local ITCM or DTCM, but instead are TCMs implemented at system level.
bits : 19 - 38 (20 bit)

Enumeration:

End of enumeration elements list.

CPU0_TCM_BANK_NUM : The VM Bank that is the TCM memory for CPU 0.
bits : 20 - 43 (24 bit)

CPU1_TYPE : CPU 1 Core Type
bits : 24 - 50 (27 bit)

Enumeration:

End of enumeration elements list.

CPU1_HAS_SYSTCM : CPU 1 has System TCM. Note that this is not the CPU's local ITCM or DTCM, but instead are TCMs implemented at system level.
bits : 27 - 54 (28 bit)

Enumeration:

End of enumeration elements list.

CPU1_TCM_BANK_NUM : The VM Bank that is the TCM memory for CPU 1.
bits : 28 - 59 (32 bit)

CPU2_TYPE : CPU 2 Core Type.
bits : 0 - 2 (3 bit)

Enumeration:

End of enumeration elements list.

CPU2_HAS_SYSTCM : CPU 2 has System TCM. Note that this is not the CPU's local ITCM or DTCM, but instead are TCMs implemented at system level.
bits : 3 - 6 (4 bit)

Enumeration:

End of enumeration elements list.

CPU2_TCM_BANK_NUM : The VM Bank that is the TCM memory for CPU 2.
bits : 4 - 11 (8 bit)

CPU3_TYPE : CPU 3 Core Type.
bits : 8 - 18 (11 bit)

Enumeration:

End of enumeration elements list.

CPU3_HAS_SYSTCM : CPU 3 has System TCM. Note that this is not the CPU's local ITCM or DTCM, but instead are TCMs implemented at system level.
bits : 11 - 22 (12 bit)

Enumeration:

End of enumeration elements list.

CPU3_TCM_BANK_NUM : The VM Bank that is the TCM memory for CPU 3.
bits : 12 - 27 (16 bit)

IMP_IMPLEMENTATOR : Contains the JEP106 code of the company that implemented the subsystem implementation.
bits : 0 - 11 (12 bit)

IMP_REVISION : IMPL_DEF value used to distinguish minor revisions of the subsystem implementation.
bits : 12 - 27 (16 bit)

IMP_VARIANT : IMPL_DEF value variant or major revision of the subsystem implementation.
bits : 16 - 35 (20 bit)

IMP_PRODUCT_ID : IMPL_DEF value identifying the subsystem implementation.
bits : 20 - 51 (32 bit)