\n
address_offset : 0x0 Bytes (0x0)
size : 0xEC byte (0x0)
mem_usage : registers
protection :
address_offset : 0x0 Bytes (0x0)
size : 0xEC byte (0x0)
mem_usage : registers
protection :
address_offset : 0x0 Bytes (0x0)
size : 0xEC byte (0x0)
mem_usage : registers
protection :
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXEN : Receive Enable
bits : 0 - 0 (1 bit)
RXDIS : Receive Disable
bits : 1 - 1 (1 bit)
TXEN : Transmit Enable
bits : 8 - 8 (1 bit)
TXDIS : Transmit Disable
bits : 9 - 9 (1 bit)
SWRST : Software Reset
bits : 15 - 15 (1 bit)
Receive Clock Mode Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKS : Receive Clock Selection
bits : 0 - 1 (2 bit)
Enumeration: CKSSelect
0x0 : MCK
Divided Clock
0x1 : TK
TK Clock signal
0x2 : RK
RK pin
End of enumeration elements list.
CKO : Receive Clock Output Mode Selection
bits : 2 - 4 (3 bit)
Enumeration: CKOSelect
0x0 : NONE
None, RK pin is an input
0x1 : CONTINUOUS
Continuous Receive Clock, RK pin is an output
0x2 : TRANSFER
Receive Clock only during data transfers, RK pin is an output
End of enumeration elements list.
CKI : Receive Clock Inversion
bits : 5 - 5 (1 bit)
CKG : Receive Clock Gating Selection
bits : 6 - 7 (2 bit)
Enumeration: CKGSelect
0x0 : CONTINUOUS
None
0x1 : EN_RF_LOW
Receive Clock enabled only if RF Low
0x2 : EN_RF_HIGH
Receive Clock enabled only if RF High
End of enumeration elements list.
START : Receive Start Selection
bits : 8 - 11 (4 bit)
Enumeration: STARTSelect
0x0 : CONTINUOUS
Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
0x1 : TRANSMIT
Transmit start
0x2 : RF_LOW
Detection of a low level on RF signal
0x3 : RF_HIGH
Detection of a high level on RF signal
0x4 : RF_FALLING
Detection of a falling edge on RF signal
0x5 : RF_RISING
Detection of a rising edge on RF signal
0x6 : RF_LEVEL
Detection of any level change on RF signal
0x7 : RF_EDGE
Detection of any edge on RF signal
0x8 : CMP_0
Compare 0
End of enumeration elements list.
STOP : Receive Stop Selection
bits : 12 - 12 (1 bit)
STTDLY : Receive Start Delay
bits : 16 - 23 (8 bit)
PERIOD : Receive Period Divider Selection
bits : 24 - 31 (8 bit)
Receive Frame Mode Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATLEN : Data Length
bits : 0 - 4 (5 bit)
LOOP : Loop Mode
bits : 5 - 5 (1 bit)
MSBF : Most Significant Bit First
bits : 7 - 7 (1 bit)
DATNB : Data Number per Frame
bits : 8 - 11 (4 bit)
FSLEN : Receive Frame Sync Length
bits : 16 - 19 (4 bit)
FSOS : Receive Frame Sync Output Selection
bits : 20 - 22 (3 bit)
Enumeration: FSOSSelect
0x0 : NONE
None, RF pin is an input
0x1 : NEGATIVE
Negative Pulse, RF pin is an output
0x2 : POSITIVE
Positive Pulse, RF pin is an output
0x3 : LOW
Driven Low during data transfer, RF pin is an output
0x4 : HIGH
Driven High during data transfer, RF pin is an output
0x5 : TOGGLING
Toggling at each start of data transfer, RF pin is an output
End of enumeration elements list.
FSEDGE : Frame Sync Edge Detection
bits : 24 - 24 (1 bit)
Enumeration: FSEDGESelect
0 : POSITIVE
Positive Edge Detection
1 : NEGATIVE
Negative Edge Detection
End of enumeration elements list.
FSLEN_EXT : FSLEN Field Extension
bits : 28 - 31 (4 bit)
Transmit Clock Mode Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKS : Transmit Clock Selection
bits : 0 - 1 (2 bit)
Enumeration: CKSSelect
0x0 : MCK
Divided Clock
0x1 : RK
RK Clock signal
0x2 : TK
TK pin
End of enumeration elements list.
CKO : Transmit Clock Output Mode Selection
bits : 2 - 4 (3 bit)
Enumeration: CKOSelect
0x0 : NONE
None, TK pin is an input
0x1 : CONTINUOUS
Continuous Transmit Clock, TK pin is an output
0x2 : TRANSFER
Transmit Clock only during data transfers, TK pin is an output
End of enumeration elements list.
CKI : Transmit Clock Inversion
bits : 5 - 5 (1 bit)
CKG : Transmit Clock Gating Selection
bits : 6 - 7 (2 bit)
Enumeration: CKGSelect
0x0 : CONTINUOUS
None
0x1 : EN_TF_LOW
Transmit Clock enabled only if TF Low
0x2 : EN_TF_HIGH
Transmit Clock enabled only if TF High
End of enumeration elements list.
START : Transmit Start Selection
bits : 8 - 11 (4 bit)
Enumeration: STARTSelect
0x0 : CONTINUOUS
Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data
0x1 : RECEIVE
Receive start
0x2 : TF_LOW
Detection of a low level on TF signal
0x3 : TF_HIGH
Detection of a high level on TF signal
0x4 : TF_FALLING
Detection of a falling edge on TF signal
0x5 : TF_RISING
Detection of a rising edge on TF signal
0x6 : TF_LEVEL
Detection of any level change on TF signal
0x7 : TF_EDGE
Detection of any edge on TF signal
End of enumeration elements list.
STTDLY : Transmit Start Delay
bits : 16 - 23 (8 bit)
PERIOD : Transmit Period Divider Selection
bits : 24 - 31 (8 bit)
Transmit Frame Mode Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATLEN : Data Length
bits : 0 - 4 (5 bit)
DATDEF : Data Default Value
bits : 5 - 5 (1 bit)
MSBF : Most Significant Bit First
bits : 7 - 7 (1 bit)
DATNB : Data Number per Frame
bits : 8 - 11 (4 bit)
FSLEN : Transmit Frame Sync Length
bits : 16 - 19 (4 bit)
FSOS : Transmit Frame Sync Output Selection
bits : 20 - 22 (3 bit)
Enumeration: FSOSSelect
0x0 : NONE
None, TF pin is an input
0x1 : NEGATIVE
Negative Pulse, TF pin is an output
0x2 : POSITIVE
Positive Pulse, TF pin is an output
0x3 : LOW
Driven Low during data transfer
0x4 : HIGH
Driven High during data transfer
0x5 : TOGGLING
Toggling at each start of data transfer
End of enumeration elements list.
FSDEN : Frame Sync Data Enable
bits : 23 - 23 (1 bit)
FSEDGE : Frame Sync Edge Detection
bits : 24 - 24 (1 bit)
Enumeration: FSEDGESelect
0 : POSITIVE
Positive Edge Detection
1 : NEGATIVE
Negative Edge Detection
End of enumeration elements list.
FSLEN_EXT : FSLEN Field Extension
bits : 28 - 31 (4 bit)
Receive Holding Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDAT : Receive Data
bits : 0 - 31 (32 bit)
Transmit Holding Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TDAT : Transmit Data
bits : 0 - 31 (32 bit)
Receive Sync. Holding Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RSDAT : Receive Synchronization Data
bits : 0 - 15 (16 bit)
Transmit Sync. Holding Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSDAT : Transmit Synchronization Data
bits : 0 - 15 (16 bit)
Receive Compare 0 Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CP0 : Receive Compare Data 0
bits : 0 - 15 (16 bit)
Receive Compare 1 Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CP1 : Receive Compare Data 1
bits : 0 - 15 (16 bit)
Clock Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Clock Divider
bits : 0 - 11 (12 bit)
Status Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXRDY : Transmit Ready
bits : 0 - 0 (1 bit)
TXEMPTY : Transmit Empty
bits : 1 - 1 (1 bit)
RXRDY : Receive Ready
bits : 4 - 4 (1 bit)
OVRUN : Receive Overrun
bits : 5 - 5 (1 bit)
CP0 : Compare 0
bits : 8 - 8 (1 bit)
CP1 : Compare 1
bits : 9 - 9 (1 bit)
TXSYN : Transmit Sync
bits : 10 - 10 (1 bit)
RXSYN : Receive Sync
bits : 11 - 11 (1 bit)
TXEN : Transmit Enable
bits : 16 - 16 (1 bit)
RXEN : Receive Enable
bits : 17 - 17 (1 bit)
Interrupt Enable Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXRDY : Transmit Ready Interrupt Enable
bits : 0 - 0 (1 bit)
TXEMPTY : Transmit Empty Interrupt Enable
bits : 1 - 1 (1 bit)
RXRDY : Receive Ready Interrupt Enable
bits : 4 - 4 (1 bit)
OVRUN : Receive Overrun Interrupt Enable
bits : 5 - 5 (1 bit)
CP0 : Compare 0 Interrupt Enable
bits : 8 - 8 (1 bit)
CP1 : Compare 1 Interrupt Enable
bits : 9 - 9 (1 bit)
TXSYN : Tx Sync Interrupt Enable
bits : 10 - 10 (1 bit)
RXSYN : Rx Sync Interrupt Enable
bits : 11 - 11 (1 bit)
Interrupt Disable Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXRDY : Transmit Ready Interrupt Disable
bits : 0 - 0 (1 bit)
TXEMPTY : Transmit Empty Interrupt Disable
bits : 1 - 1 (1 bit)
RXRDY : Receive Ready Interrupt Disable
bits : 4 - 4 (1 bit)
OVRUN : Receive Overrun Interrupt Disable
bits : 5 - 5 (1 bit)
CP0 : Compare 0 Interrupt Disable
bits : 8 - 8 (1 bit)
CP1 : Compare 1 Interrupt Disable
bits : 9 - 9 (1 bit)
TXSYN : Tx Sync Interrupt Enable
bits : 10 - 10 (1 bit)
RXSYN : Rx Sync Interrupt Enable
bits : 11 - 11 (1 bit)
Interrupt Mask Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXRDY : Transmit Ready Interrupt Mask
bits : 0 - 0 (1 bit)
TXEMPTY : Transmit Empty Interrupt Mask
bits : 1 - 1 (1 bit)
RXRDY : Receive Ready Interrupt Mask
bits : 4 - 4 (1 bit)
OVRUN : Receive Overrun Interrupt Mask
bits : 5 - 5 (1 bit)
CP0 : Compare 0 Interrupt Mask
bits : 8 - 8 (1 bit)
CP1 : Compare 1 Interrupt Mask
bits : 9 - 9 (1 bit)
TXSYN : Tx Sync Interrupt Mask
bits : 10 - 10 (1 bit)
RXSYN : Rx Sync Interrupt Mask
bits : 11 - 11 (1 bit)
Write Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)
Enumeration: WPKEYSelect
0x535343 : PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
End of enumeration elements list.
Write Protection Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WPVS : Write Protection Violation Status
bits : 0 - 0 (1 bit)
WPVSRC : Write Protect Violation Source
bits : 8 - 23 (16 bit)
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