Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x810 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x0 Bytes (0x0)
size : 0x810 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x0 Bytes (0x0)
size : 0x810 byte (0x0)
mem_usage : registers
protection :
Device General Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UADD : USB Address
bits : 0 - 6 (7 bit)
ADDEN : Address Enable
bits : 7 - 7 (1 bit)
DETACH : Detach
bits : 8 - 8 (1 bit)
RMWKUP : Remote Wake-Up
bits : 9 - 9 (1 bit)
SPDCONF : Mode Configuration
bits : 10 - 11 (2 bit)
Enumeration: SPDCONFSelect
0 : NORMAL
The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable.
1 : LOW_POWER
For a better consumption, if high speed is not needed.
End of enumeration elements list.
LS : Low-Speed Mode Force
bits : 12 - 12 (1 bit)
TSTJ : Test mode J
bits : 13 - 13 (1 bit)
TSTK : Test mode K
bits : 14 - 14 (1 bit)
TSTPCKT : Test packet mode
bits : 15 - 15 (1 bit)
OPMODE2 : Specific Operational mode
bits : 16 - 16 (1 bit)
Device DMA Channel Next Descriptor Address Register (n = 1)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
Host DMA Channel Next Descriptor Address Register (n = 1)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
Device Global Interrupt Mask Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUSPE : Suspend Interrupt Mask
bits : 0 - 0 (1 bit)
MSOFE : Micro Start of Frame Interrupt Mask
bits : 1 - 1 (1 bit)
SOFE : Start of Frame Interrupt Mask
bits : 2 - 2 (1 bit)
EORSTE : End of Reset Interrupt Mask
bits : 3 - 3 (1 bit)
WAKEUPE : Wake-Up Interrupt Mask
bits : 4 - 4 (1 bit)
EORSME : End of Resume Interrupt Mask
bits : 5 - 5 (1 bit)
UPRSME : Upstream Resume Interrupt Mask
bits : 6 - 6 (1 bit)
PEP_0 : Endpoint 0 Interrupt Mask
bits : 12 - 12 (1 bit)
PEP_1 : Endpoint 1 Interrupt Mask
bits : 13 - 13 (1 bit)
PEP_2 : Endpoint 2 Interrupt Mask
bits : 14 - 14 (1 bit)
PEP_3 : Endpoint 3 Interrupt Mask
bits : 15 - 15 (1 bit)
PEP_4 : Endpoint 4 Interrupt Mask
bits : 16 - 16 (1 bit)
PEP_5 : Endpoint 5 Interrupt Mask
bits : 17 - 17 (1 bit)
PEP_6 : Endpoint 6 Interrupt Mask
bits : 18 - 18 (1 bit)
PEP_7 : Endpoint 7 Interrupt Mask
bits : 19 - 19 (1 bit)
PEP_8 : Endpoint 8 Interrupt Mask
bits : 20 - 20 (1 bit)
PEP_9 : Endpoint 9 Interrupt Mask
bits : 21 - 21 (1 bit)
PEP_10 : Endpoint 10 Interrupt Mask
bits : 22 - 22 (1 bit)
PEP_11 : Endpoint 11 Interrupt Mask
bits : 23 - 23 (1 bit)
DMA_1 : DMA Channel 1 Interrupt Mask
bits : 25 - 25 (1 bit)
DMA_2 : DMA Channel 2 Interrupt Mask
bits : 26 - 26 (1 bit)
DMA_3 : DMA Channel 3 Interrupt Mask
bits : 27 - 27 (1 bit)
DMA_4 : DMA Channel 4 Interrupt Mask
bits : 28 - 28 (1 bit)
DMA_5 : DMA Channel 5 Interrupt Mask
bits : 29 - 29 (1 bit)
DMA_6 : DMA Channel 6 Interrupt Mask
bits : 30 - 30 (1 bit)
DMA_7 : DMA Channel 7 Interrupt Mask
bits : 31 - 31 (1 bit)
Device Endpoint Configuration Register (n = 0) 0
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALLOC : Endpoint Memory Allocate
bits : 1 - 1 (1 bit)
EPBK : Endpoint Banks
bits : 2 - 3 (2 bit)
Enumeration: EPBKSelect
0x0 : _1_BANK
Single-bank endpoint
0x1 : _2_BANK
Double-bank endpoint
0x2 : _3_BANK
Triple-bank endpoint
End of enumeration elements list.
EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
Enumeration: EPSIZESelect
0x0 : _8_BYTE
8 bytes
0x1 : _16_BYTE
16 bytes
0x2 : _32_BYTE
32 bytes
0x3 : _64_BYTE
64 bytes
0x4 : _128_BYTE
128 bytes
0x5 : _256_BYTE
256 bytes
0x6 : _512_BYTE
512 bytes
0x7 : _1024_BYTE
1024 bytes
End of enumeration elements list.
EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
Enumeration: EPDIRSelect
0 : OUT
The endpoint direction is OUT.
1 : IN
The endpoint direction is IN (nor for control endpoints).
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 9 - 9 (1 bit)
EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
Enumeration: EPTYPESelect
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
NBTRANS : Number of transactions per microframe for isochronous endpoint
bits : 13 - 14 (2 bit)
Enumeration: NBTRANSSelect
0x0 : _0_TRANS
Reserved to endpoint that does not have the high-bandwidth isochronous capability.
0x1 : _1_TRANS
Default value: one transaction per microframe.
0x2 : _2_TRANS
Two transactions per microframe. This endpoint should be configured as double-bank.
0x3 : _3_TRANS
Three transactions per microframe. This endpoint should be configured as triple-bank.
End of enumeration elements list.
Device Endpoint Configuration Register (n = 0) 0
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALLOC : Endpoint Memory Allocate
bits : 1 - 1 (1 bit)
EPBK : Endpoint Banks
bits : 2 - 3 (2 bit)
Enumeration: EPBKSelect
0x0 : _1_BANK
Single-bank endpoint
0x1 : _2_BANK
Double-bank endpoint
0x2 : _3_BANK
Triple-bank endpoint
End of enumeration elements list.
EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
Enumeration: EPSIZESelect
0x0 : _8_BYTE
8 bytes
0x1 : _16_BYTE
16 bytes
0x2 : _32_BYTE
32 bytes
0x3 : _64_BYTE
64 bytes
0x4 : _128_BYTE
128 bytes
0x5 : _256_BYTE
256 bytes
0x6 : _512_BYTE
512 bytes
0x7 : _1024_BYTE
1024 bytes
End of enumeration elements list.
EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
Enumeration: EPDIRSelect
0 : OUT
The endpoint direction is OUT.
1 : IN
The endpoint direction is IN (nor for control endpoints).
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 9 - 9 (1 bit)
EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
Enumeration: EPTYPESelect
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
NBTRANS : Number of transactions per microframe for isochronous endpoint
bits : 13 - 14 (2 bit)
Enumeration: NBTRANSSelect
0x0 : _0_TRANS
Reserved to endpoint that does not have the high-bandwidth isochronous capability.
0x1 : _1_TRANS
Default value: one transaction per microframe.
0x2 : _2_TRANS
Two transactions per microframe. This endpoint should be configured as double-bank.
0x3 : _3_TRANS
Three transactions per microframe. This endpoint should be configured as triple-bank.
End of enumeration elements list.
Device Endpoint Configuration Register (n = 0) 0
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALLOC : Endpoint Memory Allocate
bits : 1 - 1 (1 bit)
EPBK : Endpoint Banks
bits : 2 - 3 (2 bit)
Enumeration: EPBKSelect
0x0 : _1_BANK
Single-bank endpoint
0x1 : _2_BANK
Double-bank endpoint
0x2 : _3_BANK
Triple-bank endpoint
End of enumeration elements list.
EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
Enumeration: EPSIZESelect
0x0 : _8_BYTE
8 bytes
0x1 : _16_BYTE
16 bytes
0x2 : _32_BYTE
32 bytes
0x3 : _64_BYTE
64 bytes
0x4 : _128_BYTE
128 bytes
0x5 : _256_BYTE
256 bytes
0x6 : _512_BYTE
512 bytes
0x7 : _1024_BYTE
1024 bytes
End of enumeration elements list.
EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
Enumeration: EPDIRSelect
0 : OUT
The endpoint direction is OUT.
1 : IN
The endpoint direction is IN (nor for control endpoints).
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 9 - 9 (1 bit)
EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
Enumeration: EPTYPESelect
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
NBTRANS : Number of transactions per microframe for isochronous endpoint
bits : 13 - 14 (2 bit)
Enumeration: NBTRANSSelect
0x0 : _0_TRANS
Reserved to endpoint that does not have the high-bandwidth isochronous capability.
0x1 : _1_TRANS
Default value: one transaction per microframe.
0x2 : _2_TRANS
Two transactions per microframe. This endpoint should be configured as double-bank.
0x3 : _3_TRANS
Three transactions per microframe. This endpoint should be configured as triple-bank.
End of enumeration elements list.
Device Endpoint Configuration Register (n = 0) 0
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALLOC : Endpoint Memory Allocate
bits : 1 - 1 (1 bit)
EPBK : Endpoint Banks
bits : 2 - 3 (2 bit)
Enumeration: EPBKSelect
0x0 : _1_BANK
Single-bank endpoint
0x1 : _2_BANK
Double-bank endpoint
0x2 : _3_BANK
Triple-bank endpoint
End of enumeration elements list.
EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
Enumeration: EPSIZESelect
0x0 : _8_BYTE
8 bytes
0x1 : _16_BYTE
16 bytes
0x2 : _32_BYTE
32 bytes
0x3 : _64_BYTE
64 bytes
0x4 : _128_BYTE
128 bytes
0x5 : _256_BYTE
256 bytes
0x6 : _512_BYTE
512 bytes
0x7 : _1024_BYTE
1024 bytes
End of enumeration elements list.
EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
Enumeration: EPDIRSelect
0 : OUT
The endpoint direction is OUT.
1 : IN
The endpoint direction is IN (nor for control endpoints).
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 9 - 9 (1 bit)
EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
Enumeration: EPTYPESelect
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
NBTRANS : Number of transactions per microframe for isochronous endpoint
bits : 13 - 14 (2 bit)
Enumeration: NBTRANSSelect
0x0 : _0_TRANS
Reserved to endpoint that does not have the high-bandwidth isochronous capability.
0x1 : _1_TRANS
Default value: one transaction per microframe.
0x2 : _2_TRANS
Two transactions per microframe. This endpoint should be configured as double-bank.
0x3 : _3_TRANS
Three transactions per microframe. This endpoint should be configured as triple-bank.
End of enumeration elements list.
Device Endpoint Configuration Register (n = 0) 0
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALLOC : Endpoint Memory Allocate
bits : 1 - 1 (1 bit)
EPBK : Endpoint Banks
bits : 2 - 3 (2 bit)
Enumeration: EPBKSelect
0x0 : _1_BANK
Single-bank endpoint
0x1 : _2_BANK
Double-bank endpoint
0x2 : _3_BANK
Triple-bank endpoint
End of enumeration elements list.
EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
Enumeration: EPSIZESelect
0x0 : _8_BYTE
8 bytes
0x1 : _16_BYTE
16 bytes
0x2 : _32_BYTE
32 bytes
0x3 : _64_BYTE
64 bytes
0x4 : _128_BYTE
128 bytes
0x5 : _256_BYTE
256 bytes
0x6 : _512_BYTE
512 bytes
0x7 : _1024_BYTE
1024 bytes
End of enumeration elements list.
EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
Enumeration: EPDIRSelect
0 : OUT
The endpoint direction is OUT.
1 : IN
The endpoint direction is IN (nor for control endpoints).
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 9 - 9 (1 bit)
EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
Enumeration: EPTYPESelect
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
NBTRANS : Number of transactions per microframe for isochronous endpoint
bits : 13 - 14 (2 bit)
Enumeration: NBTRANSSelect
0x0 : _0_TRANS
Reserved to endpoint that does not have the high-bandwidth isochronous capability.
0x1 : _1_TRANS
Default value: one transaction per microframe.
0x2 : _2_TRANS
Two transactions per microframe. This endpoint should be configured as double-bank.
0x3 : _3_TRANS
Three transactions per microframe. This endpoint should be configured as triple-bank.
End of enumeration elements list.
Device Endpoint Configuration Register (n = 0) 0
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALLOC : Endpoint Memory Allocate
bits : 1 - 1 (1 bit)
EPBK : Endpoint Banks
bits : 2 - 3 (2 bit)
Enumeration: EPBKSelect
0x0 : _1_BANK
Single-bank endpoint
0x1 : _2_BANK
Double-bank endpoint
0x2 : _3_BANK
Triple-bank endpoint
End of enumeration elements list.
EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
Enumeration: EPSIZESelect
0x0 : _8_BYTE
8 bytes
0x1 : _16_BYTE
16 bytes
0x2 : _32_BYTE
32 bytes
0x3 : _64_BYTE
64 bytes
0x4 : _128_BYTE
128 bytes
0x5 : _256_BYTE
256 bytes
0x6 : _512_BYTE
512 bytes
0x7 : _1024_BYTE
1024 bytes
End of enumeration elements list.
EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
Enumeration: EPDIRSelect
0 : OUT
The endpoint direction is OUT.
1 : IN
The endpoint direction is IN (nor for control endpoints).
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 9 - 9 (1 bit)
EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
Enumeration: EPTYPESelect
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
NBTRANS : Number of transactions per microframe for isochronous endpoint
bits : 13 - 14 (2 bit)
Enumeration: NBTRANSSelect
0x0 : _0_TRANS
Reserved to endpoint that does not have the high-bandwidth isochronous capability.
0x1 : _1_TRANS
Default value: one transaction per microframe.
0x2 : _2_TRANS
Two transactions per microframe. This endpoint should be configured as double-bank.
0x3 : _3_TRANS
Three transactions per microframe. This endpoint should be configured as triple-bank.
End of enumeration elements list.
Device Endpoint Configuration Register (n = 0) 0
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALLOC : Endpoint Memory Allocate
bits : 1 - 1 (1 bit)
EPBK : Endpoint Banks
bits : 2 - 3 (2 bit)
Enumeration: EPBKSelect
0x0 : _1_BANK
Single-bank endpoint
0x1 : _2_BANK
Double-bank endpoint
0x2 : _3_BANK
Triple-bank endpoint
End of enumeration elements list.
EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
Enumeration: EPSIZESelect
0x0 : _8_BYTE
8 bytes
0x1 : _16_BYTE
16 bytes
0x2 : _32_BYTE
32 bytes
0x3 : _64_BYTE
64 bytes
0x4 : _128_BYTE
128 bytes
0x5 : _256_BYTE
256 bytes
0x6 : _512_BYTE
512 bytes
0x7 : _1024_BYTE
1024 bytes
End of enumeration elements list.
EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
Enumeration: EPDIRSelect
0 : OUT
The endpoint direction is OUT.
1 : IN
The endpoint direction is IN (nor for control endpoints).
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 9 - 9 (1 bit)
EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
Enumeration: EPTYPESelect
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
NBTRANS : Number of transactions per microframe for isochronous endpoint
bits : 13 - 14 (2 bit)
Enumeration: NBTRANSSelect
0x0 : _0_TRANS
Reserved to endpoint that does not have the high-bandwidth isochronous capability.
0x1 : _1_TRANS
Default value: one transaction per microframe.
0x2 : _2_TRANS
Two transactions per microframe. This endpoint should be configured as double-bank.
0x3 : _3_TRANS
Three transactions per microframe. This endpoint should be configured as triple-bank.
End of enumeration elements list.
Device Endpoint Configuration Register (n = 0) 0
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALLOC : Endpoint Memory Allocate
bits : 1 - 1 (1 bit)
EPBK : Endpoint Banks
bits : 2 - 3 (2 bit)
Enumeration: EPBKSelect
0x0 : _1_BANK
Single-bank endpoint
0x1 : _2_BANK
Double-bank endpoint
0x2 : _3_BANK
Triple-bank endpoint
End of enumeration elements list.
EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
Enumeration: EPSIZESelect
0x0 : _8_BYTE
8 bytes
0x1 : _16_BYTE
16 bytes
0x2 : _32_BYTE
32 bytes
0x3 : _64_BYTE
64 bytes
0x4 : _128_BYTE
128 bytes
0x5 : _256_BYTE
256 bytes
0x6 : _512_BYTE
512 bytes
0x7 : _1024_BYTE
1024 bytes
End of enumeration elements list.
EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
Enumeration: EPDIRSelect
0 : OUT
The endpoint direction is OUT.
1 : IN
The endpoint direction is IN (nor for control endpoints).
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 9 - 9 (1 bit)
EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
Enumeration: EPTYPESelect
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
NBTRANS : Number of transactions per microframe for isochronous endpoint
bits : 13 - 14 (2 bit)
Enumeration: NBTRANSSelect
0x0 : _0_TRANS
Reserved to endpoint that does not have the high-bandwidth isochronous capability.
0x1 : _1_TRANS
Default value: one transaction per microframe.
0x2 : _2_TRANS
Two transactions per microframe. This endpoint should be configured as double-bank.
0x3 : _3_TRANS
Three transactions per microframe. This endpoint should be configured as triple-bank.
End of enumeration elements list.
Device Endpoint Configuration Register (n = 0) 0
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALLOC : Endpoint Memory Allocate
bits : 1 - 1 (1 bit)
EPBK : Endpoint Banks
bits : 2 - 3 (2 bit)
Enumeration: EPBKSelect
0x0 : _1_BANK
Single-bank endpoint
0x1 : _2_BANK
Double-bank endpoint
0x2 : _3_BANK
Triple-bank endpoint
End of enumeration elements list.
EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
Enumeration: EPSIZESelect
0x0 : _8_BYTE
8 bytes
0x1 : _16_BYTE
16 bytes
0x2 : _32_BYTE
32 bytes
0x3 : _64_BYTE
64 bytes
0x4 : _128_BYTE
128 bytes
0x5 : _256_BYTE
256 bytes
0x6 : _512_BYTE
512 bytes
0x7 : _1024_BYTE
1024 bytes
End of enumeration elements list.
EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
Enumeration: EPDIRSelect
0 : OUT
The endpoint direction is OUT.
1 : IN
The endpoint direction is IN (nor for control endpoints).
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 9 - 9 (1 bit)
EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
Enumeration: EPTYPESelect
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
NBTRANS : Number of transactions per microframe for isochronous endpoint
bits : 13 - 14 (2 bit)
Enumeration: NBTRANSSelect
0x0 : _0_TRANS
Reserved to endpoint that does not have the high-bandwidth isochronous capability.
0x1 : _1_TRANS
Default value: one transaction per microframe.
0x2 : _2_TRANS
Two transactions per microframe. This endpoint should be configured as double-bank.
0x3 : _3_TRANS
Three transactions per microframe. This endpoint should be configured as triple-bank.
End of enumeration elements list.
Device Endpoint Configuration Register (n = 0) 0
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALLOC : Endpoint Memory Allocate
bits : 1 - 1 (1 bit)
EPBK : Endpoint Banks
bits : 2 - 3 (2 bit)
Enumeration: EPBKSelect
0x0 : _1_BANK
Single-bank endpoint
0x1 : _2_BANK
Double-bank endpoint
0x2 : _3_BANK
Triple-bank endpoint
End of enumeration elements list.
EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
Enumeration: EPSIZESelect
0x0 : _8_BYTE
8 bytes
0x1 : _16_BYTE
16 bytes
0x2 : _32_BYTE
32 bytes
0x3 : _64_BYTE
64 bytes
0x4 : _128_BYTE
128 bytes
0x5 : _256_BYTE
256 bytes
0x6 : _512_BYTE
512 bytes
0x7 : _1024_BYTE
1024 bytes
End of enumeration elements list.
EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
Enumeration: EPDIRSelect
0 : OUT
The endpoint direction is OUT.
1 : IN
The endpoint direction is IN (nor for control endpoints).
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 9 - 9 (1 bit)
EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
Enumeration: EPTYPESelect
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
NBTRANS : Number of transactions per microframe for isochronous endpoint
bits : 13 - 14 (2 bit)
Enumeration: NBTRANSSelect
0x0 : _0_TRANS
Reserved to endpoint that does not have the high-bandwidth isochronous capability.
0x1 : _1_TRANS
Default value: one transaction per microframe.
0x2 : _2_TRANS
Two transactions per microframe. This endpoint should be configured as double-bank.
0x3 : _3_TRANS
Three transactions per microframe. This endpoint should be configured as triple-bank.
End of enumeration elements list.
Device Endpoint Status Register (n = 0) 0
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
SHORTPACKET : Short Packet Interrupt
bits : 7 - 7 (1 bit)
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
Enumeration: DTSEQSelect
0x0 : DATA0
Data0 toggle sequence
0x1 : DATA1
Data1 toggle sequence
0x2 : DATA2
Reserved for high-bandwidth isochronous endpoint
0x3 : MDATA
Reserved for high-bandwidth isochronous endpoint
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
Enumeration: NBUSYBKSelect
0x0 : _0_BUSY
0 busy bank (all banks free)
0x1 : _1_BUSY
1 busy bank
0x2 : _2_BUSY
2 busy banks
0x3 : _3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
Enumeration: CURRBKSelect
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read/Write Allowed
bits : 16 - 16 (1 bit)
CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
BYCT : Byte Count
bits : 20 - 30 (11 bit)
Device Endpoint Status Register (n = 0)
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
UNDERFI : Underflow Interrupt
bits : 2 - 2 (1 bit)
access : read-only
HBISOINERRI : High Bandwidth Isochronous IN Underflow Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only
HBISOFLUSHI : High Bandwidth Isochronous IN Flush Interrupt
bits : 4 - 4 (1 bit)
access : read-only
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
CRCERRI : CRC Error Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKET : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
Enumeration:
0x0 : DATA0
Data0 toggle sequence
0x1 : DATA1
Data1 toggle sequence
0x2 : DATA2
Data2 toggle sequence (for high-bandwidth isochronous endpoint)
0x3 : MDATA
MData toggle sequence (for high-bandwidth isochronous endpoint)
End of enumeration elements list.
ERRORTRANS : High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt
bits : 10 - 10 (1 bit)
access : read-only
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only
Enumeration:
0x0 : 0_BUSY
0 busy bank (all banks free)
0x1 : 1_BUSY
1 busy bank
0x2 : 2_BUSY
2 busy banks
0x3 : 3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read/Write Allowed
bits : 16 - 16 (1 bit)
access : read-only
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only
BYCT : Byte Count
bits : 20 - 30 (11 bit)
access : read-only
Device Endpoint Status Register (n = 0) 0
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
SHORTPACKET : Short Packet Interrupt
bits : 7 - 7 (1 bit)
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
Enumeration: DTSEQSelect
0x0 : DATA0
Data0 toggle sequence
0x1 : DATA1
Data1 toggle sequence
0x2 : DATA2
Reserved for high-bandwidth isochronous endpoint
0x3 : MDATA
Reserved for high-bandwidth isochronous endpoint
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
Enumeration: NBUSYBKSelect
0x0 : _0_BUSY
0 busy bank (all banks free)
0x1 : _1_BUSY
1 busy bank
0x2 : _2_BUSY
2 busy banks
0x3 : _3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
Enumeration: CURRBKSelect
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read/Write Allowed
bits : 16 - 16 (1 bit)
CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
BYCT : Byte Count
bits : 20 - 30 (11 bit)
Device Endpoint Status Register (n = 0) 0
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
SHORTPACKET : Short Packet Interrupt
bits : 7 - 7 (1 bit)
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
Enumeration: DTSEQSelect
0x0 : DATA0
Data0 toggle sequence
0x1 : DATA1
Data1 toggle sequence
0x2 : DATA2
Reserved for high-bandwidth isochronous endpoint
0x3 : MDATA
Reserved for high-bandwidth isochronous endpoint
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
Enumeration: NBUSYBKSelect
0x0 : _0_BUSY
0 busy bank (all banks free)
0x1 : _1_BUSY
1 busy bank
0x2 : _2_BUSY
2 busy banks
0x3 : _3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
Enumeration: CURRBKSelect
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read/Write Allowed
bits : 16 - 16 (1 bit)
CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
BYCT : Byte Count
bits : 20 - 30 (11 bit)
Device Endpoint Status Register (n = 0) 0
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
SHORTPACKET : Short Packet Interrupt
bits : 7 - 7 (1 bit)
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
Enumeration: DTSEQSelect
0x0 : DATA0
Data0 toggle sequence
0x1 : DATA1
Data1 toggle sequence
0x2 : DATA2
Reserved for high-bandwidth isochronous endpoint
0x3 : MDATA
Reserved for high-bandwidth isochronous endpoint
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
Enumeration: NBUSYBKSelect
0x0 : _0_BUSY
0 busy bank (all banks free)
0x1 : _1_BUSY
1 busy bank
0x2 : _2_BUSY
2 busy banks
0x3 : _3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
Enumeration: CURRBKSelect
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read/Write Allowed
bits : 16 - 16 (1 bit)
CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
BYCT : Byte Count
bits : 20 - 30 (11 bit)
Device Global Interrupt Disable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SUSPEC : Suspend Interrupt Disable
bits : 0 - 0 (1 bit)
MSOFEC : Micro Start of Frame Interrupt Disable
bits : 1 - 1 (1 bit)
SOFEC : Start of Frame Interrupt Disable
bits : 2 - 2 (1 bit)
EORSTEC : End of Reset Interrupt Disable
bits : 3 - 3 (1 bit)
WAKEUPEC : Wake-Up Interrupt Disable
bits : 4 - 4 (1 bit)
EORSMEC : End of Resume Interrupt Disable
bits : 5 - 5 (1 bit)
UPRSMEC : Upstream Resume Interrupt Disable
bits : 6 - 6 (1 bit)
PEP_0 : Endpoint 0 Interrupt Disable
bits : 12 - 12 (1 bit)
PEP_1 : Endpoint 1 Interrupt Disable
bits : 13 - 13 (1 bit)
PEP_2 : Endpoint 2 Interrupt Disable
bits : 14 - 14 (1 bit)
PEP_3 : Endpoint 3 Interrupt Disable
bits : 15 - 15 (1 bit)
PEP_4 : Endpoint 4 Interrupt Disable
bits : 16 - 16 (1 bit)
PEP_5 : Endpoint 5 Interrupt Disable
bits : 17 - 17 (1 bit)
PEP_6 : Endpoint 6 Interrupt Disable
bits : 18 - 18 (1 bit)
PEP_7 : Endpoint 7 Interrupt Disable
bits : 19 - 19 (1 bit)
PEP_8 : Endpoint 8 Interrupt Disable
bits : 20 - 20 (1 bit)
PEP_9 : Endpoint 9 Interrupt Disable
bits : 21 - 21 (1 bit)
PEP_10 : Endpoint 10 Interrupt Disable
bits : 22 - 22 (1 bit)
PEP_11 : Endpoint 11 Interrupt Disable
bits : 23 - 23 (1 bit)
DMA_1 : DMA Channel 1 Interrupt Disable
bits : 25 - 25 (1 bit)
DMA_2 : DMA Channel 2 Interrupt Disable
bits : 26 - 26 (1 bit)
DMA_3 : DMA Channel 3 Interrupt Disable
bits : 27 - 27 (1 bit)
DMA_4 : DMA Channel 4 Interrupt Disable
bits : 28 - 28 (1 bit)
DMA_5 : DMA Channel 5 Interrupt Disable
bits : 29 - 29 (1 bit)
DMA_6 : DMA Channel 6 Interrupt Disable
bits : 30 - 30 (1 bit)
DMA_7 : DMA Channel 7 Interrupt Disable
bits : 31 - 31 (1 bit)
Device Endpoint Status Register (n = 0) 0
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
SHORTPACKET : Short Packet Interrupt
bits : 7 - 7 (1 bit)
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
Enumeration: DTSEQSelect
0x0 : DATA0
Data0 toggle sequence
0x1 : DATA1
Data1 toggle sequence
0x2 : DATA2
Reserved for high-bandwidth isochronous endpoint
0x3 : MDATA
Reserved for high-bandwidth isochronous endpoint
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
Enumeration: NBUSYBKSelect
0x0 : _0_BUSY
0 busy bank (all banks free)
0x1 : _1_BUSY
1 busy bank
0x2 : _2_BUSY
2 busy banks
0x3 : _3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
Enumeration: CURRBKSelect
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read/Write Allowed
bits : 16 - 16 (1 bit)
CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
BYCT : Byte Count
bits : 20 - 30 (11 bit)
Device Endpoint Status Register (n = 0) 0
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
SHORTPACKET : Short Packet Interrupt
bits : 7 - 7 (1 bit)
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
Enumeration: DTSEQSelect
0x0 : DATA0
Data0 toggle sequence
0x1 : DATA1
Data1 toggle sequence
0x2 : DATA2
Reserved for high-bandwidth isochronous endpoint
0x3 : MDATA
Reserved for high-bandwidth isochronous endpoint
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
Enumeration: NBUSYBKSelect
0x0 : _0_BUSY
0 busy bank (all banks free)
0x1 : _1_BUSY
1 busy bank
0x2 : _2_BUSY
2 busy banks
0x3 : _3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
Enumeration: CURRBKSelect
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read/Write Allowed
bits : 16 - 16 (1 bit)
CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
BYCT : Byte Count
bits : 20 - 30 (11 bit)
Device Endpoint Status Register (n = 0) 0
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
SHORTPACKET : Short Packet Interrupt
bits : 7 - 7 (1 bit)
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
Enumeration: DTSEQSelect
0x0 : DATA0
Data0 toggle sequence
0x1 : DATA1
Data1 toggle sequence
0x2 : DATA2
Reserved for high-bandwidth isochronous endpoint
0x3 : MDATA
Reserved for high-bandwidth isochronous endpoint
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
Enumeration: NBUSYBKSelect
0x0 : _0_BUSY
0 busy bank (all banks free)
0x1 : _1_BUSY
1 busy bank
0x2 : _2_BUSY
2 busy banks
0x3 : _3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
Enumeration: CURRBKSelect
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read/Write Allowed
bits : 16 - 16 (1 bit)
CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
BYCT : Byte Count
bits : 20 - 30 (11 bit)
Device Endpoint Status Register (n = 0) 0
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
SHORTPACKET : Short Packet Interrupt
bits : 7 - 7 (1 bit)
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
Enumeration: DTSEQSelect
0x0 : DATA0
Data0 toggle sequence
0x1 : DATA1
Data1 toggle sequence
0x2 : DATA2
Reserved for high-bandwidth isochronous endpoint
0x3 : MDATA
Reserved for high-bandwidth isochronous endpoint
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
Enumeration: NBUSYBKSelect
0x0 : _0_BUSY
0 busy bank (all banks free)
0x1 : _1_BUSY
1 busy bank
0x2 : _2_BUSY
2 busy banks
0x3 : _3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
Enumeration: CURRBKSelect
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read/Write Allowed
bits : 16 - 16 (1 bit)
CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
BYCT : Byte Count
bits : 20 - 30 (11 bit)
Device Endpoint Status Register (n = 0) 0
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
SHORTPACKET : Short Packet Interrupt
bits : 7 - 7 (1 bit)
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
Enumeration: DTSEQSelect
0x0 : DATA0
Data0 toggle sequence
0x1 : DATA1
Data1 toggle sequence
0x2 : DATA2
Reserved for high-bandwidth isochronous endpoint
0x3 : MDATA
Reserved for high-bandwidth isochronous endpoint
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
Enumeration: NBUSYBKSelect
0x0 : _0_BUSY
0 busy bank (all banks free)
0x1 : _1_BUSY
1 busy bank
0x2 : _2_BUSY
2 busy banks
0x3 : _3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
Enumeration: CURRBKSelect
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read/Write Allowed
bits : 16 - 16 (1 bit)
CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
BYCT : Byte Count
bits : 20 - 30 (11 bit)
Device Endpoint Status Register (n = 0) 0
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
SHORTPACKET : Short Packet Interrupt
bits : 7 - 7 (1 bit)
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
Enumeration: DTSEQSelect
0x0 : DATA0
Data0 toggle sequence
0x1 : DATA1
Data1 toggle sequence
0x2 : DATA2
Reserved for high-bandwidth isochronous endpoint
0x3 : MDATA
Reserved for high-bandwidth isochronous endpoint
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
Enumeration: NBUSYBKSelect
0x0 : _0_BUSY
0 busy bank (all banks free)
0x1 : _1_BUSY
1 busy bank
0x2 : _2_BUSY
2 busy banks
0x3 : _3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
Enumeration: CURRBKSelect
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read/Write Allowed
bits : 16 - 16 (1 bit)
CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
BYCT : Byte Count
bits : 20 - 30 (11 bit)
Device Endpoint Clear Register (n = 0) 0
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIC : Transmitted IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
RXOUTIC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
RXSTPIC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
NAKOUTIC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
NAKINIC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
STALLEDIC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
SHORTPACKETC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
Device Endpoint Clear Register (n = 0)
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
TXINIC : Transmitted IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
UNDERFIC : Underflow Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
HBISOINERRIC : High Bandwidth Isochronous IN Underflow Error Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only
HBISOFLUSHIC : High Bandwidth Isochronous IN Flush Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
CRCERRIC : CRC Error Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
Device Endpoint Clear Register (n = 0) 0
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIC : Transmitted IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
RXOUTIC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
RXSTPIC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
NAKOUTIC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
NAKINIC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
STALLEDIC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
SHORTPACKETC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
Device Endpoint Clear Register (n = 0) 0
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIC : Transmitted IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
RXOUTIC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
RXSTPIC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
NAKOUTIC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
NAKINIC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
STALLEDIC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
SHORTPACKETC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
Device Endpoint Clear Register (n = 0) 0
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIC : Transmitted IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
RXOUTIC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
RXSTPIC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
NAKOUTIC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
NAKINIC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
STALLEDIC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
SHORTPACKETC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
Device Endpoint Clear Register (n = 0) 0
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIC : Transmitted IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
RXOUTIC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
RXSTPIC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
NAKOUTIC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
NAKINIC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
STALLEDIC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
SHORTPACKETC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
Device Endpoint Clear Register (n = 0) 0
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIC : Transmitted IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
RXOUTIC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
RXSTPIC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
NAKOUTIC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
NAKINIC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
STALLEDIC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
SHORTPACKETC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
Device Endpoint Clear Register (n = 0) 0
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIC : Transmitted IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
RXOUTIC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
RXSTPIC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
NAKOUTIC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
NAKINIC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
STALLEDIC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
SHORTPACKETC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
Device Endpoint Clear Register (n = 0) 0
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIC : Transmitted IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
RXOUTIC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
RXSTPIC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
NAKOUTIC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
NAKINIC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
STALLEDIC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
SHORTPACKETC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
Device Global Interrupt Enable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SUSPES : Suspend Interrupt Enable
bits : 0 - 0 (1 bit)
MSOFES : Micro Start of Frame Interrupt Enable
bits : 1 - 1 (1 bit)
SOFES : Start of Frame Interrupt Enable
bits : 2 - 2 (1 bit)
EORSTES : End of Reset Interrupt Enable
bits : 3 - 3 (1 bit)
WAKEUPES : Wake-Up Interrupt Enable
bits : 4 - 4 (1 bit)
EORSMES : End of Resume Interrupt Enable
bits : 5 - 5 (1 bit)
UPRSMES : Upstream Resume Interrupt Enable
bits : 6 - 6 (1 bit)
PEP_0 : Endpoint 0 Interrupt Enable
bits : 12 - 12 (1 bit)
PEP_1 : Endpoint 1 Interrupt Enable
bits : 13 - 13 (1 bit)
PEP_2 : Endpoint 2 Interrupt Enable
bits : 14 - 14 (1 bit)
PEP_3 : Endpoint 3 Interrupt Enable
bits : 15 - 15 (1 bit)
PEP_4 : Endpoint 4 Interrupt Enable
bits : 16 - 16 (1 bit)
PEP_5 : Endpoint 5 Interrupt Enable
bits : 17 - 17 (1 bit)
PEP_6 : Endpoint 6 Interrupt Enable
bits : 18 - 18 (1 bit)
PEP_7 : Endpoint 7 Interrupt Enable
bits : 19 - 19 (1 bit)
PEP_8 : Endpoint 8 Interrupt Enable
bits : 20 - 20 (1 bit)
PEP_9 : Endpoint 9 Interrupt Enable
bits : 21 - 21 (1 bit)
PEP_10 : Endpoint 10 Interrupt Enable
bits : 22 - 22 (1 bit)
PEP_11 : Endpoint 11 Interrupt Enable
bits : 23 - 23 (1 bit)
DMA_1 : DMA Channel 1 Interrupt Enable
bits : 25 - 25 (1 bit)
DMA_2 : DMA Channel 2 Interrupt Enable
bits : 26 - 26 (1 bit)
DMA_3 : DMA Channel 3 Interrupt Enable
bits : 27 - 27 (1 bit)
DMA_4 : DMA Channel 4 Interrupt Enable
bits : 28 - 28 (1 bit)
DMA_5 : DMA Channel 5 Interrupt Enable
bits : 29 - 29 (1 bit)
DMA_6 : DMA Channel 6 Interrupt Enable
bits : 30 - 30 (1 bit)
DMA_7 : DMA Channel 7 Interrupt Enable
bits : 31 - 31 (1 bit)
Device Endpoint Clear Register (n = 0) 0
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIC : Transmitted IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
RXOUTIC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
RXSTPIC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
NAKOUTIC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
NAKINIC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
STALLEDIC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
SHORTPACKETC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
Device Endpoint Clear Register (n = 0) 0
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIC : Transmitted IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
RXOUTIC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
RXSTPIC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
NAKOUTIC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
NAKINIC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
STALLEDIC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
SHORTPACKETC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
Device Endpoint Set Register (n = 0) 0
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIS : Transmitted IN Data Interrupt Set
bits : 0 - 0 (1 bit)
RXOUTIS : Received OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
RXSTPIS : Received SETUP Interrupt Set
bits : 2 - 2 (1 bit)
NAKOUTIS : NAKed OUT Interrupt Set
bits : 3 - 3 (1 bit)
NAKINIS : NAKed IN Interrupt Set
bits : 4 - 4 (1 bit)
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
STALLEDIS : STALLed Interrupt Set
bits : 6 - 6 (1 bit)
SHORTPACKETS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
NBUSYBKS : Number of Busy Banks Interrupt Set
bits : 12 - 12 (1 bit)
Device Endpoint Set Register (n = 0)
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
TXINIS : Transmitted IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIS : Received OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only
UNDERFIS : Underflow Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only
HBISOINERRIS : High Bandwidth Isochronous IN Underflow Error Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only
HBISOFLUSHIS : High Bandwidth Isochronous IN Flush Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only
CRCERRIS : CRC Error Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKS : Number of Busy Banks Interrupt Set
bits : 12 - 12 (1 bit)
access : write-only
Device Endpoint Set Register (n = 0) 0
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIS : Transmitted IN Data Interrupt Set
bits : 0 - 0 (1 bit)
RXOUTIS : Received OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
RXSTPIS : Received SETUP Interrupt Set
bits : 2 - 2 (1 bit)
NAKOUTIS : NAKed OUT Interrupt Set
bits : 3 - 3 (1 bit)
NAKINIS : NAKed IN Interrupt Set
bits : 4 - 4 (1 bit)
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
STALLEDIS : STALLed Interrupt Set
bits : 6 - 6 (1 bit)
SHORTPACKETS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
NBUSYBKS : Number of Busy Banks Interrupt Set
bits : 12 - 12 (1 bit)
Device Endpoint Set Register (n = 0) 0
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIS : Transmitted IN Data Interrupt Set
bits : 0 - 0 (1 bit)
RXOUTIS : Received OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
RXSTPIS : Received SETUP Interrupt Set
bits : 2 - 2 (1 bit)
NAKOUTIS : NAKed OUT Interrupt Set
bits : 3 - 3 (1 bit)
NAKINIS : NAKed IN Interrupt Set
bits : 4 - 4 (1 bit)
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
STALLEDIS : STALLed Interrupt Set
bits : 6 - 6 (1 bit)
SHORTPACKETS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
NBUSYBKS : Number of Busy Banks Interrupt Set
bits : 12 - 12 (1 bit)
Device Endpoint Set Register (n = 0) 0
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIS : Transmitted IN Data Interrupt Set
bits : 0 - 0 (1 bit)
RXOUTIS : Received OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
RXSTPIS : Received SETUP Interrupt Set
bits : 2 - 2 (1 bit)
NAKOUTIS : NAKed OUT Interrupt Set
bits : 3 - 3 (1 bit)
NAKINIS : NAKed IN Interrupt Set
bits : 4 - 4 (1 bit)
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
STALLEDIS : STALLed Interrupt Set
bits : 6 - 6 (1 bit)
SHORTPACKETS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
NBUSYBKS : Number of Busy Banks Interrupt Set
bits : 12 - 12 (1 bit)
Device Endpoint Set Register (n = 0) 0
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIS : Transmitted IN Data Interrupt Set
bits : 0 - 0 (1 bit)
RXOUTIS : Received OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
RXSTPIS : Received SETUP Interrupt Set
bits : 2 - 2 (1 bit)
NAKOUTIS : NAKed OUT Interrupt Set
bits : 3 - 3 (1 bit)
NAKINIS : NAKed IN Interrupt Set
bits : 4 - 4 (1 bit)
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
STALLEDIS : STALLed Interrupt Set
bits : 6 - 6 (1 bit)
SHORTPACKETS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
NBUSYBKS : Number of Busy Banks Interrupt Set
bits : 12 - 12 (1 bit)
Device Endpoint Set Register (n = 0) 0
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIS : Transmitted IN Data Interrupt Set
bits : 0 - 0 (1 bit)
RXOUTIS : Received OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
RXSTPIS : Received SETUP Interrupt Set
bits : 2 - 2 (1 bit)
NAKOUTIS : NAKed OUT Interrupt Set
bits : 3 - 3 (1 bit)
NAKINIS : NAKed IN Interrupt Set
bits : 4 - 4 (1 bit)
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
STALLEDIS : STALLed Interrupt Set
bits : 6 - 6 (1 bit)
SHORTPACKETS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
NBUSYBKS : Number of Busy Banks Interrupt Set
bits : 12 - 12 (1 bit)
Device Endpoint Set Register (n = 0) 0
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIS : Transmitted IN Data Interrupt Set
bits : 0 - 0 (1 bit)
RXOUTIS : Received OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
RXSTPIS : Received SETUP Interrupt Set
bits : 2 - 2 (1 bit)
NAKOUTIS : NAKed OUT Interrupt Set
bits : 3 - 3 (1 bit)
NAKINIS : NAKed IN Interrupt Set
bits : 4 - 4 (1 bit)
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
STALLEDIS : STALLed Interrupt Set
bits : 6 - 6 (1 bit)
SHORTPACKETS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
NBUSYBKS : Number of Busy Banks Interrupt Set
bits : 12 - 12 (1 bit)
Device Endpoint Set Register (n = 0) 0
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIS : Transmitted IN Data Interrupt Set
bits : 0 - 0 (1 bit)
RXOUTIS : Received OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
RXSTPIS : Received SETUP Interrupt Set
bits : 2 - 2 (1 bit)
NAKOUTIS : NAKed OUT Interrupt Set
bits : 3 - 3 (1 bit)
NAKINIS : NAKed IN Interrupt Set
bits : 4 - 4 (1 bit)
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
STALLEDIS : STALLed Interrupt Set
bits : 6 - 6 (1 bit)
SHORTPACKETS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
NBUSYBKS : Number of Busy Banks Interrupt Set
bits : 12 - 12 (1 bit)
Device Endpoint Set Register (n = 0) 0
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIS : Transmitted IN Data Interrupt Set
bits : 0 - 0 (1 bit)
RXOUTIS : Received OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
RXSTPIS : Received SETUP Interrupt Set
bits : 2 - 2 (1 bit)
NAKOUTIS : NAKed OUT Interrupt Set
bits : 3 - 3 (1 bit)
NAKINIS : NAKed IN Interrupt Set
bits : 4 - 4 (1 bit)
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
STALLEDIS : STALLed Interrupt Set
bits : 6 - 6 (1 bit)
SHORTPACKETS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
NBUSYBKS : Number of Busy Banks Interrupt Set
bits : 12 - 12 (1 bit)
Device Endpoint Set Register (n = 0) 0
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIS : Transmitted IN Data Interrupt Set
bits : 0 - 0 (1 bit)
RXOUTIS : Received OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
RXSTPIS : Received SETUP Interrupt Set
bits : 2 - 2 (1 bit)
NAKOUTIS : NAKed OUT Interrupt Set
bits : 3 - 3 (1 bit)
NAKINIS : NAKed IN Interrupt Set
bits : 4 - 4 (1 bit)
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
STALLEDIS : STALLed Interrupt Set
bits : 6 - 6 (1 bit)
SHORTPACKETS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
NBUSYBKS : Number of Busy Banks Interrupt Set
bits : 12 - 12 (1 bit)
Device Endpoint Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPEN0 : Endpoint 0 Enable
bits : 0 - 0 (1 bit)
EPEN1 : Endpoint 1 Enable
bits : 1 - 1 (1 bit)
EPEN2 : Endpoint 2 Enable
bits : 2 - 2 (1 bit)
EPEN3 : Endpoint 3 Enable
bits : 3 - 3 (1 bit)
EPEN4 : Endpoint 4 Enable
bits : 4 - 4 (1 bit)
EPEN5 : Endpoint 5 Enable
bits : 5 - 5 (1 bit)
EPEN6 : Endpoint 6 Enable
bits : 6 - 6 (1 bit)
EPEN7 : Endpoint 7 Enable
bits : 7 - 7 (1 bit)
EPEN8 : Endpoint 8 Enable
bits : 8 - 8 (1 bit)
EPEN9 : Endpoint 9 Enable
bits : 9 - 9 (1 bit)
EPRST0 : Endpoint 0 Reset
bits : 16 - 16 (1 bit)
EPRST1 : Endpoint 1 Reset
bits : 17 - 17 (1 bit)
EPRST2 : Endpoint 2 Reset
bits : 18 - 18 (1 bit)
EPRST3 : Endpoint 3 Reset
bits : 19 - 19 (1 bit)
EPRST4 : Endpoint 4 Reset
bits : 20 - 20 (1 bit)
EPRST5 : Endpoint 5 Reset
bits : 21 - 21 (1 bit)
EPRST6 : Endpoint 6 Reset
bits : 22 - 22 (1 bit)
EPRST7 : Endpoint 7 Reset
bits : 23 - 23 (1 bit)
EPRST8 : Endpoint 8 Reset
bits : 24 - 24 (1 bit)
EPRST9 : Endpoint 9 Reset
bits : 25 - 25 (1 bit)
Device Endpoint Mask Register (n = 0) 0
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINE : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
RXOUTE : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
RXSTPE : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
NAKOUTE : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
NAKINE : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
OVERFE : Overflow Interrupt
bits : 5 - 5 (1 bit)
STALLEDE : STALLed Interrupt
bits : 6 - 6 (1 bit)
SHORTPACKETE : Short Packet Interrupt
bits : 7 - 7 (1 bit)
NBUSYBKE : Number of Busy Banks Interrupt
bits : 12 - 12 (1 bit)
KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
EPDISHDMA : Endpoint Interrupts Disable HDMA Request
bits : 16 - 16 (1 bit)
NYETDIS : NYET Token Disable
bits : 17 - 17 (1 bit)
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
Device Endpoint Mask Register (n = 0)
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
TXINE : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
RXOUTE : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
UNDERFE : Underflow Interrupt
bits : 2 - 2 (1 bit)
access : read-only
HBISOINERRE : High Bandwidth Isochronous IN Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only
HBISOFLUSHE : High Bandwidth Isochronous IN Flush Interrupt
bits : 4 - 4 (1 bit)
access : read-only
OVERFE : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
CRCERRE : CRC Error Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETE : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
MDATAE : MData Interrupt
bits : 8 - 8 (1 bit)
access : read-only
DATAXE : DataX Interrupt
bits : 9 - 9 (1 bit)
access : read-only
ERRORTRANSE : Transaction Error Interrupt
bits : 10 - 10 (1 bit)
access : read-only
NBUSYBKE : Number of Busy Banks Interrupt
bits : 12 - 12 (1 bit)
access : read-only
KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
EPDISHDMA : Endpoint Interrupts Disable HDMA Request
bits : 16 - 16 (1 bit)
access : read-only
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only
Device Endpoint Mask Register (n = 0) 0
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINE : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
RXOUTE : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
RXSTPE : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
NAKOUTE : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
NAKINE : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
OVERFE : Overflow Interrupt
bits : 5 - 5 (1 bit)
STALLEDE : STALLed Interrupt
bits : 6 - 6 (1 bit)
SHORTPACKETE : Short Packet Interrupt
bits : 7 - 7 (1 bit)
NBUSYBKE : Number of Busy Banks Interrupt
bits : 12 - 12 (1 bit)
KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
EPDISHDMA : Endpoint Interrupts Disable HDMA Request
bits : 16 - 16 (1 bit)
NYETDIS : NYET Token Disable
bits : 17 - 17 (1 bit)
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
Device Endpoint Mask Register (n = 0) 0
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINE : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
RXOUTE : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
RXSTPE : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
NAKOUTE : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
NAKINE : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
OVERFE : Overflow Interrupt
bits : 5 - 5 (1 bit)
STALLEDE : STALLed Interrupt
bits : 6 - 6 (1 bit)
SHORTPACKETE : Short Packet Interrupt
bits : 7 - 7 (1 bit)
NBUSYBKE : Number of Busy Banks Interrupt
bits : 12 - 12 (1 bit)
KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
EPDISHDMA : Endpoint Interrupts Disable HDMA Request
bits : 16 - 16 (1 bit)
NYETDIS : NYET Token Disable
bits : 17 - 17 (1 bit)
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
Device Endpoint Mask Register (n = 0) 0
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINE : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
RXOUTE : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
RXSTPE : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
NAKOUTE : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
NAKINE : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
OVERFE : Overflow Interrupt
bits : 5 - 5 (1 bit)
STALLEDE : STALLed Interrupt
bits : 6 - 6 (1 bit)
SHORTPACKETE : Short Packet Interrupt
bits : 7 - 7 (1 bit)
NBUSYBKE : Number of Busy Banks Interrupt
bits : 12 - 12 (1 bit)
KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
EPDISHDMA : Endpoint Interrupts Disable HDMA Request
bits : 16 - 16 (1 bit)
NYETDIS : NYET Token Disable
bits : 17 - 17 (1 bit)
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
Device Endpoint Mask Register (n = 0) 0
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINE : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
RXOUTE : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
RXSTPE : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
NAKOUTE : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
NAKINE : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
OVERFE : Overflow Interrupt
bits : 5 - 5 (1 bit)
STALLEDE : STALLed Interrupt
bits : 6 - 6 (1 bit)
SHORTPACKETE : Short Packet Interrupt
bits : 7 - 7 (1 bit)
NBUSYBKE : Number of Busy Banks Interrupt
bits : 12 - 12 (1 bit)
KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
EPDISHDMA : Endpoint Interrupts Disable HDMA Request
bits : 16 - 16 (1 bit)
NYETDIS : NYET Token Disable
bits : 17 - 17 (1 bit)
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
Device Endpoint Mask Register (n = 0) 0
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINE : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
RXOUTE : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
RXSTPE : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
NAKOUTE : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
NAKINE : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
OVERFE : Overflow Interrupt
bits : 5 - 5 (1 bit)
STALLEDE : STALLed Interrupt
bits : 6 - 6 (1 bit)
SHORTPACKETE : Short Packet Interrupt
bits : 7 - 7 (1 bit)
NBUSYBKE : Number of Busy Banks Interrupt
bits : 12 - 12 (1 bit)
KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
EPDISHDMA : Endpoint Interrupts Disable HDMA Request
bits : 16 - 16 (1 bit)
NYETDIS : NYET Token Disable
bits : 17 - 17 (1 bit)
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
Device Endpoint Mask Register (n = 0) 0
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINE : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
RXOUTE : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
RXSTPE : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
NAKOUTE : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
NAKINE : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
OVERFE : Overflow Interrupt
bits : 5 - 5 (1 bit)
STALLEDE : STALLed Interrupt
bits : 6 - 6 (1 bit)
SHORTPACKETE : Short Packet Interrupt
bits : 7 - 7 (1 bit)
NBUSYBKE : Number of Busy Banks Interrupt
bits : 12 - 12 (1 bit)
KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
EPDISHDMA : Endpoint Interrupts Disable HDMA Request
bits : 16 - 16 (1 bit)
NYETDIS : NYET Token Disable
bits : 17 - 17 (1 bit)
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
Device Endpoint Mask Register (n = 0) 0
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINE : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
RXOUTE : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
RXSTPE : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
NAKOUTE : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
NAKINE : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
OVERFE : Overflow Interrupt
bits : 5 - 5 (1 bit)
STALLEDE : STALLed Interrupt
bits : 6 - 6 (1 bit)
SHORTPACKETE : Short Packet Interrupt
bits : 7 - 7 (1 bit)
NBUSYBKE : Number of Busy Banks Interrupt
bits : 12 - 12 (1 bit)
KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
EPDISHDMA : Endpoint Interrupts Disable HDMA Request
bits : 16 - 16 (1 bit)
NYETDIS : NYET Token Disable
bits : 17 - 17 (1 bit)
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
Device Endpoint Mask Register (n = 0) 0
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINE : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
RXOUTE : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
RXSTPE : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
NAKOUTE : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
NAKINE : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
OVERFE : Overflow Interrupt
bits : 5 - 5 (1 bit)
STALLEDE : STALLed Interrupt
bits : 6 - 6 (1 bit)
SHORTPACKETE : Short Packet Interrupt
bits : 7 - 7 (1 bit)
NBUSYBKE : Number of Busy Banks Interrupt
bits : 12 - 12 (1 bit)
KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
EPDISHDMA : Endpoint Interrupts Disable HDMA Request
bits : 16 - 16 (1 bit)
NYETDIS : NYET Token Disable
bits : 17 - 17 (1 bit)
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
Device Endpoint Mask Register (n = 0) 0
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINE : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
RXOUTE : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
RXSTPE : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
NAKOUTE : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
NAKINE : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
OVERFE : Overflow Interrupt
bits : 5 - 5 (1 bit)
STALLEDE : STALLed Interrupt
bits : 6 - 6 (1 bit)
SHORTPACKETE : Short Packet Interrupt
bits : 7 - 7 (1 bit)
NBUSYBKE : Number of Busy Banks Interrupt
bits : 12 - 12 (1 bit)
KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
EPDISHDMA : Endpoint Interrupts Disable HDMA Request
bits : 16 - 16 (1 bit)
NYETDIS : NYET Token Disable
bits : 17 - 17 (1 bit)
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
Device Endpoint Enable Register (n = 0) 0
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINES : Transmitted IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
RXOUTES : Received OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
RXSTPES : Received SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
NAKOUTES : NAKed OUT Interrupt Enable
bits : 3 - 3 (1 bit)
NAKINES : NAKed IN Interrupt Enable
bits : 4 - 4 (1 bit)
OVERFES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
STALLEDES : STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
SHORTPACKETES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
NBUSYBKES : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
KILLBKS : Kill IN Bank
bits : 13 - 13 (1 bit)
FIFOCONS : FIFO Control
bits : 14 - 14 (1 bit)
EPDISHDMAS : Endpoint Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
NYETDISS : NYET Token Disable Enable
bits : 17 - 17 (1 bit)
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
STALLRQS : STALL Request Enable
bits : 19 - 19 (1 bit)
Device Endpoint Enable Register (n = 0)
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
TXINES : Transmitted IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
RXOUTES : Received OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
UNDERFES : Underflow Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
HBISOINERRES : High Bandwidth Isochronous IN Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
HBISOFLUSHES : High Bandwidth Isochronous IN Flush Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
OVERFES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
CRCERRES : CRC Error Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
MDATAES : MData Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
DATAXES : DataX Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
ERRORTRANSES : Transaction Error Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
NBUSYBKES : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
KILLBKS : Kill IN Bank
bits : 13 - 13 (1 bit)
access : write-only
FIFOCONS : FIFO Control
bits : 14 - 14 (1 bit)
access : write-only
EPDISHDMAS : Endpoint Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only
STALLRQS : STALL Request Enable
bits : 19 - 19 (1 bit)
access : write-only
Device Endpoint Enable Register (n = 0) 0
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINES : Transmitted IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
RXOUTES : Received OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
RXSTPES : Received SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
NAKOUTES : NAKed OUT Interrupt Enable
bits : 3 - 3 (1 bit)
NAKINES : NAKed IN Interrupt Enable
bits : 4 - 4 (1 bit)
OVERFES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
STALLEDES : STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
SHORTPACKETES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
NBUSYBKES : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
KILLBKS : Kill IN Bank
bits : 13 - 13 (1 bit)
FIFOCONS : FIFO Control
bits : 14 - 14 (1 bit)
EPDISHDMAS : Endpoint Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
NYETDISS : NYET Token Disable Enable
bits : 17 - 17 (1 bit)
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
STALLRQS : STALL Request Enable
bits : 19 - 19 (1 bit)
Device Endpoint Enable Register (n = 0) 0
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINES : Transmitted IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
RXOUTES : Received OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
RXSTPES : Received SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
NAKOUTES : NAKed OUT Interrupt Enable
bits : 3 - 3 (1 bit)
NAKINES : NAKed IN Interrupt Enable
bits : 4 - 4 (1 bit)
OVERFES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
STALLEDES : STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
SHORTPACKETES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
NBUSYBKES : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
KILLBKS : Kill IN Bank
bits : 13 - 13 (1 bit)
FIFOCONS : FIFO Control
bits : 14 - 14 (1 bit)
EPDISHDMAS : Endpoint Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
NYETDISS : NYET Token Disable Enable
bits : 17 - 17 (1 bit)
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
STALLRQS : STALL Request Enable
bits : 19 - 19 (1 bit)
Device Endpoint Enable Register (n = 0) 0
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINES : Transmitted IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
RXOUTES : Received OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
RXSTPES : Received SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
NAKOUTES : NAKed OUT Interrupt Enable
bits : 3 - 3 (1 bit)
NAKINES : NAKed IN Interrupt Enable
bits : 4 - 4 (1 bit)
OVERFES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
STALLEDES : STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
SHORTPACKETES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
NBUSYBKES : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
KILLBKS : Kill IN Bank
bits : 13 - 13 (1 bit)
FIFOCONS : FIFO Control
bits : 14 - 14 (1 bit)
EPDISHDMAS : Endpoint Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
NYETDISS : NYET Token Disable Enable
bits : 17 - 17 (1 bit)
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
STALLRQS : STALL Request Enable
bits : 19 - 19 (1 bit)
Device Frame Number Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFNUM : Micro Frame Number
bits : 0 - 2 (3 bit)
FNUM : Frame Number
bits : 3 - 13 (11 bit)
FNCERR : Frame Number CRC Error
bits : 15 - 15 (1 bit)
Device Endpoint Enable Register (n = 0) 0
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINES : Transmitted IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
RXOUTES : Received OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
RXSTPES : Received SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
NAKOUTES : NAKed OUT Interrupt Enable
bits : 3 - 3 (1 bit)
NAKINES : NAKed IN Interrupt Enable
bits : 4 - 4 (1 bit)
OVERFES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
STALLEDES : STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
SHORTPACKETES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
NBUSYBKES : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
KILLBKS : Kill IN Bank
bits : 13 - 13 (1 bit)
FIFOCONS : FIFO Control
bits : 14 - 14 (1 bit)
EPDISHDMAS : Endpoint Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
NYETDISS : NYET Token Disable Enable
bits : 17 - 17 (1 bit)
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
STALLRQS : STALL Request Enable
bits : 19 - 19 (1 bit)
Device Endpoint Enable Register (n = 0) 0
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINES : Transmitted IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
RXOUTES : Received OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
RXSTPES : Received SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
NAKOUTES : NAKed OUT Interrupt Enable
bits : 3 - 3 (1 bit)
NAKINES : NAKed IN Interrupt Enable
bits : 4 - 4 (1 bit)
OVERFES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
STALLEDES : STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
SHORTPACKETES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
NBUSYBKES : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
KILLBKS : Kill IN Bank
bits : 13 - 13 (1 bit)
FIFOCONS : FIFO Control
bits : 14 - 14 (1 bit)
EPDISHDMAS : Endpoint Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
NYETDISS : NYET Token Disable Enable
bits : 17 - 17 (1 bit)
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
STALLRQS : STALL Request Enable
bits : 19 - 19 (1 bit)
Device Endpoint Enable Register (n = 0) 0
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINES : Transmitted IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
RXOUTES : Received OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
RXSTPES : Received SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
NAKOUTES : NAKed OUT Interrupt Enable
bits : 3 - 3 (1 bit)
NAKINES : NAKed IN Interrupt Enable
bits : 4 - 4 (1 bit)
OVERFES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
STALLEDES : STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
SHORTPACKETES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
NBUSYBKES : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
KILLBKS : Kill IN Bank
bits : 13 - 13 (1 bit)
FIFOCONS : FIFO Control
bits : 14 - 14 (1 bit)
EPDISHDMAS : Endpoint Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
NYETDISS : NYET Token Disable Enable
bits : 17 - 17 (1 bit)
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
STALLRQS : STALL Request Enable
bits : 19 - 19 (1 bit)
Device Endpoint Enable Register (n = 0) 0
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINES : Transmitted IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
RXOUTES : Received OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
RXSTPES : Received SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
NAKOUTES : NAKed OUT Interrupt Enable
bits : 3 - 3 (1 bit)
NAKINES : NAKed IN Interrupt Enable
bits : 4 - 4 (1 bit)
OVERFES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
STALLEDES : STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
SHORTPACKETES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
NBUSYBKES : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
KILLBKS : Kill IN Bank
bits : 13 - 13 (1 bit)
FIFOCONS : FIFO Control
bits : 14 - 14 (1 bit)
EPDISHDMAS : Endpoint Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
NYETDISS : NYET Token Disable Enable
bits : 17 - 17 (1 bit)
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
STALLRQS : STALL Request Enable
bits : 19 - 19 (1 bit)
Device Endpoint Enable Register (n = 0) 0
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINES : Transmitted IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
RXOUTES : Received OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
RXSTPES : Received SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
NAKOUTES : NAKed OUT Interrupt Enable
bits : 3 - 3 (1 bit)
NAKINES : NAKed IN Interrupt Enable
bits : 4 - 4 (1 bit)
OVERFES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
STALLEDES : STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
SHORTPACKETES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
NBUSYBKES : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
KILLBKS : Kill IN Bank
bits : 13 - 13 (1 bit)
FIFOCONS : FIFO Control
bits : 14 - 14 (1 bit)
EPDISHDMAS : Endpoint Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
NYETDISS : NYET Token Disable Enable
bits : 17 - 17 (1 bit)
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
STALLRQS : STALL Request Enable
bits : 19 - 19 (1 bit)
Device Endpoint Enable Register (n = 0) 0
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINES : Transmitted IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
RXOUTES : Received OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
RXSTPES : Received SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
NAKOUTES : NAKed OUT Interrupt Enable
bits : 3 - 3 (1 bit)
NAKINES : NAKed IN Interrupt Enable
bits : 4 - 4 (1 bit)
OVERFES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
STALLEDES : STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
SHORTPACKETES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
NBUSYBKES : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
KILLBKS : Kill IN Bank
bits : 13 - 13 (1 bit)
FIFOCONS : FIFO Control
bits : 14 - 14 (1 bit)
EPDISHDMAS : Endpoint Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
NYETDISS : NYET Token Disable Enable
bits : 17 - 17 (1 bit)
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
STALLRQS : STALL Request Enable
bits : 19 - 19 (1 bit)
Device Endpoint Disable Register (n = 0) 0
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINEC : Transmitted IN Interrupt Clear
bits : 0 - 0 (1 bit)
RXOUTEC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
RXSTPEC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
NAKOUTEC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
NAKINEC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
OVERFEC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
STALLEDEC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
SHORTPACKETEC : Shortpacket Interrupt Clear
bits : 7 - 7 (1 bit)
NBUSYBKEC : Number of Busy Banks Interrupt Clear
bits : 12 - 12 (1 bit)
FIFOCONC : FIFO Control Clear
bits : 14 - 14 (1 bit)
EPDISHDMAC : Endpoint Interrupts Disable HDMA Request Clear
bits : 16 - 16 (1 bit)
NYETDISC : NYET Token Disable Clear
bits : 17 - 17 (1 bit)
STALLRQC : STALL Request Clear
bits : 19 - 19 (1 bit)
Device Endpoint Disable Register (n = 0)
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
TXINEC : Transmitted IN Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTEC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
UNDERFEC : Underflow Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
HBISOINERREC : High Bandwidth Isochronous IN Error Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only
HBISOFLUSHEC : High Bandwidth Isochronous IN Flush Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
OVERFEC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
CRCERREC : CRC Error Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETEC : Shortpacket Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
MDATEC : MData Interrupt Clear
bits : 8 - 8 (1 bit)
access : write-only
DATAXEC : DataX Interrupt Clear
bits : 9 - 9 (1 bit)
access : write-only
ERRORTRANSEC : Transaction Error Interrupt Clear
bits : 10 - 10 (1 bit)
access : write-only
NBUSYBKEC : Number of Busy Banks Interrupt Clear
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFO Control Clear
bits : 14 - 14 (1 bit)
access : write-only
EPDISHDMAC : Endpoint Interrupts Disable HDMA Request Clear
bits : 16 - 16 (1 bit)
access : write-only
Device Endpoint Disable Register (n = 0) 0
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINEC : Transmitted IN Interrupt Clear
bits : 0 - 0 (1 bit)
RXOUTEC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
RXSTPEC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
NAKOUTEC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
NAKINEC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
OVERFEC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
STALLEDEC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
SHORTPACKETEC : Shortpacket Interrupt Clear
bits : 7 - 7 (1 bit)
NBUSYBKEC : Number of Busy Banks Interrupt Clear
bits : 12 - 12 (1 bit)
FIFOCONC : FIFO Control Clear
bits : 14 - 14 (1 bit)
EPDISHDMAC : Endpoint Interrupts Disable HDMA Request Clear
bits : 16 - 16 (1 bit)
NYETDISC : NYET Token Disable Clear
bits : 17 - 17 (1 bit)
STALLRQC : STALL Request Clear
bits : 19 - 19 (1 bit)
Device Endpoint Disable Register (n = 0) 0
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINEC : Transmitted IN Interrupt Clear
bits : 0 - 0 (1 bit)
RXOUTEC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
RXSTPEC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
NAKOUTEC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
NAKINEC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
OVERFEC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
STALLEDEC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
SHORTPACKETEC : Shortpacket Interrupt Clear
bits : 7 - 7 (1 bit)
NBUSYBKEC : Number of Busy Banks Interrupt Clear
bits : 12 - 12 (1 bit)
FIFOCONC : FIFO Control Clear
bits : 14 - 14 (1 bit)
EPDISHDMAC : Endpoint Interrupts Disable HDMA Request Clear
bits : 16 - 16 (1 bit)
NYETDISC : NYET Token Disable Clear
bits : 17 - 17 (1 bit)
STALLRQC : STALL Request Clear
bits : 19 - 19 (1 bit)
Device Endpoint Disable Register (n = 0) 0
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINEC : Transmitted IN Interrupt Clear
bits : 0 - 0 (1 bit)
RXOUTEC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
RXSTPEC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
NAKOUTEC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
NAKINEC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
OVERFEC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
STALLEDEC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
SHORTPACKETEC : Shortpacket Interrupt Clear
bits : 7 - 7 (1 bit)
NBUSYBKEC : Number of Busy Banks Interrupt Clear
bits : 12 - 12 (1 bit)
FIFOCONC : FIFO Control Clear
bits : 14 - 14 (1 bit)
EPDISHDMAC : Endpoint Interrupts Disable HDMA Request Clear
bits : 16 - 16 (1 bit)
NYETDISC : NYET Token Disable Clear
bits : 17 - 17 (1 bit)
STALLRQC : STALL Request Clear
bits : 19 - 19 (1 bit)
Device Endpoint Disable Register (n = 0) 0
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINEC : Transmitted IN Interrupt Clear
bits : 0 - 0 (1 bit)
RXOUTEC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
RXSTPEC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
NAKOUTEC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
NAKINEC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
OVERFEC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
STALLEDEC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
SHORTPACKETEC : Shortpacket Interrupt Clear
bits : 7 - 7 (1 bit)
NBUSYBKEC : Number of Busy Banks Interrupt Clear
bits : 12 - 12 (1 bit)
FIFOCONC : FIFO Control Clear
bits : 14 - 14 (1 bit)
EPDISHDMAC : Endpoint Interrupts Disable HDMA Request Clear
bits : 16 - 16 (1 bit)
NYETDISC : NYET Token Disable Clear
bits : 17 - 17 (1 bit)
STALLRQC : STALL Request Clear
bits : 19 - 19 (1 bit)
Device Endpoint Disable Register (n = 0) 0
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINEC : Transmitted IN Interrupt Clear
bits : 0 - 0 (1 bit)
RXOUTEC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
RXSTPEC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
NAKOUTEC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
NAKINEC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
OVERFEC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
STALLEDEC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
SHORTPACKETEC : Shortpacket Interrupt Clear
bits : 7 - 7 (1 bit)
NBUSYBKEC : Number of Busy Banks Interrupt Clear
bits : 12 - 12 (1 bit)
FIFOCONC : FIFO Control Clear
bits : 14 - 14 (1 bit)
EPDISHDMAC : Endpoint Interrupts Disable HDMA Request Clear
bits : 16 - 16 (1 bit)
NYETDISC : NYET Token Disable Clear
bits : 17 - 17 (1 bit)
STALLRQC : STALL Request Clear
bits : 19 - 19 (1 bit)
Device Endpoint Disable Register (n = 0) 0
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINEC : Transmitted IN Interrupt Clear
bits : 0 - 0 (1 bit)
RXOUTEC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
RXSTPEC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
NAKOUTEC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
NAKINEC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
OVERFEC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
STALLEDEC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
SHORTPACKETEC : Shortpacket Interrupt Clear
bits : 7 - 7 (1 bit)
NBUSYBKEC : Number of Busy Banks Interrupt Clear
bits : 12 - 12 (1 bit)
FIFOCONC : FIFO Control Clear
bits : 14 - 14 (1 bit)
EPDISHDMAC : Endpoint Interrupts Disable HDMA Request Clear
bits : 16 - 16 (1 bit)
NYETDISC : NYET Token Disable Clear
bits : 17 - 17 (1 bit)
STALLRQC : STALL Request Clear
bits : 19 - 19 (1 bit)
Device Endpoint Disable Register (n = 0) 0
address_offset : 0x23C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINEC : Transmitted IN Interrupt Clear
bits : 0 - 0 (1 bit)
RXOUTEC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
RXSTPEC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
NAKOUTEC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
NAKINEC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
OVERFEC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
STALLEDEC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
SHORTPACKETEC : Shortpacket Interrupt Clear
bits : 7 - 7 (1 bit)
NBUSYBKEC : Number of Busy Banks Interrupt Clear
bits : 12 - 12 (1 bit)
FIFOCONC : FIFO Control Clear
bits : 14 - 14 (1 bit)
EPDISHDMAC : Endpoint Interrupts Disable HDMA Request Clear
bits : 16 - 16 (1 bit)
NYETDISC : NYET Token Disable Clear
bits : 17 - 17 (1 bit)
STALLRQC : STALL Request Clear
bits : 19 - 19 (1 bit)
Device Endpoint Disable Register (n = 0) 0
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINEC : Transmitted IN Interrupt Clear
bits : 0 - 0 (1 bit)
RXOUTEC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
RXSTPEC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
NAKOUTEC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
NAKINEC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
OVERFEC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
STALLEDEC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
SHORTPACKETEC : Shortpacket Interrupt Clear
bits : 7 - 7 (1 bit)
NBUSYBKEC : Number of Busy Banks Interrupt Clear
bits : 12 - 12 (1 bit)
FIFOCONC : FIFO Control Clear
bits : 14 - 14 (1 bit)
EPDISHDMAC : Endpoint Interrupts Disable HDMA Request Clear
bits : 16 - 16 (1 bit)
NYETDISC : NYET Token Disable Clear
bits : 17 - 17 (1 bit)
STALLRQC : STALL Request Clear
bits : 19 - 19 (1 bit)
Device Endpoint Disable Register (n = 0) 0
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINEC : Transmitted IN Interrupt Clear
bits : 0 - 0 (1 bit)
RXOUTEC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
RXSTPEC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
NAKOUTEC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
NAKINEC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
OVERFEC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
STALLEDEC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
SHORTPACKETEC : Shortpacket Interrupt Clear
bits : 7 - 7 (1 bit)
NBUSYBKEC : Number of Busy Banks Interrupt Clear
bits : 12 - 12 (1 bit)
FIFOCONC : FIFO Control Clear
bits : 14 - 14 (1 bit)
EPDISHDMAC : Endpoint Interrupts Disable HDMA Request Clear
bits : 16 - 16 (1 bit)
NYETDISC : NYET Token Disable Clear
bits : 17 - 17 (1 bit)
STALLRQC : STALL Request Clear
bits : 19 - 19 (1 bit)
Device DMA Channel Next Descriptor Address Register (n = 1)
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write
Device DMA Channel Address Register (n = 1)
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write
Device DMA Channel Control Register (n = 1)
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CHANN_ENB : Channel Enable Command
bits : 0 - 0 (1 bit)
access : read-write
LDNXT_DSC : Load Next Channel Transfer Descriptor Enable Command
bits : 1 - 1 (1 bit)
access : read-write
END_TR_EN : End of Transfer Enable Control (OUT transfers only)
bits : 2 - 2 (1 bit)
access : read-write
END_B_EN : End of Buffer Enable Control
bits : 3 - 3 (1 bit)
access : read-write
END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write
BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write
Device DMA Channel Status Register (n = 1)
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write
CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write
END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write
END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write
DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write
BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write
Device DMA Channel Next Descriptor Address Register (n = 2)
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write
Device DMA Channel Address Register (n = 2)
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write
Device DMA Channel Control Register (n = 2)
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CHANN_ENB : Channel Enable Command
bits : 0 - 0 (1 bit)
access : read-write
LDNXT_DSC : Load Next Channel Transfer Descriptor Enable Command
bits : 1 - 1 (1 bit)
access : read-write
END_TR_EN : End of Transfer Enable Control (OUT transfers only)
bits : 2 - 2 (1 bit)
access : read-write
END_B_EN : End of Buffer Enable Control
bits : 3 - 3 (1 bit)
access : read-write
END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write
BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write
Device DMA Channel Status Register (n = 2)
address_offset : 0x32C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write
CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write
END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write
END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write
DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write
BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write
Device DMA Channel Next Descriptor Address Register (n = 3)
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write
Device DMA Channel Address Register (n = 3)
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write
Device DMA Channel Control Register (n = 3)
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CHANN_ENB : Channel Enable Command
bits : 0 - 0 (1 bit)
access : read-write
LDNXT_DSC : Load Next Channel Transfer Descriptor Enable Command
bits : 1 - 1 (1 bit)
access : read-write
END_TR_EN : End of Transfer Enable Control (OUT transfers only)
bits : 2 - 2 (1 bit)
access : read-write
END_B_EN : End of Buffer Enable Control
bits : 3 - 3 (1 bit)
access : read-write
END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write
BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write
Device DMA Channel Status Register (n = 3)
address_offset : 0x33C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write
CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write
END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write
END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write
DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write
BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write
Device DMA Channel Next Descriptor Address Register (n = 4)
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write
Device DMA Channel Address Register (n = 4)
address_offset : 0x344 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write
Device DMA Channel Control Register (n = 4)
address_offset : 0x348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CHANN_ENB : Channel Enable Command
bits : 0 - 0 (1 bit)
access : read-write
LDNXT_DSC : Load Next Channel Transfer Descriptor Enable Command
bits : 1 - 1 (1 bit)
access : read-write
END_TR_EN : End of Transfer Enable Control (OUT transfers only)
bits : 2 - 2 (1 bit)
access : read-write
END_B_EN : End of Buffer Enable Control
bits : 3 - 3 (1 bit)
access : read-write
END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write
BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write
Device DMA Channel Status Register (n = 4)
address_offset : 0x34C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write
CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write
END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write
END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write
DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write
BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write
Device DMA Channel Next Descriptor Address Register (n = 5)
address_offset : 0x350 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write
Device DMA Channel Address Register (n = 5)
address_offset : 0x354 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write
Device DMA Channel Control Register (n = 5)
address_offset : 0x358 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CHANN_ENB : Channel Enable Command
bits : 0 - 0 (1 bit)
access : read-write
LDNXT_DSC : Load Next Channel Transfer Descriptor Enable Command
bits : 1 - 1 (1 bit)
access : read-write
END_TR_EN : End of Transfer Enable Control (OUT transfers only)
bits : 2 - 2 (1 bit)
access : read-write
END_B_EN : End of Buffer Enable Control
bits : 3 - 3 (1 bit)
access : read-write
END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write
BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write
Device DMA Channel Status Register (n = 5)
address_offset : 0x35C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write
CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write
END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write
END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write
DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write
BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write
Device DMA Channel Next Descriptor Address Register (n = 6)
address_offset : 0x360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write
Device DMA Channel Address Register (n = 6)
address_offset : 0x364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write
Device DMA Channel Control Register (n = 6)
address_offset : 0x368 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CHANN_ENB : Channel Enable Command
bits : 0 - 0 (1 bit)
access : read-write
LDNXT_DSC : Load Next Channel Transfer Descriptor Enable Command
bits : 1 - 1 (1 bit)
access : read-write
END_TR_EN : End of Transfer Enable Control (OUT transfers only)
bits : 2 - 2 (1 bit)
access : read-write
END_B_EN : End of Buffer Enable Control
bits : 3 - 3 (1 bit)
access : read-write
END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write
BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write
Device DMA Channel Status Register (n = 6)
address_offset : 0x36C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write
CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write
END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write
END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write
DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write
BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write
Device DMA Channel Next Descriptor Address Register (n = 7)
address_offset : 0x370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write
Device DMA Channel Address Register (n = 7)
address_offset : 0x374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write
Device DMA Channel Control Register (n = 7)
address_offset : 0x378 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CHANN_ENB : Channel Enable Command
bits : 0 - 0 (1 bit)
access : read-write
LDNXT_DSC : Load Next Channel Transfer Descriptor Enable Command
bits : 1 - 1 (1 bit)
access : read-write
END_TR_EN : End of Transfer Enable Control (OUT transfers only)
bits : 2 - 2 (1 bit)
access : read-write
END_B_EN : End of Buffer Enable Control
bits : 3 - 3 (1 bit)
access : read-write
END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write
BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write
Device DMA Channel Status Register (n = 7)
address_offset : 0x37C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write
CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write
END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write
END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write
DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write
BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write
Device Global Interrupt Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUSP : Suspend Interrupt
bits : 0 - 0 (1 bit)
MSOF : Micro Start of Frame Interrupt
bits : 1 - 1 (1 bit)
SOF : Start of Frame Interrupt
bits : 2 - 2 (1 bit)
EORST : End of Reset Interrupt
bits : 3 - 3 (1 bit)
WAKEUP : Wake-Up Interrupt
bits : 4 - 4 (1 bit)
EORSM : End of Resume Interrupt
bits : 5 - 5 (1 bit)
UPRSM : Upstream Resume Interrupt
bits : 6 - 6 (1 bit)
PEP_0 : Endpoint 0 Interrupt
bits : 12 - 12 (1 bit)
PEP_1 : Endpoint 1 Interrupt
bits : 13 - 13 (1 bit)
PEP_2 : Endpoint 2 Interrupt
bits : 14 - 14 (1 bit)
PEP_3 : Endpoint 3 Interrupt
bits : 15 - 15 (1 bit)
PEP_4 : Endpoint 4 Interrupt
bits : 16 - 16 (1 bit)
PEP_5 : Endpoint 5 Interrupt
bits : 17 - 17 (1 bit)
PEP_6 : Endpoint 6 Interrupt
bits : 18 - 18 (1 bit)
PEP_7 : Endpoint 7 Interrupt
bits : 19 - 19 (1 bit)
PEP_8 : Endpoint 8 Interrupt
bits : 20 - 20 (1 bit)
PEP_9 : Endpoint 9 Interrupt
bits : 21 - 21 (1 bit)
PEP_10 : Endpoint 10 Interrupt
bits : 22 - 22 (1 bit)
PEP_11 : Endpoint 11 Interrupt
bits : 23 - 23 (1 bit)
DMA_1 : DMA Channel 1 Interrupt
bits : 25 - 25 (1 bit)
DMA_2 : DMA Channel 2 Interrupt
bits : 26 - 26 (1 bit)
DMA_3 : DMA Channel 3 Interrupt
bits : 27 - 27 (1 bit)
DMA_4 : DMA Channel 4 Interrupt
bits : 28 - 28 (1 bit)
DMA_5 : DMA Channel 5 Interrupt
bits : 29 - 29 (1 bit)
DMA_6 : DMA Channel 6 Interrupt
bits : 30 - 30 (1 bit)
DMA_7 : DMA Channel 7 Interrupt
bits : 31 - 31 (1 bit)
Device DMA Channel Address Register (n = 1)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
Host DMA Channel Address Register (n = 1)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
Host General Control Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFE : Start of Frame Generation Enable
bits : 8 - 8 (1 bit)
RESET : Send USB Reset
bits : 9 - 9 (1 bit)
RESUME : Send USB Resume
bits : 10 - 10 (1 bit)
SPDCONF : Mode Configuration
bits : 12 - 13 (2 bit)
Enumeration: SPDCONFSelect
0 : NORMAL
The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable.
1 : LOW_POWER
For a better consumption, if high speed is not needed.
End of enumeration elements list.
Host Global Interrupt Status Register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DCONNI : Device Connection Interrupt
bits : 0 - 0 (1 bit)
DDISCI : Device Disconnection Interrupt
bits : 1 - 1 (1 bit)
RSTI : USB Reset Sent Interrupt
bits : 2 - 2 (1 bit)
RSMEDI : Downstream Resume Sent Interrupt
bits : 3 - 3 (1 bit)
RXRSMI : Upstream Resume Received Interrupt
bits : 4 - 4 (1 bit)
HSOFI : Host Start of Frame Interrupt
bits : 5 - 5 (1 bit)
HWUPI : Host Wake-Up Interrupt
bits : 6 - 6 (1 bit)
PEP_0 : Pipe 0 Interrupt
bits : 8 - 8 (1 bit)
PEP_1 : Pipe 1 Interrupt
bits : 9 - 9 (1 bit)
PEP_2 : Pipe 2 Interrupt
bits : 10 - 10 (1 bit)
PEP_3 : Pipe 3 Interrupt
bits : 11 - 11 (1 bit)
PEP_4 : Pipe 4 Interrupt
bits : 12 - 12 (1 bit)
PEP_5 : Pipe 5 Interrupt
bits : 13 - 13 (1 bit)
PEP_6 : Pipe 6 Interrupt
bits : 14 - 14 (1 bit)
PEP_7 : Pipe 7 Interrupt
bits : 15 - 15 (1 bit)
PEP_8 : Pipe 8 Interrupt
bits : 16 - 16 (1 bit)
PEP_9 : Pipe 9 Interrupt
bits : 17 - 17 (1 bit)
PEP_10 : Pipe 10 Interrupt
bits : 18 - 18 (1 bit)
PEP_11 : Pipe 11 Interrupt
bits : 19 - 19 (1 bit)
DMA_1 : DMA Channel 1 Interrupt
bits : 25 - 25 (1 bit)
DMA_2 : DMA Channel 2 Interrupt
bits : 26 - 26 (1 bit)
DMA_3 : DMA Channel 3 Interrupt
bits : 27 - 27 (1 bit)
DMA_4 : DMA Channel 4 Interrupt
bits : 28 - 28 (1 bit)
DMA_5 : DMA Channel 5 Interrupt
bits : 29 - 29 (1 bit)
DMA_6 : DMA Channel 6 Interrupt
bits : 30 - 30 (1 bit)
DMA_7 : DMA Channel 7 Interrupt
bits : 31 - 31 (1 bit)
Host Global Interrupt Clear Register
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DCONNIC : Device Connection Interrupt Clear
bits : 0 - 0 (1 bit)
DDISCIC : Device Disconnection Interrupt Clear
bits : 1 - 1 (1 bit)
RSTIC : USB Reset Sent Interrupt Clear
bits : 2 - 2 (1 bit)
RSMEDIC : Downstream Resume Sent Interrupt Clear
bits : 3 - 3 (1 bit)
RXRSMIC : Upstream Resume Received Interrupt Clear
bits : 4 - 4 (1 bit)
HSOFIC : Host Start of Frame Interrupt Clear
bits : 5 - 5 (1 bit)
HWUPIC : Host Wake-Up Interrupt Clear
bits : 6 - 6 (1 bit)
Host Global Interrupt Set Register
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DCONNIS : Device Connection Interrupt Set
bits : 0 - 0 (1 bit)
DDISCIS : Device Disconnection Interrupt Set
bits : 1 - 1 (1 bit)
RSTIS : USB Reset Sent Interrupt Set
bits : 2 - 2 (1 bit)
RSMEDIS : Downstream Resume Sent Interrupt Set
bits : 3 - 3 (1 bit)
RXRSMIS : Upstream Resume Received Interrupt Set
bits : 4 - 4 (1 bit)
HSOFIS : Host Start of Frame Interrupt Set
bits : 5 - 5 (1 bit)
HWUPIS : Host Wake-Up Interrupt Set
bits : 6 - 6 (1 bit)
DMA_1 : DMA Channel 1 Interrupt Set
bits : 25 - 25 (1 bit)
DMA_2 : DMA Channel 2 Interrupt Set
bits : 26 - 26 (1 bit)
DMA_3 : DMA Channel 3 Interrupt Set
bits : 27 - 27 (1 bit)
DMA_4 : DMA Channel 4 Interrupt Set
bits : 28 - 28 (1 bit)
DMA_5 : DMA Channel 5 Interrupt Set
bits : 29 - 29 (1 bit)
DMA_6 : DMA Channel 6 Interrupt Set
bits : 30 - 30 (1 bit)
DMA_7 : DMA Channel 7 Interrupt Set
bits : 31 - 31 (1 bit)
Host Global Interrupt Mask Register
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DCONNIE : Device Connection Interrupt Enable
bits : 0 - 0 (1 bit)
DDISCIE : Device Disconnection Interrupt Enable
bits : 1 - 1 (1 bit)
RSTIE : USB Reset Sent Interrupt Enable
bits : 2 - 2 (1 bit)
RSMEDIE : Downstream Resume Sent Interrupt Enable
bits : 3 - 3 (1 bit)
RXRSMIE : Upstream Resume Received Interrupt Enable
bits : 4 - 4 (1 bit)
HSOFIE : Host Start of Frame Interrupt Enable
bits : 5 - 5 (1 bit)
HWUPIE : Host Wake-Up Interrupt Enable
bits : 6 - 6 (1 bit)
PEP_0 : Pipe 0 Interrupt Enable
bits : 8 - 8 (1 bit)
PEP_1 : Pipe 1 Interrupt Enable
bits : 9 - 9 (1 bit)
PEP_2 : Pipe 2 Interrupt Enable
bits : 10 - 10 (1 bit)
PEP_3 : Pipe 3 Interrupt Enable
bits : 11 - 11 (1 bit)
PEP_4 : Pipe 4 Interrupt Enable
bits : 12 - 12 (1 bit)
PEP_5 : Pipe 5 Interrupt Enable
bits : 13 - 13 (1 bit)
PEP_6 : Pipe 6 Interrupt Enable
bits : 14 - 14 (1 bit)
PEP_7 : Pipe 7 Interrupt Enable
bits : 15 - 15 (1 bit)
PEP_8 : Pipe 8 Interrupt Enable
bits : 16 - 16 (1 bit)
PEP_9 : Pipe 9 Interrupt Enable
bits : 17 - 17 (1 bit)
PEP_10 : Pipe 10 Interrupt Enable
bits : 18 - 18 (1 bit)
PEP_11 : Pipe 11 Interrupt Enable
bits : 19 - 19 (1 bit)
DMA_1 : DMA Channel 1 Interrupt Enable
bits : 25 - 25 (1 bit)
DMA_2 : DMA Channel 2 Interrupt Enable
bits : 26 - 26 (1 bit)
DMA_3 : DMA Channel 3 Interrupt Enable
bits : 27 - 27 (1 bit)
DMA_4 : DMA Channel 4 Interrupt Enable
bits : 28 - 28 (1 bit)
DMA_5 : DMA Channel 5 Interrupt Enable
bits : 29 - 29 (1 bit)
DMA_6 : DMA Channel 6 Interrupt Enable
bits : 30 - 30 (1 bit)
DMA_7 : DMA Channel 7 Interrupt Enable
bits : 31 - 31 (1 bit)
Host Global Interrupt Disable Register
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DCONNIEC : Device Connection Interrupt Disable
bits : 0 - 0 (1 bit)
DDISCIEC : Device Disconnection Interrupt Disable
bits : 1 - 1 (1 bit)
RSTIEC : USB Reset Sent Interrupt Disable
bits : 2 - 2 (1 bit)
RSMEDIEC : Downstream Resume Sent Interrupt Disable
bits : 3 - 3 (1 bit)
RXRSMIEC : Upstream Resume Received Interrupt Disable
bits : 4 - 4 (1 bit)
HSOFIEC : Host Start of Frame Interrupt Disable
bits : 5 - 5 (1 bit)
HWUPIEC : Host Wake-Up Interrupt Disable
bits : 6 - 6 (1 bit)
PEP_0 : Pipe 0 Interrupt Disable
bits : 8 - 8 (1 bit)
PEP_1 : Pipe 1 Interrupt Disable
bits : 9 - 9 (1 bit)
PEP_2 : Pipe 2 Interrupt Disable
bits : 10 - 10 (1 bit)
PEP_3 : Pipe 3 Interrupt Disable
bits : 11 - 11 (1 bit)
PEP_4 : Pipe 4 Interrupt Disable
bits : 12 - 12 (1 bit)
PEP_5 : Pipe 5 Interrupt Disable
bits : 13 - 13 (1 bit)
PEP_6 : Pipe 6 Interrupt Disable
bits : 14 - 14 (1 bit)
PEP_7 : Pipe 7 Interrupt Disable
bits : 15 - 15 (1 bit)
PEP_8 : Pipe 8 Interrupt Disable
bits : 16 - 16 (1 bit)
PEP_9 : Pipe 9 Interrupt Disable
bits : 17 - 17 (1 bit)
PEP_10 : Pipe 10 Interrupt Disable
bits : 18 - 18 (1 bit)
PEP_11 : Pipe 11 Interrupt Disable
bits : 19 - 19 (1 bit)
DMA_1 : DMA Channel 1 Interrupt Disable
bits : 25 - 25 (1 bit)
DMA_2 : DMA Channel 2 Interrupt Disable
bits : 26 - 26 (1 bit)
DMA_3 : DMA Channel 3 Interrupt Disable
bits : 27 - 27 (1 bit)
DMA_4 : DMA Channel 4 Interrupt Disable
bits : 28 - 28 (1 bit)
DMA_5 : DMA Channel 5 Interrupt Disable
bits : 29 - 29 (1 bit)
DMA_6 : DMA Channel 6 Interrupt Disable
bits : 30 - 30 (1 bit)
DMA_7 : DMA Channel 7 Interrupt Disable
bits : 31 - 31 (1 bit)
Host Global Interrupt Enable Register
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DCONNIES : Device Connection Interrupt Enable
bits : 0 - 0 (1 bit)
DDISCIES : Device Disconnection Interrupt Enable
bits : 1 - 1 (1 bit)
RSTIES : USB Reset Sent Interrupt Enable
bits : 2 - 2 (1 bit)
RSMEDIES : Downstream Resume Sent Interrupt Enable
bits : 3 - 3 (1 bit)
RXRSMIES : Upstream Resume Received Interrupt Enable
bits : 4 - 4 (1 bit)
HSOFIES : Host Start of Frame Interrupt Enable
bits : 5 - 5 (1 bit)
HWUPIES : Host Wake-Up Interrupt Enable
bits : 6 - 6 (1 bit)
PEP_0 : Pipe 0 Interrupt Enable
bits : 8 - 8 (1 bit)
PEP_1 : Pipe 1 Interrupt Enable
bits : 9 - 9 (1 bit)
PEP_2 : Pipe 2 Interrupt Enable
bits : 10 - 10 (1 bit)
PEP_3 : Pipe 3 Interrupt Enable
bits : 11 - 11 (1 bit)
PEP_4 : Pipe 4 Interrupt Enable
bits : 12 - 12 (1 bit)
PEP_5 : Pipe 5 Interrupt Enable
bits : 13 - 13 (1 bit)
PEP_6 : Pipe 6 Interrupt Enable
bits : 14 - 14 (1 bit)
PEP_7 : Pipe 7 Interrupt Enable
bits : 15 - 15 (1 bit)
PEP_8 : Pipe 8 Interrupt Enable
bits : 16 - 16 (1 bit)
PEP_9 : Pipe 9 Interrupt Enable
bits : 17 - 17 (1 bit)
PEP_10 : Pipe 10 Interrupt Enable
bits : 18 - 18 (1 bit)
PEP_11 : Pipe 11 Interrupt Enable
bits : 19 - 19 (1 bit)
DMA_1 : DMA Channel 1 Interrupt Enable
bits : 25 - 25 (1 bit)
DMA_2 : DMA Channel 2 Interrupt Enable
bits : 26 - 26 (1 bit)
DMA_3 : DMA Channel 3 Interrupt Enable
bits : 27 - 27 (1 bit)
DMA_4 : DMA Channel 4 Interrupt Enable
bits : 28 - 28 (1 bit)
DMA_5 : DMA Channel 5 Interrupt Enable
bits : 29 - 29 (1 bit)
DMA_6 : DMA Channel 6 Interrupt Enable
bits : 30 - 30 (1 bit)
DMA_7 : DMA Channel 7 Interrupt Enable
bits : 31 - 31 (1 bit)
Host Pipe Register
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEN0 : Pipe 0 Enable
bits : 0 - 0 (1 bit)
PEN1 : Pipe 1 Enable
bits : 1 - 1 (1 bit)
PEN2 : Pipe 2 Enable
bits : 2 - 2 (1 bit)
PEN3 : Pipe 3 Enable
bits : 3 - 3 (1 bit)
PEN4 : Pipe 4 Enable
bits : 4 - 4 (1 bit)
PEN5 : Pipe 5 Enable
bits : 5 - 5 (1 bit)
PEN6 : Pipe 6 Enable
bits : 6 - 6 (1 bit)
PEN7 : Pipe 7 Enable
bits : 7 - 7 (1 bit)
PEN8 : Pipe 8 Enable
bits : 8 - 8 (1 bit)
PRST0 : Pipe 0 Reset
bits : 16 - 16 (1 bit)
PRST1 : Pipe 1 Reset
bits : 17 - 17 (1 bit)
PRST2 : Pipe 2 Reset
bits : 18 - 18 (1 bit)
PRST3 : Pipe 3 Reset
bits : 19 - 19 (1 bit)
PRST4 : Pipe 4 Reset
bits : 20 - 20 (1 bit)
PRST5 : Pipe 5 Reset
bits : 21 - 21 (1 bit)
PRST6 : Pipe 6 Reset
bits : 22 - 22 (1 bit)
PRST7 : Pipe 7 Reset
bits : 23 - 23 (1 bit)
PRST8 : Pipe 8 Reset
bits : 24 - 24 (1 bit)
Host Frame Number Register
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MFNUM : Micro Frame Number
bits : 0 - 2 (3 bit)
FNUM : Frame Number
bits : 3 - 13 (11 bit)
FLENHIGH : Frame Length
bits : 16 - 23 (8 bit)
Host Address 1 Register
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSTADDRP0 : USB Host Address
bits : 0 - 6 (7 bit)
HSTADDRP1 : USB Host Address
bits : 8 - 14 (7 bit)
HSTADDRP2 : USB Host Address
bits : 16 - 22 (7 bit)
HSTADDRP3 : USB Host Address
bits : 24 - 30 (7 bit)
Host Address 2 Register
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSTADDRP4 : USB Host Address
bits : 0 - 6 (7 bit)
HSTADDRP5 : USB Host Address
bits : 8 - 14 (7 bit)
HSTADDRP6 : USB Host Address
bits : 16 - 22 (7 bit)
HSTADDRP7 : USB Host Address
bits : 24 - 30 (7 bit)
Host Address 3 Register
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSTADDRP8 : USB Host Address
bits : 0 - 6 (7 bit)
HSTADDRP9 : USB Host Address
bits : 8 - 14 (7 bit)
Host Pipe Configuration Register (n = 0) 0
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALLOC : Pipe Memory Allocate
bits : 1 - 1 (1 bit)
PBK : Pipe Banks
bits : 2 - 3 (2 bit)
Enumeration: PBKSelect
0x0 : _1_BANK
Single-bank pipe
0x1 : _2_BANK
Double-bank pipe
0x2 : _3_BANK
Triple-bank pipe
End of enumeration elements list.
PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
Enumeration: PSIZESelect
0x0 : _8_BYTE
8 bytes
0x1 : _16_BYTE
16 bytes
0x2 : _32_BYTE
32 bytes
0x3 : _64_BYTE
64 bytes
0x4 : _128_BYTE
128 bytes
0x5 : _256_BYTE
256 bytes
0x6 : _512_BYTE
512 bytes
0x7 : _1024_BYTE
1024 bytes
End of enumeration elements list.
PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
Enumeration: PTOKENSelect
0x0 : SETUP
SETUP
0x1 : IN
IN
0x2 : OUT
OUT
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 10 - 10 (1 bit)
PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
Enumeration: PTYPESelect
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
PEPNUM : Pipe Endpoint Number
bits : 16 - 19 (4 bit)
INTFRQ : Pipe Interrupt Request Frequency
bits : 24 - 31 (8 bit)
Host Pipe Configuration Register (n = 0)
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ALLOC : Pipe Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write
PBK : Pipe Banks
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : 1_BANK
Single-bank pipe
0x1 : 2_BANK
Double-bank pipe
0x2 : 3_BANK
Triple-bank pipe
End of enumeration elements list.
PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : 8_BYTE
8 bytes
0x1 : 16_BYTE
16 bytes
0x2 : 32_BYTE
32 bytes
0x3 : 64_BYTE
64 bytes
0x4 : 128_BYTE
128 bytes
0x5 : 256_BYTE
256 bytes
0x6 : 512_BYTE
512 bytes
0x7 : 1024_BYTE
1024 bytes
End of enumeration elements list.
PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : SETUP
SETUP
0x1 : IN
IN
0x2 : OUT
OUT
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 10 - 10 (1 bit)
access : read-write
PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x2 : BLK
Bulk
End of enumeration elements list.
PEPNUM : Pipe Endpoint Number
bits : 16 - 19 (4 bit)
access : read-write
PINGEN : Ping Enable
bits : 20 - 20 (1 bit)
access : read-write
BINTERVAL : Binterval Parameter for the Bulk-Out/Ping Transaction
bits : 24 - 31 (8 bit)
access : read-write
Host Pipe Configuration Register (n = 0) 0
address_offset : 0x504 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALLOC : Pipe Memory Allocate
bits : 1 - 1 (1 bit)
PBK : Pipe Banks
bits : 2 - 3 (2 bit)
Enumeration: PBKSelect
0x0 : _1_BANK
Single-bank pipe
0x1 : _2_BANK
Double-bank pipe
0x2 : _3_BANK
Triple-bank pipe
End of enumeration elements list.
PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
Enumeration: PSIZESelect
0x0 : _8_BYTE
8 bytes
0x1 : _16_BYTE
16 bytes
0x2 : _32_BYTE
32 bytes
0x3 : _64_BYTE
64 bytes
0x4 : _128_BYTE
128 bytes
0x5 : _256_BYTE
256 bytes
0x6 : _512_BYTE
512 bytes
0x7 : _1024_BYTE
1024 bytes
End of enumeration elements list.
PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
Enumeration: PTOKENSelect
0x0 : SETUP
SETUP
0x1 : IN
IN
0x2 : OUT
OUT
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 10 - 10 (1 bit)
PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
Enumeration: PTYPESelect
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
PEPNUM : Pipe Endpoint Number
bits : 16 - 19 (4 bit)
INTFRQ : Pipe Interrupt Request Frequency
bits : 24 - 31 (8 bit)
Host Pipe Configuration Register (n = 0) 0
address_offset : 0x508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALLOC : Pipe Memory Allocate
bits : 1 - 1 (1 bit)
PBK : Pipe Banks
bits : 2 - 3 (2 bit)
Enumeration: PBKSelect
0x0 : _1_BANK
Single-bank pipe
0x1 : _2_BANK
Double-bank pipe
0x2 : _3_BANK
Triple-bank pipe
End of enumeration elements list.
PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
Enumeration: PSIZESelect
0x0 : _8_BYTE
8 bytes
0x1 : _16_BYTE
16 bytes
0x2 : _32_BYTE
32 bytes
0x3 : _64_BYTE
64 bytes
0x4 : _128_BYTE
128 bytes
0x5 : _256_BYTE
256 bytes
0x6 : _512_BYTE
512 bytes
0x7 : _1024_BYTE
1024 bytes
End of enumeration elements list.
PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
Enumeration: PTOKENSelect
0x0 : SETUP
SETUP
0x1 : IN
IN
0x2 : OUT
OUT
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 10 - 10 (1 bit)
PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
Enumeration: PTYPESelect
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
PEPNUM : Pipe Endpoint Number
bits : 16 - 19 (4 bit)
INTFRQ : Pipe Interrupt Request Frequency
bits : 24 - 31 (8 bit)
Host Pipe Configuration Register (n = 0) 0
address_offset : 0x50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALLOC : Pipe Memory Allocate
bits : 1 - 1 (1 bit)
PBK : Pipe Banks
bits : 2 - 3 (2 bit)
Enumeration: PBKSelect
0x0 : _1_BANK
Single-bank pipe
0x1 : _2_BANK
Double-bank pipe
0x2 : _3_BANK
Triple-bank pipe
End of enumeration elements list.
PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
Enumeration: PSIZESelect
0x0 : _8_BYTE
8 bytes
0x1 : _16_BYTE
16 bytes
0x2 : _32_BYTE
32 bytes
0x3 : _64_BYTE
64 bytes
0x4 : _128_BYTE
128 bytes
0x5 : _256_BYTE
256 bytes
0x6 : _512_BYTE
512 bytes
0x7 : _1024_BYTE
1024 bytes
End of enumeration elements list.
PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
Enumeration: PTOKENSelect
0x0 : SETUP
SETUP
0x1 : IN
IN
0x2 : OUT
OUT
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 10 - 10 (1 bit)
PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
Enumeration: PTYPESelect
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
PEPNUM : Pipe Endpoint Number
bits : 16 - 19 (4 bit)
INTFRQ : Pipe Interrupt Request Frequency
bits : 24 - 31 (8 bit)
Host Pipe Configuration Register (n = 0) 0
address_offset : 0x510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALLOC : Pipe Memory Allocate
bits : 1 - 1 (1 bit)
PBK : Pipe Banks
bits : 2 - 3 (2 bit)
Enumeration: PBKSelect
0x0 : _1_BANK
Single-bank pipe
0x1 : _2_BANK
Double-bank pipe
0x2 : _3_BANK
Triple-bank pipe
End of enumeration elements list.
PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
Enumeration: PSIZESelect
0x0 : _8_BYTE
8 bytes
0x1 : _16_BYTE
16 bytes
0x2 : _32_BYTE
32 bytes
0x3 : _64_BYTE
64 bytes
0x4 : _128_BYTE
128 bytes
0x5 : _256_BYTE
256 bytes
0x6 : _512_BYTE
512 bytes
0x7 : _1024_BYTE
1024 bytes
End of enumeration elements list.
PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
Enumeration: PTOKENSelect
0x0 : SETUP
SETUP
0x1 : IN
IN
0x2 : OUT
OUT
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 10 - 10 (1 bit)
PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
Enumeration: PTYPESelect
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
PEPNUM : Pipe Endpoint Number
bits : 16 - 19 (4 bit)
INTFRQ : Pipe Interrupt Request Frequency
bits : 24 - 31 (8 bit)
Host Pipe Configuration Register (n = 0) 0
address_offset : 0x514 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALLOC : Pipe Memory Allocate
bits : 1 - 1 (1 bit)
PBK : Pipe Banks
bits : 2 - 3 (2 bit)
Enumeration: PBKSelect
0x0 : _1_BANK
Single-bank pipe
0x1 : _2_BANK
Double-bank pipe
0x2 : _3_BANK
Triple-bank pipe
End of enumeration elements list.
PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
Enumeration: PSIZESelect
0x0 : _8_BYTE
8 bytes
0x1 : _16_BYTE
16 bytes
0x2 : _32_BYTE
32 bytes
0x3 : _64_BYTE
64 bytes
0x4 : _128_BYTE
128 bytes
0x5 : _256_BYTE
256 bytes
0x6 : _512_BYTE
512 bytes
0x7 : _1024_BYTE
1024 bytes
End of enumeration elements list.
PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
Enumeration: PTOKENSelect
0x0 : SETUP
SETUP
0x1 : IN
IN
0x2 : OUT
OUT
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 10 - 10 (1 bit)
PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
Enumeration: PTYPESelect
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
PEPNUM : Pipe Endpoint Number
bits : 16 - 19 (4 bit)
INTFRQ : Pipe Interrupt Request Frequency
bits : 24 - 31 (8 bit)
Host Pipe Configuration Register (n = 0) 0
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALLOC : Pipe Memory Allocate
bits : 1 - 1 (1 bit)
PBK : Pipe Banks
bits : 2 - 3 (2 bit)
Enumeration: PBKSelect
0x0 : _1_BANK
Single-bank pipe
0x1 : _2_BANK
Double-bank pipe
0x2 : _3_BANK
Triple-bank pipe
End of enumeration elements list.
PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
Enumeration: PSIZESelect
0x0 : _8_BYTE
8 bytes
0x1 : _16_BYTE
16 bytes
0x2 : _32_BYTE
32 bytes
0x3 : _64_BYTE
64 bytes
0x4 : _128_BYTE
128 bytes
0x5 : _256_BYTE
256 bytes
0x6 : _512_BYTE
512 bytes
0x7 : _1024_BYTE
1024 bytes
End of enumeration elements list.
PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
Enumeration: PTOKENSelect
0x0 : SETUP
SETUP
0x1 : IN
IN
0x2 : OUT
OUT
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 10 - 10 (1 bit)
PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
Enumeration: PTYPESelect
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
PEPNUM : Pipe Endpoint Number
bits : 16 - 19 (4 bit)
INTFRQ : Pipe Interrupt Request Frequency
bits : 24 - 31 (8 bit)
Host Pipe Configuration Register (n = 0) 0
address_offset : 0x51C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALLOC : Pipe Memory Allocate
bits : 1 - 1 (1 bit)
PBK : Pipe Banks
bits : 2 - 3 (2 bit)
Enumeration: PBKSelect
0x0 : _1_BANK
Single-bank pipe
0x1 : _2_BANK
Double-bank pipe
0x2 : _3_BANK
Triple-bank pipe
End of enumeration elements list.
PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
Enumeration: PSIZESelect
0x0 : _8_BYTE
8 bytes
0x1 : _16_BYTE
16 bytes
0x2 : _32_BYTE
32 bytes
0x3 : _64_BYTE
64 bytes
0x4 : _128_BYTE
128 bytes
0x5 : _256_BYTE
256 bytes
0x6 : _512_BYTE
512 bytes
0x7 : _1024_BYTE
1024 bytes
End of enumeration elements list.
PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
Enumeration: PTOKENSelect
0x0 : SETUP
SETUP
0x1 : IN
IN
0x2 : OUT
OUT
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 10 - 10 (1 bit)
PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
Enumeration: PTYPESelect
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
PEPNUM : Pipe Endpoint Number
bits : 16 - 19 (4 bit)
INTFRQ : Pipe Interrupt Request Frequency
bits : 24 - 31 (8 bit)
Host Pipe Configuration Register (n = 0) 0
address_offset : 0x520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALLOC : Pipe Memory Allocate
bits : 1 - 1 (1 bit)
PBK : Pipe Banks
bits : 2 - 3 (2 bit)
Enumeration: PBKSelect
0x0 : _1_BANK
Single-bank pipe
0x1 : _2_BANK
Double-bank pipe
0x2 : _3_BANK
Triple-bank pipe
End of enumeration elements list.
PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
Enumeration: PSIZESelect
0x0 : _8_BYTE
8 bytes
0x1 : _16_BYTE
16 bytes
0x2 : _32_BYTE
32 bytes
0x3 : _64_BYTE
64 bytes
0x4 : _128_BYTE
128 bytes
0x5 : _256_BYTE
256 bytes
0x6 : _512_BYTE
512 bytes
0x7 : _1024_BYTE
1024 bytes
End of enumeration elements list.
PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
Enumeration: PTOKENSelect
0x0 : SETUP
SETUP
0x1 : IN
IN
0x2 : OUT
OUT
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 10 - 10 (1 bit)
PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
Enumeration: PTYPESelect
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
PEPNUM : Pipe Endpoint Number
bits : 16 - 19 (4 bit)
INTFRQ : Pipe Interrupt Request Frequency
bits : 24 - 31 (8 bit)
Host Pipe Configuration Register (n = 0) 0
address_offset : 0x524 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALLOC : Pipe Memory Allocate
bits : 1 - 1 (1 bit)
PBK : Pipe Banks
bits : 2 - 3 (2 bit)
Enumeration: PBKSelect
0x0 : _1_BANK
Single-bank pipe
0x1 : _2_BANK
Double-bank pipe
0x2 : _3_BANK
Triple-bank pipe
End of enumeration elements list.
PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
Enumeration: PSIZESelect
0x0 : _8_BYTE
8 bytes
0x1 : _16_BYTE
16 bytes
0x2 : _32_BYTE
32 bytes
0x3 : _64_BYTE
64 bytes
0x4 : _128_BYTE
128 bytes
0x5 : _256_BYTE
256 bytes
0x6 : _512_BYTE
512 bytes
0x7 : _1024_BYTE
1024 bytes
End of enumeration elements list.
PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
Enumeration: PTOKENSelect
0x0 : SETUP
SETUP
0x1 : IN
IN
0x2 : OUT
OUT
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 10 - 10 (1 bit)
PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
Enumeration: PTYPESelect
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
PEPNUM : Pipe Endpoint Number
bits : 16 - 19 (4 bit)
INTFRQ : Pipe Interrupt Request Frequency
bits : 24 - 31 (8 bit)
Host Pipe Status Register (n = 0) 0
address_offset : 0x530 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
SHORTPACKETI : Short Packet Interrupt
bits : 7 - 7 (1 bit)
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
Enumeration: DTSEQSelect
0 : DATA0
Data0 toggle sequence
1 : DATA1
Data1 toggle sequence
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
Enumeration: NBUSYBKSelect
0x0 : _0_BUSY
0 busy bank (all banks free)
0x1 : _1_BUSY
1 busy bank
0x2 : _2_BUSY
2 busy banks
0x3 : _3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
Enumeration: CURRBKSelect
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read/Write Allowed
bits : 16 - 16 (1 bit)
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
PBYCT : Pipe Byte Count
bits : 20 - 30 (11 bit)
Host Pipe Status Register (n = 0)
address_offset : 0x530 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
UNDERFI : Underflow Interrupt
bits : 2 - 2 (1 bit)
access : read-only
PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETI : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
Enumeration:
0 : DATA0
Data0 toggle sequence
1 : DATA1
Data1 toggle sequence
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only
Enumeration:
0x0 : 0_BUSY
0 busy bank (all banks free)
0x1 : 1_BUSY
1 busy bank
0x2 : 2_BUSY
2 busy banks
0x3 : 3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read/Write Allowed
bits : 16 - 16 (1 bit)
access : read-only
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only
PBYCT : Pipe Byte Count
bits : 20 - 30 (11 bit)
access : read-only
Host Pipe Status Register (n = 0)
address_offset : 0x530 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
UNDERFI : Underflow Interrupt
bits : 2 - 2 (1 bit)
access : read-only
PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
CRCERRI : CRC Error Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETI : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
Enumeration:
0 : DATA0
Data0 toggle sequence
1 : DATA1
Data1 toggle sequence
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only
Enumeration:
0x0 : 0_BUSY
0 busy bank (all banks free)
0x1 : 1_BUSY
1 busy bank
0x2 : 2_BUSY
2 busy banks
0x3 : 3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read/Write Allowed
bits : 16 - 16 (1 bit)
access : read-only
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only
PBYCT : Pipe Byte Count
bits : 20 - 30 (11 bit)
access : read-only
Host Pipe Status Register (n = 0) 0
address_offset : 0x534 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
SHORTPACKETI : Short Packet Interrupt
bits : 7 - 7 (1 bit)
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
Enumeration: DTSEQSelect
0 : DATA0
Data0 toggle sequence
1 : DATA1
Data1 toggle sequence
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
Enumeration: NBUSYBKSelect
0x0 : _0_BUSY
0 busy bank (all banks free)
0x1 : _1_BUSY
1 busy bank
0x2 : _2_BUSY
2 busy banks
0x3 : _3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
Enumeration: CURRBKSelect
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read/Write Allowed
bits : 16 - 16 (1 bit)
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
PBYCT : Pipe Byte Count
bits : 20 - 30 (11 bit)
Host Pipe Status Register (n = 0) 0
address_offset : 0x538 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
SHORTPACKETI : Short Packet Interrupt
bits : 7 - 7 (1 bit)
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
Enumeration: DTSEQSelect
0 : DATA0
Data0 toggle sequence
1 : DATA1
Data1 toggle sequence
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
Enumeration: NBUSYBKSelect
0x0 : _0_BUSY
0 busy bank (all banks free)
0x1 : _1_BUSY
1 busy bank
0x2 : _2_BUSY
2 busy banks
0x3 : _3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
Enumeration: CURRBKSelect
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read/Write Allowed
bits : 16 - 16 (1 bit)
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
PBYCT : Pipe Byte Count
bits : 20 - 30 (11 bit)
Host Pipe Status Register (n = 0) 0
address_offset : 0x53C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
SHORTPACKETI : Short Packet Interrupt
bits : 7 - 7 (1 bit)
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
Enumeration: DTSEQSelect
0 : DATA0
Data0 toggle sequence
1 : DATA1
Data1 toggle sequence
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
Enumeration: NBUSYBKSelect
0x0 : _0_BUSY
0 busy bank (all banks free)
0x1 : _1_BUSY
1 busy bank
0x2 : _2_BUSY
2 busy banks
0x3 : _3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
Enumeration: CURRBKSelect
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read/Write Allowed
bits : 16 - 16 (1 bit)
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
PBYCT : Pipe Byte Count
bits : 20 - 30 (11 bit)
Host Pipe Status Register (n = 0) 0
address_offset : 0x540 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
SHORTPACKETI : Short Packet Interrupt
bits : 7 - 7 (1 bit)
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
Enumeration: DTSEQSelect
0 : DATA0
Data0 toggle sequence
1 : DATA1
Data1 toggle sequence
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
Enumeration: NBUSYBKSelect
0x0 : _0_BUSY
0 busy bank (all banks free)
0x1 : _1_BUSY
1 busy bank
0x2 : _2_BUSY
2 busy banks
0x3 : _3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
Enumeration: CURRBKSelect
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read/Write Allowed
bits : 16 - 16 (1 bit)
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
PBYCT : Pipe Byte Count
bits : 20 - 30 (11 bit)
Host Pipe Status Register (n = 0) 0
address_offset : 0x544 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
SHORTPACKETI : Short Packet Interrupt
bits : 7 - 7 (1 bit)
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
Enumeration: DTSEQSelect
0 : DATA0
Data0 toggle sequence
1 : DATA1
Data1 toggle sequence
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
Enumeration: NBUSYBKSelect
0x0 : _0_BUSY
0 busy bank (all banks free)
0x1 : _1_BUSY
1 busy bank
0x2 : _2_BUSY
2 busy banks
0x3 : _3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
Enumeration: CURRBKSelect
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read/Write Allowed
bits : 16 - 16 (1 bit)
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
PBYCT : Pipe Byte Count
bits : 20 - 30 (11 bit)
Host Pipe Status Register (n = 0) 0
address_offset : 0x548 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
SHORTPACKETI : Short Packet Interrupt
bits : 7 - 7 (1 bit)
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
Enumeration: DTSEQSelect
0 : DATA0
Data0 toggle sequence
1 : DATA1
Data1 toggle sequence
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
Enumeration: NBUSYBKSelect
0x0 : _0_BUSY
0 busy bank (all banks free)
0x1 : _1_BUSY
1 busy bank
0x2 : _2_BUSY
2 busy banks
0x3 : _3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
Enumeration: CURRBKSelect
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read/Write Allowed
bits : 16 - 16 (1 bit)
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
PBYCT : Pipe Byte Count
bits : 20 - 30 (11 bit)
Host Pipe Status Register (n = 0) 0
address_offset : 0x54C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
SHORTPACKETI : Short Packet Interrupt
bits : 7 - 7 (1 bit)
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
Enumeration: DTSEQSelect
0 : DATA0
Data0 toggle sequence
1 : DATA1
Data1 toggle sequence
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
Enumeration: NBUSYBKSelect
0x0 : _0_BUSY
0 busy bank (all banks free)
0x1 : _1_BUSY
1 busy bank
0x2 : _2_BUSY
2 busy banks
0x3 : _3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
Enumeration: CURRBKSelect
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read/Write Allowed
bits : 16 - 16 (1 bit)
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
PBYCT : Pipe Byte Count
bits : 20 - 30 (11 bit)
Host Pipe Status Register (n = 0) 0
address_offset : 0x550 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
SHORTPACKETI : Short Packet Interrupt
bits : 7 - 7 (1 bit)
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
Enumeration: DTSEQSelect
0 : DATA0
Data0 toggle sequence
1 : DATA1
Data1 toggle sequence
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
Enumeration: NBUSYBKSelect
0x0 : _0_BUSY
0 busy bank (all banks free)
0x1 : _1_BUSY
1 busy bank
0x2 : _2_BUSY
2 busy banks
0x3 : _3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
Enumeration: CURRBKSelect
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read/Write Allowed
bits : 16 - 16 (1 bit)
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
PBYCT : Pipe Byte Count
bits : 20 - 30 (11 bit)
Host Pipe Status Register (n = 0) 0
address_offset : 0x554 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
SHORTPACKETI : Short Packet Interrupt
bits : 7 - 7 (1 bit)
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
Enumeration: DTSEQSelect
0 : DATA0
Data0 toggle sequence
1 : DATA1
Data1 toggle sequence
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
Enumeration: NBUSYBKSelect
0x0 : _0_BUSY
0 busy bank (all banks free)
0x1 : _1_BUSY
1 busy bank
0x2 : _2_BUSY
2 busy banks
0x3 : _3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
Enumeration: CURRBKSelect
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read/Write Allowed
bits : 16 - 16 (1 bit)
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
PBYCT : Pipe Byte Count
bits : 20 - 30 (11 bit)
Host Pipe Clear Register (n = 0) 0
address_offset : 0x560 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIC : Received IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
TXOUTIC : Transmitted OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
TXSTPIC : Transmitted SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
NAKEDIC : NAKed Interrupt Clear
bits : 4 - 4 (1 bit)
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
RXSTALLDIC : Received STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
SHORTPACKETIC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
Host Pipe Clear Register (n = 0)
address_offset : 0x560 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
RXINIC : Received IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIC : Transmitted OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
UNDERFIC : Underflow Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKEDIC : NAKed Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIC : Received STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
Host Pipe Clear Register (n = 0)
address_offset : 0x560 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
RXINIC : Received IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIC : Transmitted OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
UNDERFIC : Underflow Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKEDIC : NAKed Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
CRCERRIC : CRC Error Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
Host Pipe Clear Register (n = 0) 0
address_offset : 0x564 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIC : Received IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
TXOUTIC : Transmitted OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
TXSTPIC : Transmitted SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
NAKEDIC : NAKed Interrupt Clear
bits : 4 - 4 (1 bit)
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
RXSTALLDIC : Received STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
SHORTPACKETIC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
Host Pipe Clear Register (n = 0) 0
address_offset : 0x568 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIC : Received IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
TXOUTIC : Transmitted OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
TXSTPIC : Transmitted SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
NAKEDIC : NAKed Interrupt Clear
bits : 4 - 4 (1 bit)
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
RXSTALLDIC : Received STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
SHORTPACKETIC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
Host Pipe Clear Register (n = 0) 0
address_offset : 0x56C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIC : Received IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
TXOUTIC : Transmitted OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
TXSTPIC : Transmitted SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
NAKEDIC : NAKed Interrupt Clear
bits : 4 - 4 (1 bit)
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
RXSTALLDIC : Received STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
SHORTPACKETIC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
Host Pipe Clear Register (n = 0) 0
address_offset : 0x570 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIC : Received IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
TXOUTIC : Transmitted OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
TXSTPIC : Transmitted SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
NAKEDIC : NAKed Interrupt Clear
bits : 4 - 4 (1 bit)
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
RXSTALLDIC : Received STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
SHORTPACKETIC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
Host Pipe Clear Register (n = 0) 0
address_offset : 0x574 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIC : Received IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
TXOUTIC : Transmitted OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
TXSTPIC : Transmitted SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
NAKEDIC : NAKed Interrupt Clear
bits : 4 - 4 (1 bit)
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
RXSTALLDIC : Received STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
SHORTPACKETIC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
Host Pipe Clear Register (n = 0) 0
address_offset : 0x578 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIC : Received IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
TXOUTIC : Transmitted OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
TXSTPIC : Transmitted SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
NAKEDIC : NAKed Interrupt Clear
bits : 4 - 4 (1 bit)
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
RXSTALLDIC : Received STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
SHORTPACKETIC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
Host Pipe Clear Register (n = 0) 0
address_offset : 0x57C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIC : Received IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
TXOUTIC : Transmitted OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
TXSTPIC : Transmitted SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
NAKEDIC : NAKed Interrupt Clear
bits : 4 - 4 (1 bit)
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
RXSTALLDIC : Received STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
SHORTPACKETIC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
Host Pipe Clear Register (n = 0) 0
address_offset : 0x580 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIC : Received IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
TXOUTIC : Transmitted OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
TXSTPIC : Transmitted SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
NAKEDIC : NAKed Interrupt Clear
bits : 4 - 4 (1 bit)
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
RXSTALLDIC : Received STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
SHORTPACKETIC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
Host Pipe Clear Register (n = 0) 0
address_offset : 0x584 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIC : Received IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
TXOUTIC : Transmitted OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
TXSTPIC : Transmitted SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
NAKEDIC : NAKed Interrupt Clear
bits : 4 - 4 (1 bit)
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
RXSTALLDIC : Received STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
SHORTPACKETIC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
Host Pipe Set Register (n = 0) 0
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIS : Received IN Data Interrupt Set
bits : 0 - 0 (1 bit)
TXOUTIS : Transmitted OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
TXSTPIS : Transmitted SETUP Interrupt Set
bits : 2 - 2 (1 bit)
PERRIS : Pipe Error Interrupt Set
bits : 3 - 3 (1 bit)
NAKEDIS : NAKed Interrupt Set
bits : 4 - 4 (1 bit)
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
RXSTALLDIS : Received STALLed Interrupt Set
bits : 6 - 6 (1 bit)
SHORTPACKETIS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
NBUSYBKS : Number of Busy Banks Set
bits : 12 - 12 (1 bit)
Host Pipe Set Register (n = 0)
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
RXINIS : Received IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIS : Transmitted OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only
UNDERFIS : Underflow Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only
PERRIS : Pipe Error Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only
NAKEDIS : NAKed Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIS : Received STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKS : Number of Busy Banks Set
bits : 12 - 12 (1 bit)
access : write-only
Host Pipe Set Register (n = 0)
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
RXINIS : Received IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIS : Transmitted OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only
UNDERFIS : Underflow Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only
PERRIS : Pipe Error Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only
NAKEDIS : NAKed Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only
CRCERRIS : CRC Error Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKS : Number of Busy Banks Set
bits : 12 - 12 (1 bit)
access : write-only
Host Pipe Set Register (n = 0) 0
address_offset : 0x594 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIS : Received IN Data Interrupt Set
bits : 0 - 0 (1 bit)
TXOUTIS : Transmitted OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
TXSTPIS : Transmitted SETUP Interrupt Set
bits : 2 - 2 (1 bit)
PERRIS : Pipe Error Interrupt Set
bits : 3 - 3 (1 bit)
NAKEDIS : NAKed Interrupt Set
bits : 4 - 4 (1 bit)
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
RXSTALLDIS : Received STALLed Interrupt Set
bits : 6 - 6 (1 bit)
SHORTPACKETIS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
NBUSYBKS : Number of Busy Banks Set
bits : 12 - 12 (1 bit)
Host Pipe Set Register (n = 0) 0
address_offset : 0x598 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIS : Received IN Data Interrupt Set
bits : 0 - 0 (1 bit)
TXOUTIS : Transmitted OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
TXSTPIS : Transmitted SETUP Interrupt Set
bits : 2 - 2 (1 bit)
PERRIS : Pipe Error Interrupt Set
bits : 3 - 3 (1 bit)
NAKEDIS : NAKed Interrupt Set
bits : 4 - 4 (1 bit)
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
RXSTALLDIS : Received STALLed Interrupt Set
bits : 6 - 6 (1 bit)
SHORTPACKETIS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
NBUSYBKS : Number of Busy Banks Set
bits : 12 - 12 (1 bit)
Host Pipe Set Register (n = 0) 0
address_offset : 0x59C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIS : Received IN Data Interrupt Set
bits : 0 - 0 (1 bit)
TXOUTIS : Transmitted OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
TXSTPIS : Transmitted SETUP Interrupt Set
bits : 2 - 2 (1 bit)
PERRIS : Pipe Error Interrupt Set
bits : 3 - 3 (1 bit)
NAKEDIS : NAKed Interrupt Set
bits : 4 - 4 (1 bit)
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
RXSTALLDIS : Received STALLed Interrupt Set
bits : 6 - 6 (1 bit)
SHORTPACKETIS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
NBUSYBKS : Number of Busy Banks Set
bits : 12 - 12 (1 bit)
Host Pipe Set Register (n = 0) 0
address_offset : 0x5A0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIS : Received IN Data Interrupt Set
bits : 0 - 0 (1 bit)
TXOUTIS : Transmitted OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
TXSTPIS : Transmitted SETUP Interrupt Set
bits : 2 - 2 (1 bit)
PERRIS : Pipe Error Interrupt Set
bits : 3 - 3 (1 bit)
NAKEDIS : NAKed Interrupt Set
bits : 4 - 4 (1 bit)
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
RXSTALLDIS : Received STALLed Interrupt Set
bits : 6 - 6 (1 bit)
SHORTPACKETIS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
NBUSYBKS : Number of Busy Banks Set
bits : 12 - 12 (1 bit)
Host Pipe Set Register (n = 0) 0
address_offset : 0x5A4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIS : Received IN Data Interrupt Set
bits : 0 - 0 (1 bit)
TXOUTIS : Transmitted OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
TXSTPIS : Transmitted SETUP Interrupt Set
bits : 2 - 2 (1 bit)
PERRIS : Pipe Error Interrupt Set
bits : 3 - 3 (1 bit)
NAKEDIS : NAKed Interrupt Set
bits : 4 - 4 (1 bit)
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
RXSTALLDIS : Received STALLed Interrupt Set
bits : 6 - 6 (1 bit)
SHORTPACKETIS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
NBUSYBKS : Number of Busy Banks Set
bits : 12 - 12 (1 bit)
Host Pipe Set Register (n = 0) 0
address_offset : 0x5A8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIS : Received IN Data Interrupt Set
bits : 0 - 0 (1 bit)
TXOUTIS : Transmitted OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
TXSTPIS : Transmitted SETUP Interrupt Set
bits : 2 - 2 (1 bit)
PERRIS : Pipe Error Interrupt Set
bits : 3 - 3 (1 bit)
NAKEDIS : NAKed Interrupt Set
bits : 4 - 4 (1 bit)
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
RXSTALLDIS : Received STALLed Interrupt Set
bits : 6 - 6 (1 bit)
SHORTPACKETIS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
NBUSYBKS : Number of Busy Banks Set
bits : 12 - 12 (1 bit)
Host Pipe Set Register (n = 0) 0
address_offset : 0x5AC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIS : Received IN Data Interrupt Set
bits : 0 - 0 (1 bit)
TXOUTIS : Transmitted OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
TXSTPIS : Transmitted SETUP Interrupt Set
bits : 2 - 2 (1 bit)
PERRIS : Pipe Error Interrupt Set
bits : 3 - 3 (1 bit)
NAKEDIS : NAKed Interrupt Set
bits : 4 - 4 (1 bit)
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
RXSTALLDIS : Received STALLed Interrupt Set
bits : 6 - 6 (1 bit)
SHORTPACKETIS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
NBUSYBKS : Number of Busy Banks Set
bits : 12 - 12 (1 bit)
Host Pipe Set Register (n = 0) 0
address_offset : 0x5B0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIS : Received IN Data Interrupt Set
bits : 0 - 0 (1 bit)
TXOUTIS : Transmitted OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
TXSTPIS : Transmitted SETUP Interrupt Set
bits : 2 - 2 (1 bit)
PERRIS : Pipe Error Interrupt Set
bits : 3 - 3 (1 bit)
NAKEDIS : NAKed Interrupt Set
bits : 4 - 4 (1 bit)
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
RXSTALLDIS : Received STALLed Interrupt Set
bits : 6 - 6 (1 bit)
SHORTPACKETIS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
NBUSYBKS : Number of Busy Banks Set
bits : 12 - 12 (1 bit)
Host Pipe Set Register (n = 0) 0
address_offset : 0x5B4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIS : Received IN Data Interrupt Set
bits : 0 - 0 (1 bit)
TXOUTIS : Transmitted OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
TXSTPIS : Transmitted SETUP Interrupt Set
bits : 2 - 2 (1 bit)
PERRIS : Pipe Error Interrupt Set
bits : 3 - 3 (1 bit)
NAKEDIS : NAKed Interrupt Set
bits : 4 - 4 (1 bit)
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
RXSTALLDIS : Received STALLed Interrupt Set
bits : 6 - 6 (1 bit)
SHORTPACKETIS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
NBUSYBKS : Number of Busy Banks Set
bits : 12 - 12 (1 bit)
Host Pipe Mask Register (n = 0) 0
address_offset : 0x5C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINE : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
TXOUTE : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
TXSTPE : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
PERRE : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
NAKEDE : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
OVERFIE : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
RXSTALLDE : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
SHORTPACKETIE : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
PDISHDMA : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
Host Pipe Mask Register (n = 0)
address_offset : 0x5C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
RXINE : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only
TXOUTE : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only
UNDERFIE : Underflow Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only
PERRE : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only
NAKEDE : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only
OVERFIE : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDE : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETIE : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-only
NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
PDISHDMA : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : read-only
PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only
Host Pipe Mask Register (n = 0)
address_offset : 0x5C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
RXINE : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only
TXOUTE : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only
UNDERFIE : Underflow Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only
PERRE : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only
NAKEDE : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only
OVERFIE : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only
CRCERRE : CRC Error Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETIE : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-only
NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
PDISHDMA : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : read-only
PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only
Host Pipe Mask Register (n = 0) 0
address_offset : 0x5C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINE : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
TXOUTE : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
TXSTPE : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
PERRE : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
NAKEDE : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
OVERFIE : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
RXSTALLDE : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
SHORTPACKETIE : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
PDISHDMA : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
Host Pipe Mask Register (n = 0) 0
address_offset : 0x5C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINE : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
TXOUTE : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
TXSTPE : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
PERRE : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
NAKEDE : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
OVERFIE : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
RXSTALLDE : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
SHORTPACKETIE : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
PDISHDMA : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
Host Pipe Mask Register (n = 0) 0
address_offset : 0x5CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINE : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
TXOUTE : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
TXSTPE : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
PERRE : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
NAKEDE : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
OVERFIE : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
RXSTALLDE : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
SHORTPACKETIE : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
PDISHDMA : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
Host Pipe Mask Register (n = 0) 0
address_offset : 0x5D0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINE : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
TXOUTE : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
TXSTPE : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
PERRE : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
NAKEDE : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
OVERFIE : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
RXSTALLDE : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
SHORTPACKETIE : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
PDISHDMA : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
Host Pipe Mask Register (n = 0) 0
address_offset : 0x5D4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINE : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
TXOUTE : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
TXSTPE : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
PERRE : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
NAKEDE : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
OVERFIE : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
RXSTALLDE : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
SHORTPACKETIE : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
PDISHDMA : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
Host Pipe Mask Register (n = 0) 0
address_offset : 0x5D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINE : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
TXOUTE : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
TXSTPE : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
PERRE : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
NAKEDE : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
OVERFIE : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
RXSTALLDE : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
SHORTPACKETIE : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
PDISHDMA : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
Host Pipe Mask Register (n = 0) 0
address_offset : 0x5DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINE : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
TXOUTE : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
TXSTPE : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
PERRE : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
NAKEDE : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
OVERFIE : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
RXSTALLDE : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
SHORTPACKETIE : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
PDISHDMA : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
Host Pipe Mask Register (n = 0) 0
address_offset : 0x5E0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINE : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
TXOUTE : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
TXSTPE : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
PERRE : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
NAKEDE : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
OVERFIE : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
RXSTALLDE : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
SHORTPACKETIE : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
PDISHDMA : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
Host Pipe Mask Register (n = 0) 0
address_offset : 0x5E4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINE : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
TXOUTE : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
TXSTPE : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
PERRE : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
NAKEDE : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
OVERFIE : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
RXSTALLDE : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
SHORTPACKETIE : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
PDISHDMA : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
Host Pipe Enable Register (n = 0) 0
address_offset : 0x5F0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINES : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
TXOUTES : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
TXSTPES : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
PERRES : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
NAKEDES : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
OVERFIES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
RXSTALLDES : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
SHORTPACKETIES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
NBUSYBKES : Number of Busy Banks Enable
bits : 12 - 12 (1 bit)
PDISHDMAS : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
PFREEZES : Pipe Freeze Enable
bits : 17 - 17 (1 bit)
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
Host Pipe Enable Register (n = 0)
address_offset : 0x5F0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
RXINES : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
TXOUTES : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
UNDERFIES : Underflow Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
PERRES : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
NAKEDES : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
OVERFIES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDES : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKES : Number of Busy Banks Enable
bits : 12 - 12 (1 bit)
access : write-only
PDISHDMAS : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only
PFREEZES : Pipe Freeze Enable
bits : 17 - 17 (1 bit)
access : write-only
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only
Host Pipe Enable Register (n = 0)
address_offset : 0x5F0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
RXINES : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
TXOUTES : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
UNDERFIES : Underflow Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
PERRES : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
NAKEDES : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
OVERFIES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
CRCERRES : CRC Error Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKES : Number of Busy Banks Enable
bits : 12 - 12 (1 bit)
access : write-only
PDISHDMAS : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only
PFREEZES : Pipe Freeze Enable
bits : 17 - 17 (1 bit)
access : write-only
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only
Host Pipe Enable Register (n = 0) 0
address_offset : 0x5F4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINES : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
TXOUTES : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
TXSTPES : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
PERRES : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
NAKEDES : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
OVERFIES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
RXSTALLDES : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
SHORTPACKETIES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
NBUSYBKES : Number of Busy Banks Enable
bits : 12 - 12 (1 bit)
PDISHDMAS : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
PFREEZES : Pipe Freeze Enable
bits : 17 - 17 (1 bit)
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
Host Pipe Enable Register (n = 0) 0
address_offset : 0x5F8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINES : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
TXOUTES : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
TXSTPES : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
PERRES : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
NAKEDES : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
OVERFIES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
RXSTALLDES : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
SHORTPACKETIES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
NBUSYBKES : Number of Busy Banks Enable
bits : 12 - 12 (1 bit)
PDISHDMAS : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
PFREEZES : Pipe Freeze Enable
bits : 17 - 17 (1 bit)
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
Host Pipe Enable Register (n = 0) 0
address_offset : 0x5FC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINES : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
TXOUTES : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
TXSTPES : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
PERRES : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
NAKEDES : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
OVERFIES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
RXSTALLDES : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
SHORTPACKETIES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
NBUSYBKES : Number of Busy Banks Enable
bits : 12 - 12 (1 bit)
PDISHDMAS : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
PFREEZES : Pipe Freeze Enable
bits : 17 - 17 (1 bit)
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
Host Pipe Enable Register (n = 0) 0
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINES : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
TXOUTES : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
TXSTPES : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
PERRES : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
NAKEDES : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
OVERFIES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
RXSTALLDES : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
SHORTPACKETIES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
NBUSYBKES : Number of Busy Banks Enable
bits : 12 - 12 (1 bit)
PDISHDMAS : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
PFREEZES : Pipe Freeze Enable
bits : 17 - 17 (1 bit)
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
Host Pipe Enable Register (n = 0) 0
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINES : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
TXOUTES : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
TXSTPES : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
PERRES : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
NAKEDES : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
OVERFIES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
RXSTALLDES : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
SHORTPACKETIES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
NBUSYBKES : Number of Busy Banks Enable
bits : 12 - 12 (1 bit)
PDISHDMAS : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
PFREEZES : Pipe Freeze Enable
bits : 17 - 17 (1 bit)
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
Host Pipe Enable Register (n = 0) 0
address_offset : 0x608 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINES : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
TXOUTES : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
TXSTPES : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
PERRES : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
NAKEDES : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
OVERFIES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
RXSTALLDES : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
SHORTPACKETIES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
NBUSYBKES : Number of Busy Banks Enable
bits : 12 - 12 (1 bit)
PDISHDMAS : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
PFREEZES : Pipe Freeze Enable
bits : 17 - 17 (1 bit)
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
Host Pipe Enable Register (n = 0) 0
address_offset : 0x60C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINES : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
TXOUTES : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
TXSTPES : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
PERRES : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
NAKEDES : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
OVERFIES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
RXSTALLDES : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
SHORTPACKETIES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
NBUSYBKES : Number of Busy Banks Enable
bits : 12 - 12 (1 bit)
PDISHDMAS : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
PFREEZES : Pipe Freeze Enable
bits : 17 - 17 (1 bit)
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
Host Pipe Enable Register (n = 0) 0
address_offset : 0x610 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINES : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
TXOUTES : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
TXSTPES : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
PERRES : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
NAKEDES : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
OVERFIES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
RXSTALLDES : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
SHORTPACKETIES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
NBUSYBKES : Number of Busy Banks Enable
bits : 12 - 12 (1 bit)
PDISHDMAS : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
PFREEZES : Pipe Freeze Enable
bits : 17 - 17 (1 bit)
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
Host Pipe Enable Register (n = 0) 0
address_offset : 0x614 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINES : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
TXOUTES : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
TXSTPES : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
PERRES : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
NAKEDES : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
OVERFIES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
RXSTALLDES : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
SHORTPACKETIES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
NBUSYBKES : Number of Busy Banks Enable
bits : 12 - 12 (1 bit)
PDISHDMAS : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
PFREEZES : Pipe Freeze Enable
bits : 17 - 17 (1 bit)
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
Host Pipe Disable Register (n = 0) 0
address_offset : 0x620 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINEC : Received IN Data Interrupt Disable
bits : 0 - 0 (1 bit)
TXOUTEC : Transmitted OUT Data Interrupt Disable
bits : 1 - 1 (1 bit)
TXSTPEC : Transmitted SETUP Interrupt Disable
bits : 2 - 2 (1 bit)
PERREC : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
NAKEDEC : NAKed Interrupt Disable
bits : 4 - 4 (1 bit)
OVERFIEC : Overflow Interrupt Disable
bits : 5 - 5 (1 bit)
RXSTALLDEC : Received STALLed Interrupt Disable
bits : 6 - 6 (1 bit)
SHORTPACKETIEC : Short Packet Interrupt Disable
bits : 7 - 7 (1 bit)
NBUSYBKEC : Number of Busy Banks Disable
bits : 12 - 12 (1 bit)
FIFOCONC : FIFO Control Disable
bits : 14 - 14 (1 bit)
PDISHDMAC : Pipe Interrupts Disable HDMA Request Disable
bits : 16 - 16 (1 bit)
PFREEZEC : Pipe Freeze Disable
bits : 17 - 17 (1 bit)
Host Pipe Disable Register (n = 0)
address_offset : 0x620 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
RXINEC : Received IN Data Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
TXOUTEC : Transmitted OUT Data Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
UNDERFIEC : Underflow Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
PERREC : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only
NAKEDEC : NAKed Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only
OVERFIEC : Overflow Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDEC : Received STALLed Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIEC : Short Packet Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKEC : Number of Busy Banks Disable
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFO Control Disable
bits : 14 - 14 (1 bit)
access : write-only
PDISHDMAC : Pipe Interrupts Disable HDMA Request Disable
bits : 16 - 16 (1 bit)
access : write-only
PFREEZEC : Pipe Freeze Disable
bits : 17 - 17 (1 bit)
access : write-only
Host Pipe Disable Register (n = 0)
address_offset : 0x620 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
RXINEC : Received IN Data Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
TXOUTEC : Transmitted OUT Data Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
UNDERFIEC : Underflow Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
PERREC : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only
NAKEDEC : NAKed Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only
OVERFIEC : Overflow Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only
CRCERREC : CRC Error Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIEC : Short Packet Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKEC : Number of Busy Banks Disable
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFO Control Disable
bits : 14 - 14 (1 bit)
access : write-only
PDISHDMAC : Pipe Interrupts Disable HDMA Request Disable
bits : 16 - 16 (1 bit)
access : write-only
PFREEZEC : Pipe Freeze Disable
bits : 17 - 17 (1 bit)
access : write-only
Host Pipe Disable Register (n = 0) 0
address_offset : 0x624 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINEC : Received IN Data Interrupt Disable
bits : 0 - 0 (1 bit)
TXOUTEC : Transmitted OUT Data Interrupt Disable
bits : 1 - 1 (1 bit)
TXSTPEC : Transmitted SETUP Interrupt Disable
bits : 2 - 2 (1 bit)
PERREC : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
NAKEDEC : NAKed Interrupt Disable
bits : 4 - 4 (1 bit)
OVERFIEC : Overflow Interrupt Disable
bits : 5 - 5 (1 bit)
RXSTALLDEC : Received STALLed Interrupt Disable
bits : 6 - 6 (1 bit)
SHORTPACKETIEC : Short Packet Interrupt Disable
bits : 7 - 7 (1 bit)
NBUSYBKEC : Number of Busy Banks Disable
bits : 12 - 12 (1 bit)
FIFOCONC : FIFO Control Disable
bits : 14 - 14 (1 bit)
PDISHDMAC : Pipe Interrupts Disable HDMA Request Disable
bits : 16 - 16 (1 bit)
PFREEZEC : Pipe Freeze Disable
bits : 17 - 17 (1 bit)
Host Pipe Disable Register (n = 0) 0
address_offset : 0x628 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINEC : Received IN Data Interrupt Disable
bits : 0 - 0 (1 bit)
TXOUTEC : Transmitted OUT Data Interrupt Disable
bits : 1 - 1 (1 bit)
TXSTPEC : Transmitted SETUP Interrupt Disable
bits : 2 - 2 (1 bit)
PERREC : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
NAKEDEC : NAKed Interrupt Disable
bits : 4 - 4 (1 bit)
OVERFIEC : Overflow Interrupt Disable
bits : 5 - 5 (1 bit)
RXSTALLDEC : Received STALLed Interrupt Disable
bits : 6 - 6 (1 bit)
SHORTPACKETIEC : Short Packet Interrupt Disable
bits : 7 - 7 (1 bit)
NBUSYBKEC : Number of Busy Banks Disable
bits : 12 - 12 (1 bit)
FIFOCONC : FIFO Control Disable
bits : 14 - 14 (1 bit)
PDISHDMAC : Pipe Interrupts Disable HDMA Request Disable
bits : 16 - 16 (1 bit)
PFREEZEC : Pipe Freeze Disable
bits : 17 - 17 (1 bit)
Host Pipe Disable Register (n = 0) 0
address_offset : 0x62C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINEC : Received IN Data Interrupt Disable
bits : 0 - 0 (1 bit)
TXOUTEC : Transmitted OUT Data Interrupt Disable
bits : 1 - 1 (1 bit)
TXSTPEC : Transmitted SETUP Interrupt Disable
bits : 2 - 2 (1 bit)
PERREC : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
NAKEDEC : NAKed Interrupt Disable
bits : 4 - 4 (1 bit)
OVERFIEC : Overflow Interrupt Disable
bits : 5 - 5 (1 bit)
RXSTALLDEC : Received STALLed Interrupt Disable
bits : 6 - 6 (1 bit)
SHORTPACKETIEC : Short Packet Interrupt Disable
bits : 7 - 7 (1 bit)
NBUSYBKEC : Number of Busy Banks Disable
bits : 12 - 12 (1 bit)
FIFOCONC : FIFO Control Disable
bits : 14 - 14 (1 bit)
PDISHDMAC : Pipe Interrupts Disable HDMA Request Disable
bits : 16 - 16 (1 bit)
PFREEZEC : Pipe Freeze Disable
bits : 17 - 17 (1 bit)
Host Pipe Disable Register (n = 0) 0
address_offset : 0x630 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINEC : Received IN Data Interrupt Disable
bits : 0 - 0 (1 bit)
TXOUTEC : Transmitted OUT Data Interrupt Disable
bits : 1 - 1 (1 bit)
TXSTPEC : Transmitted SETUP Interrupt Disable
bits : 2 - 2 (1 bit)
PERREC : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
NAKEDEC : NAKed Interrupt Disable
bits : 4 - 4 (1 bit)
OVERFIEC : Overflow Interrupt Disable
bits : 5 - 5 (1 bit)
RXSTALLDEC : Received STALLed Interrupt Disable
bits : 6 - 6 (1 bit)
SHORTPACKETIEC : Short Packet Interrupt Disable
bits : 7 - 7 (1 bit)
NBUSYBKEC : Number of Busy Banks Disable
bits : 12 - 12 (1 bit)
FIFOCONC : FIFO Control Disable
bits : 14 - 14 (1 bit)
PDISHDMAC : Pipe Interrupts Disable HDMA Request Disable
bits : 16 - 16 (1 bit)
PFREEZEC : Pipe Freeze Disable
bits : 17 - 17 (1 bit)
Host Pipe Disable Register (n = 0) 0
address_offset : 0x634 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINEC : Received IN Data Interrupt Disable
bits : 0 - 0 (1 bit)
TXOUTEC : Transmitted OUT Data Interrupt Disable
bits : 1 - 1 (1 bit)
TXSTPEC : Transmitted SETUP Interrupt Disable
bits : 2 - 2 (1 bit)
PERREC : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
NAKEDEC : NAKed Interrupt Disable
bits : 4 - 4 (1 bit)
OVERFIEC : Overflow Interrupt Disable
bits : 5 - 5 (1 bit)
RXSTALLDEC : Received STALLed Interrupt Disable
bits : 6 - 6 (1 bit)
SHORTPACKETIEC : Short Packet Interrupt Disable
bits : 7 - 7 (1 bit)
NBUSYBKEC : Number of Busy Banks Disable
bits : 12 - 12 (1 bit)
FIFOCONC : FIFO Control Disable
bits : 14 - 14 (1 bit)
PDISHDMAC : Pipe Interrupts Disable HDMA Request Disable
bits : 16 - 16 (1 bit)
PFREEZEC : Pipe Freeze Disable
bits : 17 - 17 (1 bit)
Host Pipe Disable Register (n = 0) 0
address_offset : 0x638 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINEC : Received IN Data Interrupt Disable
bits : 0 - 0 (1 bit)
TXOUTEC : Transmitted OUT Data Interrupt Disable
bits : 1 - 1 (1 bit)
TXSTPEC : Transmitted SETUP Interrupt Disable
bits : 2 - 2 (1 bit)
PERREC : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
NAKEDEC : NAKed Interrupt Disable
bits : 4 - 4 (1 bit)
OVERFIEC : Overflow Interrupt Disable
bits : 5 - 5 (1 bit)
RXSTALLDEC : Received STALLed Interrupt Disable
bits : 6 - 6 (1 bit)
SHORTPACKETIEC : Short Packet Interrupt Disable
bits : 7 - 7 (1 bit)
NBUSYBKEC : Number of Busy Banks Disable
bits : 12 - 12 (1 bit)
FIFOCONC : FIFO Control Disable
bits : 14 - 14 (1 bit)
PDISHDMAC : Pipe Interrupts Disable HDMA Request Disable
bits : 16 - 16 (1 bit)
PFREEZEC : Pipe Freeze Disable
bits : 17 - 17 (1 bit)
Host Pipe Disable Register (n = 0) 0
address_offset : 0x63C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINEC : Received IN Data Interrupt Disable
bits : 0 - 0 (1 bit)
TXOUTEC : Transmitted OUT Data Interrupt Disable
bits : 1 - 1 (1 bit)
TXSTPEC : Transmitted SETUP Interrupt Disable
bits : 2 - 2 (1 bit)
PERREC : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
NAKEDEC : NAKed Interrupt Disable
bits : 4 - 4 (1 bit)
OVERFIEC : Overflow Interrupt Disable
bits : 5 - 5 (1 bit)
RXSTALLDEC : Received STALLed Interrupt Disable
bits : 6 - 6 (1 bit)
SHORTPACKETIEC : Short Packet Interrupt Disable
bits : 7 - 7 (1 bit)
NBUSYBKEC : Number of Busy Banks Disable
bits : 12 - 12 (1 bit)
FIFOCONC : FIFO Control Disable
bits : 14 - 14 (1 bit)
PDISHDMAC : Pipe Interrupts Disable HDMA Request Disable
bits : 16 - 16 (1 bit)
PFREEZEC : Pipe Freeze Disable
bits : 17 - 17 (1 bit)
Host Pipe Disable Register (n = 0) 0
address_offset : 0x640 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINEC : Received IN Data Interrupt Disable
bits : 0 - 0 (1 bit)
TXOUTEC : Transmitted OUT Data Interrupt Disable
bits : 1 - 1 (1 bit)
TXSTPEC : Transmitted SETUP Interrupt Disable
bits : 2 - 2 (1 bit)
PERREC : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
NAKEDEC : NAKed Interrupt Disable
bits : 4 - 4 (1 bit)
OVERFIEC : Overflow Interrupt Disable
bits : 5 - 5 (1 bit)
RXSTALLDEC : Received STALLed Interrupt Disable
bits : 6 - 6 (1 bit)
SHORTPACKETIEC : Short Packet Interrupt Disable
bits : 7 - 7 (1 bit)
NBUSYBKEC : Number of Busy Banks Disable
bits : 12 - 12 (1 bit)
FIFOCONC : FIFO Control Disable
bits : 14 - 14 (1 bit)
PDISHDMAC : Pipe Interrupts Disable HDMA Request Disable
bits : 16 - 16 (1 bit)
PFREEZEC : Pipe Freeze Disable
bits : 17 - 17 (1 bit)
Host Pipe Disable Register (n = 0) 0
address_offset : 0x644 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINEC : Received IN Data Interrupt Disable
bits : 0 - 0 (1 bit)
TXOUTEC : Transmitted OUT Data Interrupt Disable
bits : 1 - 1 (1 bit)
TXSTPEC : Transmitted SETUP Interrupt Disable
bits : 2 - 2 (1 bit)
PERREC : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
NAKEDEC : NAKed Interrupt Disable
bits : 4 - 4 (1 bit)
OVERFIEC : Overflow Interrupt Disable
bits : 5 - 5 (1 bit)
RXSTALLDEC : Received STALLed Interrupt Disable
bits : 6 - 6 (1 bit)
SHORTPACKETIEC : Short Packet Interrupt Disable
bits : 7 - 7 (1 bit)
NBUSYBKEC : Number of Busy Banks Disable
bits : 12 - 12 (1 bit)
FIFOCONC : FIFO Control Disable
bits : 14 - 14 (1 bit)
PDISHDMAC : Pipe Interrupts Disable HDMA Request Disable
bits : 16 - 16 (1 bit)
PFREEZEC : Pipe Freeze Disable
bits : 17 - 17 (1 bit)
Host Pipe IN Request Register (n = 0) 0
address_offset : 0x650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
Host Pipe IN Request Register (n = 0) 0
address_offset : 0x654 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
Host Pipe IN Request Register (n = 0) 0
address_offset : 0x658 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
Host Pipe IN Request Register (n = 0) 0
address_offset : 0x65C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
Host Pipe IN Request Register (n = 0) 0
address_offset : 0x660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
Host Pipe IN Request Register (n = 0) 0
address_offset : 0x664 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
Host Pipe IN Request Register (n = 0) 0
address_offset : 0x668 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
Host Pipe IN Request Register (n = 0) 0
address_offset : 0x66C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
Host Pipe IN Request Register (n = 0) 0
address_offset : 0x670 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
Host Pipe IN Request Register (n = 0) 0
address_offset : 0x674 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
Host Pipe Error Register (n = 0) 0
address_offset : 0x680 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATATGL : Data Toggle Error
bits : 0 - 0 (1 bit)
DATAPID : Data PID Error
bits : 1 - 1 (1 bit)
PID : Data PID Error
bits : 2 - 2 (1 bit)
TIMEOUT : Time-Out Error
bits : 3 - 3 (1 bit)
CRC16 : CRC16 Error
bits : 4 - 4 (1 bit)
COUNTER : Error Counter
bits : 5 - 6 (2 bit)
Host Pipe Error Register (n = 0) 0
address_offset : 0x684 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATATGL : Data Toggle Error
bits : 0 - 0 (1 bit)
DATAPID : Data PID Error
bits : 1 - 1 (1 bit)
PID : Data PID Error
bits : 2 - 2 (1 bit)
TIMEOUT : Time-Out Error
bits : 3 - 3 (1 bit)
CRC16 : CRC16 Error
bits : 4 - 4 (1 bit)
COUNTER : Error Counter
bits : 5 - 6 (2 bit)
Host Pipe Error Register (n = 0) 0
address_offset : 0x688 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATATGL : Data Toggle Error
bits : 0 - 0 (1 bit)
DATAPID : Data PID Error
bits : 1 - 1 (1 bit)
PID : Data PID Error
bits : 2 - 2 (1 bit)
TIMEOUT : Time-Out Error
bits : 3 - 3 (1 bit)
CRC16 : CRC16 Error
bits : 4 - 4 (1 bit)
COUNTER : Error Counter
bits : 5 - 6 (2 bit)
Host Pipe Error Register (n = 0) 0
address_offset : 0x68C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATATGL : Data Toggle Error
bits : 0 - 0 (1 bit)
DATAPID : Data PID Error
bits : 1 - 1 (1 bit)
PID : Data PID Error
bits : 2 - 2 (1 bit)
TIMEOUT : Time-Out Error
bits : 3 - 3 (1 bit)
CRC16 : CRC16 Error
bits : 4 - 4 (1 bit)
COUNTER : Error Counter
bits : 5 - 6 (2 bit)
Host Pipe Error Register (n = 0) 0
address_offset : 0x690 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATATGL : Data Toggle Error
bits : 0 - 0 (1 bit)
DATAPID : Data PID Error
bits : 1 - 1 (1 bit)
PID : Data PID Error
bits : 2 - 2 (1 bit)
TIMEOUT : Time-Out Error
bits : 3 - 3 (1 bit)
CRC16 : CRC16 Error
bits : 4 - 4 (1 bit)
COUNTER : Error Counter
bits : 5 - 6 (2 bit)
Host Pipe Error Register (n = 0) 0
address_offset : 0x694 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATATGL : Data Toggle Error
bits : 0 - 0 (1 bit)
DATAPID : Data PID Error
bits : 1 - 1 (1 bit)
PID : Data PID Error
bits : 2 - 2 (1 bit)
TIMEOUT : Time-Out Error
bits : 3 - 3 (1 bit)
CRC16 : CRC16 Error
bits : 4 - 4 (1 bit)
COUNTER : Error Counter
bits : 5 - 6 (2 bit)
Host Pipe Error Register (n = 0) 0
address_offset : 0x698 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATATGL : Data Toggle Error
bits : 0 - 0 (1 bit)
DATAPID : Data PID Error
bits : 1 - 1 (1 bit)
PID : Data PID Error
bits : 2 - 2 (1 bit)
TIMEOUT : Time-Out Error
bits : 3 - 3 (1 bit)
CRC16 : CRC16 Error
bits : 4 - 4 (1 bit)
COUNTER : Error Counter
bits : 5 - 6 (2 bit)
Host Pipe Error Register (n = 0) 0
address_offset : 0x69C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATATGL : Data Toggle Error
bits : 0 - 0 (1 bit)
DATAPID : Data PID Error
bits : 1 - 1 (1 bit)
PID : Data PID Error
bits : 2 - 2 (1 bit)
TIMEOUT : Time-Out Error
bits : 3 - 3 (1 bit)
CRC16 : CRC16 Error
bits : 4 - 4 (1 bit)
COUNTER : Error Counter
bits : 5 - 6 (2 bit)
Host Pipe Error Register (n = 0) 0
address_offset : 0x6A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATATGL : Data Toggle Error
bits : 0 - 0 (1 bit)
DATAPID : Data PID Error
bits : 1 - 1 (1 bit)
PID : Data PID Error
bits : 2 - 2 (1 bit)
TIMEOUT : Time-Out Error
bits : 3 - 3 (1 bit)
CRC16 : CRC16 Error
bits : 4 - 4 (1 bit)
COUNTER : Error Counter
bits : 5 - 6 (2 bit)
Host Pipe Error Register (n = 0) 0
address_offset : 0x6A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATATGL : Data Toggle Error
bits : 0 - 0 (1 bit)
DATAPID : Data PID Error
bits : 1 - 1 (1 bit)
PID : Data PID Error
bits : 2 - 2 (1 bit)
TIMEOUT : Time-Out Error
bits : 3 - 3 (1 bit)
CRC16 : CRC16 Error
bits : 4 - 4 (1 bit)
COUNTER : Error Counter
bits : 5 - 6 (2 bit)
Host DMA Channel Next Descriptor Address Register (n = 1)
address_offset : 0x710 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write
Host DMA Channel Address Register (n = 1)
address_offset : 0x714 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write
Host DMA Channel Control Register (n = 1)
address_offset : 0x718 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CHANN_ENB : Channel Enable Command
bits : 0 - 0 (1 bit)
access : read-write
LDNXT_DSC : Load Next Channel Transfer Descriptor Enable Command
bits : 1 - 1 (1 bit)
access : read-write
END_TR_EN : End of Transfer Enable Control (OUT transfers only)
bits : 2 - 2 (1 bit)
access : read-write
END_B_EN : End of Buffer Enable Control
bits : 3 - 3 (1 bit)
access : read-write
END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write
BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write
Host DMA Channel Status Register (n = 1)
address_offset : 0x71C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write
CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write
END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write
END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write
DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write
BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write
Host DMA Channel Next Descriptor Address Register (n = 2)
address_offset : 0x720 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write
Host DMA Channel Address Register (n = 2)
address_offset : 0x724 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write
Host DMA Channel Control Register (n = 2)
address_offset : 0x728 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CHANN_ENB : Channel Enable Command
bits : 0 - 0 (1 bit)
access : read-write
LDNXT_DSC : Load Next Channel Transfer Descriptor Enable Command
bits : 1 - 1 (1 bit)
access : read-write
END_TR_EN : End of Transfer Enable Control (OUT transfers only)
bits : 2 - 2 (1 bit)
access : read-write
END_B_EN : End of Buffer Enable Control
bits : 3 - 3 (1 bit)
access : read-write
END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write
BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write
Host DMA Channel Status Register (n = 2)
address_offset : 0x72C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write
CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write
END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write
END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write
DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write
BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write
Host DMA Channel Next Descriptor Address Register (n = 3)
address_offset : 0x730 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write
Host DMA Channel Address Register (n = 3)
address_offset : 0x734 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write
Host DMA Channel Control Register (n = 3)
address_offset : 0x738 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CHANN_ENB : Channel Enable Command
bits : 0 - 0 (1 bit)
access : read-write
LDNXT_DSC : Load Next Channel Transfer Descriptor Enable Command
bits : 1 - 1 (1 bit)
access : read-write
END_TR_EN : End of Transfer Enable Control (OUT transfers only)
bits : 2 - 2 (1 bit)
access : read-write
END_B_EN : End of Buffer Enable Control
bits : 3 - 3 (1 bit)
access : read-write
END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write
BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write
Host DMA Channel Status Register (n = 3)
address_offset : 0x73C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write
CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write
END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write
END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write
DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write
BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write
Host DMA Channel Next Descriptor Address Register (n = 4)
address_offset : 0x740 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write
Host DMA Channel Address Register (n = 4)
address_offset : 0x744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write
Host DMA Channel Control Register (n = 4)
address_offset : 0x748 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CHANN_ENB : Channel Enable Command
bits : 0 - 0 (1 bit)
access : read-write
LDNXT_DSC : Load Next Channel Transfer Descriptor Enable Command
bits : 1 - 1 (1 bit)
access : read-write
END_TR_EN : End of Transfer Enable Control (OUT transfers only)
bits : 2 - 2 (1 bit)
access : read-write
END_B_EN : End of Buffer Enable Control
bits : 3 - 3 (1 bit)
access : read-write
END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write
BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write
Host DMA Channel Status Register (n = 4)
address_offset : 0x74C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write
CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write
END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write
END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write
DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write
BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write
Host DMA Channel Next Descriptor Address Register (n = 5)
address_offset : 0x750 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write
Host DMA Channel Address Register (n = 5)
address_offset : 0x754 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write
Host DMA Channel Control Register (n = 5)
address_offset : 0x758 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CHANN_ENB : Channel Enable Command
bits : 0 - 0 (1 bit)
access : read-write
LDNXT_DSC : Load Next Channel Transfer Descriptor Enable Command
bits : 1 - 1 (1 bit)
access : read-write
END_TR_EN : End of Transfer Enable Control (OUT transfers only)
bits : 2 - 2 (1 bit)
access : read-write
END_B_EN : End of Buffer Enable Control
bits : 3 - 3 (1 bit)
access : read-write
END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write
BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write
Host DMA Channel Status Register (n = 5)
address_offset : 0x75C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write
CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write
END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write
END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write
DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write
BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write
Host DMA Channel Next Descriptor Address Register (n = 6)
address_offset : 0x760 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write
Host DMA Channel Address Register (n = 6)
address_offset : 0x764 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write
Host DMA Channel Control Register (n = 6)
address_offset : 0x768 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CHANN_ENB : Channel Enable Command
bits : 0 - 0 (1 bit)
access : read-write
LDNXT_DSC : Load Next Channel Transfer Descriptor Enable Command
bits : 1 - 1 (1 bit)
access : read-write
END_TR_EN : End of Transfer Enable Control (OUT transfers only)
bits : 2 - 2 (1 bit)
access : read-write
END_B_EN : End of Buffer Enable Control
bits : 3 - 3 (1 bit)
access : read-write
END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write
BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write
Host DMA Channel Status Register (n = 6)
address_offset : 0x76C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write
CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write
END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write
END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write
DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write
BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write
Host DMA Channel Next Descriptor Address Register (n = 7)
address_offset : 0x770 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write
Host DMA Channel Address Register (n = 7)
address_offset : 0x774 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write
Host DMA Channel Control Register (n = 7)
address_offset : 0x778 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CHANN_ENB : Channel Enable Command
bits : 0 - 0 (1 bit)
access : read-write
LDNXT_DSC : Load Next Channel Transfer Descriptor Enable Command
bits : 1 - 1 (1 bit)
access : read-write
END_TR_EN : End of Transfer Enable Control (OUT transfers only)
bits : 2 - 2 (1 bit)
access : read-write
END_B_EN : End of Buffer Enable Control
bits : 3 - 3 (1 bit)
access : read-write
END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write
BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write
Host DMA Channel Status Register (n = 7)
address_offset : 0x77C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write
CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write
END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write
END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write
DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write
BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write
Device Global Interrupt Clear Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SUSPC : Suspend Interrupt Clear
bits : 0 - 0 (1 bit)
MSOFC : Micro Start of Frame Interrupt Clear
bits : 1 - 1 (1 bit)
SOFC : Start of Frame Interrupt Clear
bits : 2 - 2 (1 bit)
EORSTC : End of Reset Interrupt Clear
bits : 3 - 3 (1 bit)
WAKEUPC : Wake-Up Interrupt Clear
bits : 4 - 4 (1 bit)
EORSMC : End of Resume Interrupt Clear
bits : 5 - 5 (1 bit)
UPRSMC : Upstream Resume Interrupt Clear
bits : 6 - 6 (1 bit)
Device DMA Channel Control Register (n = 1)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANN_ENB : Channel Enable Command
bits : 0 - 0 (1 bit)
LDNXT_DSC : Load Next Channel Transfer Descriptor Enable Command
bits : 1 - 1 (1 bit)
END_TR_EN : End of Transfer Enable Control (OUT transfers only)
bits : 2 - 2 (1 bit)
END_B_EN : End of Buffer Enable Control
bits : 3 - 3 (1 bit)
END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
Host DMA Channel Control Register (n = 1)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANN_ENB : Channel Enable Command
bits : 0 - 0 (1 bit)
LDNXT_DSC : Load Next Channel Transfer Descriptor Enable Command
bits : 1 - 1 (1 bit)
END_TR_EN : End of Transfer Enable Control (OUT transfers only)
bits : 2 - 2 (1 bit)
END_B_EN : End of Buffer Enable Control
bits : 3 - 3 (1 bit)
END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
General Control Register
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDERRE : Remote Device Connection Error Interrupt Enable
bits : 4 - 4 (1 bit)
VBUSHWC : VBUS Hardware Control
bits : 8 - 8 (1 bit)
FRZCLK : Freeze USB Clock
bits : 14 - 14 (1 bit)
USBE : USBHS Enable
bits : 15 - 15 (1 bit)
UIMOD : USBHS Mode
bits : 25 - 25 (1 bit)
Enumeration: UIMODSelect
0 : HOST
The module is in USB Host mode.
1 : DEVICE
The module is in USB Device mode.
End of enumeration elements list.
General Status Register
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDERRI : Remote Device Connection Error Interrupt (Host mode only)
bits : 4 - 4 (1 bit)
SPEED : Speed Status (Device mode only)
bits : 12 - 13 (2 bit)
Enumeration: SPEEDSelect
0x0 : FULL_SPEED
Full-Speed mode
0x1 : HIGH_SPEED
High-Speed mode
0x2 : LOW_SPEED
Low-Speed mode
End of enumeration elements list.
CLKUSABLE : UTMI Clock Usable
bits : 14 - 14 (1 bit)
General Status Clear Register
address_offset : 0x808 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RDERRIC : Remote Device Connection Error Interrupt Clear
bits : 4 - 4 (1 bit)
General Status Set Register
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RDERRIS : Remote Device Connection Error Interrupt Set
bits : 4 - 4 (1 bit)
VBUSRQS : VBUS Request Set
bits : 9 - 9 (1 bit)
Device Global Interrupt Set Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SUSPS : Suspend Interrupt Set
bits : 0 - 0 (1 bit)
MSOFS : Micro Start of Frame Interrupt Set
bits : 1 - 1 (1 bit)
SOFS : Start of Frame Interrupt Set
bits : 2 - 2 (1 bit)
EORSTS : End of Reset Interrupt Set
bits : 3 - 3 (1 bit)
WAKEUPS : Wake-Up Interrupt Set
bits : 4 - 4 (1 bit)
EORSMS : End of Resume Interrupt Set
bits : 5 - 5 (1 bit)
UPRSMS : Upstream Resume Interrupt Set
bits : 6 - 6 (1 bit)
DMA_1 : DMA Channel 1 Interrupt Set
bits : 25 - 25 (1 bit)
DMA_2 : DMA Channel 2 Interrupt Set
bits : 26 - 26 (1 bit)
DMA_3 : DMA Channel 3 Interrupt Set
bits : 27 - 27 (1 bit)
DMA_4 : DMA Channel 4 Interrupt Set
bits : 28 - 28 (1 bit)
DMA_5 : DMA Channel 5 Interrupt Set
bits : 29 - 29 (1 bit)
DMA_6 : DMA Channel 6 Interrupt Set
bits : 30 - 30 (1 bit)
DMA_7 : DMA Channel 7 Interrupt Set
bits : 31 - 31 (1 bit)
Device DMA Channel Status Register (n = 1)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
Host DMA Channel Status Register (n = 1)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
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