Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x24C byte (0x0)
mem_usage : registers
protection :
CPUID Base Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
REVISION : Indicates patch release: 0x0 = Patch 0
bits : 0 - 3 (4 bit)
PARTNO : Indicates part number
bits : 4 - 15 (12 bit)
ARCHITECTURE : Indicates architecture. Reads as 0xF
bits : 16 - 19 (4 bit)
VARIANT : Indicates processor revision: 0x2 = Revision 2
bits : 20 - 23 (4 bit)
IMPLEMENTER : Implementer code
bits : 24 - 31 (8 bit)
System Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLEEPONEXIT : Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state
bits : 1 - 1 (1 bit)
Enumeration: SLEEPONEXITSelect
0 : VALUE_0
o not sleep when returning to Thread mode
1 : VALUE_1
enter sleep, or deep sleep, on return from an ISR
End of enumeration elements list.
SLEEPDEEP : Provides a qualifying hint indicating that waking from sleep might take longer
bits : 2 - 2 (1 bit)
Enumeration: SLEEPDEEPSelect
0 : VALUE_0
sleep
1 : VALUE_1
deep sleep
End of enumeration elements list.
SEVONPEND : Determines whether an interrupt transition from inactive state to pending state is a wakeup event
bits : 4 - 4 (1 bit)
Enumeration: SEVONPENDSelect
0 : VALUE_0
only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded
1 : VALUE_1
enabled events and all interrupts, including disabled interrupts, can wakeup the processor
End of enumeration elements list.
Configuration and Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NONBASETHRDENA : Controls whether the processor can enter Thread mode with exceptions active
bits : 0 - 0 (1 bit)
Enumeration: NONBASETHRDENASelect
0 : VALUE_0
processor can enter Thread mode only when no exception is active
1 : VALUE_1
processor can enter Thread mode from any level under the control of an EXC_RETURN value
End of enumeration elements list.
USERSETMPEND : Enables unprivileged software access to the STIR
bits : 1 - 1 (1 bit)
Enumeration: USERSETMPENDSelect
0 : VALUE_0
disable
1 : VALUE_1
enable
End of enumeration elements list.
UNALIGN_TRP : Enables unaligned access traps
bits : 3 - 3 (1 bit)
Enumeration: UNALIGN_TRPSelect
0 : VALUE_0
do not trap unaligned halfword and word accesses
1 : VALUE_1
trap unaligned halfword and word accesses
End of enumeration elements list.
DIV_0_TRP : Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0
bits : 4 - 4 (1 bit)
Enumeration: DIV_0_TRPSelect
0 : VALUE_0
do not trap divide by 0
1 : VALUE_1
trap divide by 0
End of enumeration elements list.
BFHFNMIGN : Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions.
bits : 8 - 8 (1 bit)
Enumeration: BFHFNMIGNSelect
0 : VALUE_0
data bus faults caused by load and store instructions cause a lock-up
1 : VALUE_1
handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions
End of enumeration elements list.
STKALIGN : Indicates stack alignment on exception entry
bits : 9 - 9 (1 bit)
Enumeration: STKALIGNSelect
0 : VALUE_0
4-byte aligned
1 : VALUE_1
8-byte aligned
End of enumeration elements list.
DC : Cache enable bit
bits : 16 - 16 (1 bit)
IC : Instruction cache enable bi
bits : 17 - 17 (1 bit)
BP : Branch prediction enable bi
bits : 18 - 18 (1 bit)
System Handler Priority Register 1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_4 : Priority of system handler 4, MemManage
bits : 0 - 7 (8 bit)
PRI_5 : Priority of system handler 5, BusFault
bits : 8 - 15 (8 bit)
PRI_6 : Priority of system handler 6, UsageFault
bits : 16 - 23 (8 bit)
System Handler Priority Register 2
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_11 : Priority of system handler 11, SVCall
bits : 24 - 31 (8 bit)
System Handler Priority Register 3
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_12 : Priority of system handler 12, SysTick
bits : 0 - 7 (8 bit)
PRI_14 : Priority of system handler 14, PendSV
bits : 16 - 23 (8 bit)
PRI_15 : Priority of system handler 15, SysTick exception
bits : 24 - 31 (8 bit)
Software Trigger Interrupt Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTID : Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of 0x03 specifies interrupt IRQ3.
bits : 0 - 8 (9 bit)
System Handler Control and State Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MEMFAULTACT :
bits : 0 - 0 (1 bit)
Enumeration: MEMFAULTACTSelect
0 : VALUE_0
exception is not active
1 : VALUE_1
exception is active
End of enumeration elements list.
BUSFAULTACT :
bits : 1 - 1 (1 bit)
Enumeration: BUSFAULTACTSelect
0 : VALUE_0
exception is not active
1 : VALUE_1
exception is active
End of enumeration elements list.
USGFAULTACT :
bits : 3 - 3 (1 bit)
Enumeration: USGFAULTACTSelect
0 : VALUE_0
exception is not active
1 : VALUE_1
exception is active
End of enumeration elements list.
SVCALLACT :
bits : 7 - 7 (1 bit)
Enumeration: SVCALLACTSelect
0 : VALUE_0
exception is not active
1 : VALUE_1
exception is active
End of enumeration elements list.
MONITORACT :
bits : 8 - 8 (1 bit)
Enumeration: MONITORACTSelect
0 : VALUE_0
exception is not active
1 : VALUE_1
exception is active
End of enumeration elements list.
PENDSVACT :
bits : 10 - 10 (1 bit)
Enumeration: PENDSVACTSelect
0 : VALUE_0
exception is not active
1 : VALUE_1
exception is active
End of enumeration elements list.
SYSTICKACT :
bits : 11 - 11 (1 bit)
Enumeration: SYSTICKACTSelect
0 : VALUE_0
exception is not active
1 : VALUE_1
exception is active
End of enumeration elements list.
USGFAULTPENDED :
bits : 12 - 12 (1 bit)
Enumeration: USGFAULTPENDEDSelect
0 : VALUE_0
exception is not pending
1 : VALUE_1
exception is pending
End of enumeration elements list.
MEMFAULTPENDED :
bits : 13 - 13 (1 bit)
Enumeration: MEMFAULTPENDEDSelect
0 : VALUE_0
exception is not pending
1 : VALUE_1
exception is pending
End of enumeration elements list.
BUSFAULTPENDED :
bits : 14 - 14 (1 bit)
Enumeration: BUSFAULTPENDEDSelect
0 : VALUE_0
exception is not pending
1 : VALUE_1
exception is pending
End of enumeration elements list.
SVCALLPENDED :
bits : 15 - 15 (1 bit)
Enumeration: SVCALLPENDEDSelect
0 : VALUE_0
exception is not pending
1 : VALUE_1
exception is pending
End of enumeration elements list.
MEMFAULTENA :
bits : 16 - 16 (1 bit)
Enumeration: MEMFAULTENASelect
0 : VALUE_0
disable the exception
1 : VALUE_1
enable the exception
End of enumeration elements list.
BUSFAULTENA :
bits : 17 - 17 (1 bit)
Enumeration: BUSFAULTENASelect
0 : VALUE_0
disable the exception
1 : VALUE_1
enable the exception
End of enumeration elements list.
USGFAULTENA :
bits : 18 - 18 (1 bit)
Enumeration: USGFAULTENASelect
0 : VALUE_0
disable the exception
1 : VALUE_1
enable the exception
End of enumeration elements list.
Media and VFP Feature Register 0
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Media and VFP Feature Register 1
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Media and VFP Feature Register 2
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Configurable Fault Status Registers
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IACCVIOL :
bits : 0 - 0 (1 bit)
Enumeration: IACCVIOLSelect
0 : VALUE_0
no instruction access violation fault
1 : VALUE_1
the processor attempted an instruction fetch from a location that does not permit execution
End of enumeration elements list.
DACCVIOL :
bits : 1 - 1 (1 bit)
Enumeration: DACCVIOLSelect
0 : VALUE_0
no data access violation fault
1 : VALUE_1
the processor attempted a load or store at a location that does not permit the operation
End of enumeration elements list.
MUNSTKERR :
bits : 3 - 3 (1 bit)
Enumeration: MUNSTKERRSelect
0 : VALUE_0
no unstacking fault
1 : VALUE_1
unstack for an exception return has caused one or more access violations
End of enumeration elements list.
MSTKERR :
bits : 4 - 4 (1 bit)
Enumeration: MSTKERRSelect
0 : VALUE_0
no stacking fault
1 : VALUE_1
stacking for an exception entry has caused one or more access violations
End of enumeration elements list.
MLSPERR :
bits : 5 - 5 (1 bit)
Enumeration: MLSPERRSelect
0 : VALUE_0
No MemManage fault occurred during floating-point lazy state preservation
1 : VALUE_1
A MemManage fault occurred during floating-point lazy state preservation
End of enumeration elements list.
MMARVALID :
bits : 7 - 7 (1 bit)
Enumeration: MMARVALIDSelect
0 : VALUE_0
value in MMAR is not a valid fault address
1 : VALUE_1
MMAR holds a valid fault address
End of enumeration elements list.
IBUSERR :
bits : 8 - 8 (1 bit)
Enumeration: IBUSERRSelect
0 : VALUE_0
no instruction bus error
1 : VALUE_1
instruction bus error
End of enumeration elements list.
PRECISERR :
bits : 9 - 9 (1 bit)
Enumeration: PRECISERRSelect
0 : VALUE_0
no precise data bus error
1 : VALUE_1
a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault
End of enumeration elements list.
IMPRECISERR :
bits : 10 - 10 (1 bit)
Enumeration: IMPRECISERRSelect
0 : VALUE_0
no imprecise data bus error
1 : VALUE_1
a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error
End of enumeration elements list.
UNSTKERR :
bits : 11 - 11 (1 bit)
Enumeration: UNSTKERRSelect
0 : VALUE_0
no unstacking fault
1 : VALUE_1
unstack for an exception return has caused one or more BusFaults
End of enumeration elements list.
STKERR :
bits : 12 - 12 (1 bit)
Enumeration: STKERRSelect
0 : VALUE_0
no stacking fault
1 : VALUE_1
stacking for an exception entry has caused one or more BusFaults
End of enumeration elements list.
LSPERR :
bits : 13 - 13 (1 bit)
Enumeration: LSPERRSelect
0 : VALUE_0
No bus fault occurred during floating-point lazy state preservation
1 : VALUE_1
A bus fault occurred during floating-point lazy state preservation
End of enumeration elements list.
BFARVALID :
bits : 15 - 15 (1 bit)
Enumeration: BFARVALIDSelect
0 : VALUE_0
value in BFAR is not a valid fault address
1 : VALUE_1
BFAR holds a valid fault address
End of enumeration elements list.
UNDEFINSTR :
bits : 16 - 16 (1 bit)
Enumeration: UNDEFINSTRSelect
0 : VALUE_0
no undefined instruction UsageFault
1 : VALUE_1
the processor has attempted to execute an undefined instruction
End of enumeration elements list.
INVSTATE :
bits : 17 - 17 (1 bit)
Enumeration: INVSTATESelect
0 : VALUE_0
no invalid state UsageFault
1 : VALUE_1
the processor has attempted to execute an instruction that makes illegal use of the EPSR
End of enumeration elements list.
INVPC :
bits : 18 - 18 (1 bit)
Enumeration: INVPCSelect
0 : VALUE_0
no invalid PC load UsageFault
1 : VALUE_1
the processor has attempted an illegal load of EXC_RETURN to the PC
End of enumeration elements list.
NOCP :
bits : 19 - 19 (1 bit)
Enumeration: NOCPSelect
0 : VALUE_0
no UsageFault caused by attempting to access a coprocessor
1 : VALUE_1
the processor has attempted to access a coprocessor
End of enumeration elements list.
UNALIGNED :
bits : 24 - 24 (1 bit)
Enumeration: UNALIGNEDSelect
0 : VALUE_0
no unaligned access fault, or unaligned access trapping not enabled
1 : VALUE_1
the processor has made an unaligned memory access
End of enumeration elements list.
DIVBYZERO :
bits : 25 - 25 (1 bit)
Enumeration: DIVBYZEROSelect
0 : VALUE_0
no divide by zero fault, or divide by zero trapping not enabled
1 : VALUE_1
the processor has executed an SDIV or UDIV instruction with a divisor of 0
End of enumeration elements list.
HardFault Status register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTTBL : Indicates when a fault has occurred because of a vector table read error on exception processing
bits : 1 - 1 (1 bit)
Enumeration: VECTTBLSelect
0 : VALUE_0
no BusFault on vector table read
1 : VALUE_1
BusFault on vector table read
End of enumeration elements list.
FORCED : Indicates that a fault with configurable priority has been escalated to a HardFault exception
bits : 30 - 30 (1 bit)
Enumeration: FORCEDSelect
0 : VALUE_0
no forced HardFault
1 : VALUE_1
forced HardFault
End of enumeration elements list.
DEBUGEVT : Indicates when a Debug event has occurred
bits : 31 - 31 (1 bit)
Debug Fault Status Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HALTED : debug event generated by
bits : 0 - 0 (1 bit)
Enumeration: HALTEDSelect
0 : VALUE_0
No active halt request debug event
1 : VALUE_1
Halt request debug event active
End of enumeration elements list.
BKPT : debug event generated by BKPT instruction execution or a breakpoint match in FPB
bits : 1 - 1 (1 bit)
Enumeration: BKPTSelect
0 : VALUE_0
No current breakpoint debug event
1 : VALUE_1
At least one current breakpoint debug event
End of enumeration elements list.
DWTTRAP : debug event generated by the DWT
bits : 2 - 2 (1 bit)
Enumeration: DWTTRAPSelect
0 : VALUE_0
No current debug events generated by the DWT
1 : VALUE_1
At least one current debug event generated by the DWT
End of enumeration elements list.
VCATCH : triggering of a Vector catch
bits : 3 - 3 (1 bit)
Enumeration: VCATCHSelect
0 : VALUE_0
No Vector catch triggered
1 : VALUE_1
Vector catch triggered
End of enumeration elements list.
EXTERNAL : debug event generated because of the assertion of an external debug request
bits : 4 - 4 (1 bit)
Enumeration: EXTERNALSelect
0 : VALUE_0
No EDBGRQ debug event
1 : VALUE_1
EDBGRQ debug event
End of enumeration elements list.
MemManage Fault Address Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : Data address for an MPU fault
bits : 0 - 31 (32 bit)
BusFault Address Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : Data address for a precise bus fault
bits : 0 - 31 (32 bit)
Auxiliary Fault Status Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Interrupt Control and State Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTACTIVE : Active exception number
bits : 0 - 8 (9 bit)
RETTOBASE : Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR
bits : 11 - 11 (1 bit)
Enumeration: RETTOBASESelect
0 : VALUE_0
there are preempted active exceptions to execute
1 : VALUE_1
there are no active exceptions, or the currently-executing exception is the only active exception
End of enumeration elements list.
VECTPENDING : Exception number of the highest priority pending enabled exception
bits : 12 - 17 (6 bit)
ISRPENDING : Is external interrupt, generated by the NVIC, pending
bits : 22 - 22 (1 bit)
ISRPREEMPT : Indicates whether a pending exception will be serviced on exit from debug halt state
bits : 23 - 23 (1 bit)
Enumeration: ISRPREEMPTSelect
0 : VALUE_0
Will not service
1 : VALUE_1
Will service a pending exception
End of enumeration elements list.
PENDSTCLR : Removes the pending status of the SysTick exception
bits : 25 - 25 (1 bit)
Enumeration: PENDSTCLRSelect
0 : VALUE_0
no effect
1 : VALUE_1
removes the pending state from the SysTick exception
End of enumeration elements list.
PENDSTSET : Sets the SysTick exception as pending, or reads the current state of the exception
bits : 26 - 26 (1 bit)
Enumeration: PENDSTSETSelect
0 : VALUE_0
write: no effect read: SysTick exception is not pending
1 : VALUE_1
write: changes SysTick exception state to pending read: SysTick exception is pending
End of enumeration elements list.
PENDSVCLR : Removes the pending status of the PendSV exception
bits : 27 - 27 (1 bit)
Enumeration: PENDSVCLRSelect
0 : VALUE_0
no effect
1 : VALUE_1
removes the pending state from the PendSV exception
End of enumeration elements list.
PENDSVSET : Sets the PendSV exception as pending, or reads the current state of the exception
bits : 28 - 28 (1 bit)
Enumeration: PENDSVSETSelect
0 : VALUE_0
write: no effect read: PendSV exception is not pending
1 : VALUE_1
write: changes PendSV exception state to pending read: PendSV exception is pending
End of enumeration elements list.
NMIPENDSET : Makes the NMI exception active, or reads the state of the exception
bits : 31 - 31 (1 bit)
Enumeration: NMIPENDSETSelect
0 : VALUE_0
write: no effect read: NMI exception is not pending
1 : VALUE_1
write: changes NMI exception state to pending read: NMI exception is pending
End of enumeration elements list.
Cache Level ID Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LoC : Level of Coherency
bits : 24 - 26 (3 bit)
Enumeration: LoCSelect
0 : LEVEL_1
if neither instruction nor data cache is implemented
1 : LEVEL_2
if either cache is implemented
End of enumeration elements list.
LoU : Level of Unification
bits : 27 - 29 (3 bit)
Enumeration: LoUSelect
0 : LEVEL_1
if neither instruction nor data cache is implemented
1 : LEVEL_2
if either cache is implemented
End of enumeration elements list.
Cache Type Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IMINLINE : Smallest cache line of all the instruction caches under the control of the processor
bits : 0 - 3 (4 bit)
DMINLINE : Smallest cache line of all the data and unified caches under the core control
bits : 16 - 19 (4 bit)
ERG : Exclusives Reservation Granule
bits : 20 - 23 (4 bit)
CWG : Cache Writeback Granule
bits : 24 - 27 (4 bit)
FORMAT : Register format
bits : 29 - 31 (3 bit)
Vector Table Offset Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TBLOFF : Bits[31:7] of the vector table address
bits : 7 - 31 (25 bit)
Cache Size ID Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LineSize : number of words in each cache line
bits : 0 - 2 (3 bit)
Associativity : number of ways
bits : 3 - 11 (9 bit)
NumSets : number of sets
bits : 12 - 27 (16 bit)
WA : Write allocation support
bits : 28 - 28 (1 bit)
RA : Read allocation support
bits : 29 - 29 (1 bit)
WB : Write-Back support
bits : 30 - 30 (1 bit)
WT : Write-Through support
bits : 31 - 31 (1 bit)
Cache Size Selection Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IND : selection of instruction or data cache
bits : 0 - 0 (1 bit)
Enumeration: INDSelect
0 : DATA
Data cache
1 : INSTRUCTION
Instruction cache
End of enumeration elements list.
LEVEL : cache level selected
bits : 1 - 3 (3 bit)
Coprocessor Access Control Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CP10 : Access privileges for coprocessor 10.
bits : 20 - 21 (2 bit)
CP11 : Access privileges for coprocessor 11.
bits : 22 - 23 (2 bit)
Application Interrupt and Reset Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTRESET : Writing 1 to this bit causes a local system reset
bits : 0 - 0 (1 bit)
VECTCLRACTIVE : Clears all active state information for fixed and configurable exceptions
bits : 1 - 1 (1 bit)
SYSRESETREQ : System Reset Request
bits : 2 - 2 (1 bit)
Enumeration: SYSRESETREQSelect
0 : VALUE_0
no system reset request
1 : VALUE_1
asserts a signal to the outer system that requests a reset
End of enumeration elements list.
PRIGROUP : Interrupt priority grouping field. This field determines the split of group priority from subpriority.
bits : 8 - 10 (3 bit)
ENDIANNESS : Memory system endianness
bits : 15 - 15 (1 bit)
Enumeration: ENDIANNESSSelect
0 : VALUE_0
Little-endian
1 : VALUE_1
Big-endian
End of enumeration elements list.
VECTKEY : Vector key
bits : 16 - 31 (16 bit)
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