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ICM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x58 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x0 Bytes (0x0)
size : 0x58 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x0 Bytes (0x0)
size : 0x58 byte (0x0)
mem_usage : registers
protection :

Registers

CFG

IER

IDR

IMR

ISR

UASR

DSCR

HASH

UIHVAL0

UIHVAL1

CTRL

UIHVAL2

UIHVAL3

UIHVAL4

UIHVAL5

UIHVAL6

UIHVAL7

SR


CFG

Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WBDIS EOMDIS SLBDIS BBC ASCD DUALBUFF UIHASH UALGO

WBDIS : Write Back Disable
bits : 0 - 0 (1 bit)

EOMDIS : End of Monitoring Disable
bits : 1 - 1 (1 bit)

SLBDIS : Secondary List Branching Disable
bits : 2 - 2 (1 bit)

BBC : Bus Burden Control
bits : 4 - 7 (4 bit)

ASCD : Automatic Switch To Compare Digest
bits : 8 - 8 (1 bit)

DUALBUFF : Dual Input Buffer
bits : 9 - 9 (1 bit)

UIHASH : User Initial Hash Value
bits : 12 - 12 (1 bit)

UALGO : User SHA Algorithm
bits : 13 - 15 (3 bit)

Enumeration: UALGOSelect

0x0 : SHA1

SHA1 algorithm processed

0x1 : SHA256

SHA256 algorithm processed

0x4 : SHA224

SHA224 algorithm processed

End of enumeration elements list.


IER

Interrupt Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RHC RDM RBE RWC REC RSU URAD

RHC : Region Hash Completed Interrupt Enable
bits : 0 - 3 (4 bit)

RDM : Region Digest Mismatch Interrupt Enable
bits : 4 - 7 (4 bit)

RBE : Region Bus Error Interrupt Enable
bits : 8 - 11 (4 bit)

RWC : Region Wrap Condition detected Interrupt Enable
bits : 12 - 15 (4 bit)

REC : Region End bit Condition Detected Interrupt Enable
bits : 16 - 19 (4 bit)

RSU : Region Status Updated Interrupt Disable
bits : 20 - 23 (4 bit)

URAD : Undefined Register Access Detection Interrupt Enable
bits : 24 - 24 (1 bit)


IDR

Interrupt Disable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RHC RDM RBE RWC REC RSU URAD

RHC : Region Hash Completed Interrupt Disable
bits : 0 - 3 (4 bit)

RDM : Region Digest Mismatch Interrupt Disable
bits : 4 - 7 (4 bit)

RBE : Region Bus Error Interrupt Disable
bits : 8 - 11 (4 bit)

RWC : Region Wrap Condition Detected Interrupt Disable
bits : 12 - 15 (4 bit)

REC : Region End bit Condition detected Interrupt Disable
bits : 16 - 19 (4 bit)

RSU : Region Status Updated Interrupt Disable
bits : 20 - 23 (4 bit)

URAD : Undefined Register Access Detection Interrupt Disable
bits : 24 - 24 (1 bit)


IMR

Interrupt Mask Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RHC RDM RBE RWC REC RSU URAD

RHC : Region Hash Completed Interrupt Mask
bits : 0 - 3 (4 bit)

RDM : Region Digest Mismatch Interrupt Mask
bits : 4 - 7 (4 bit)

RBE : Region Bus Error Interrupt Mask
bits : 8 - 11 (4 bit)

RWC : Region Wrap Condition Detected Interrupt Mask
bits : 12 - 15 (4 bit)

REC : Region End bit Condition Detected Interrupt Mask
bits : 16 - 19 (4 bit)

RSU : Region Status Updated Interrupt Mask
bits : 20 - 23 (4 bit)

URAD : Undefined Register Access Detection Interrupt Mask
bits : 24 - 24 (1 bit)


ISR

Interrupt Status Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RHC RDM RBE RWC REC RSU URAD

RHC : Region Hash Completed
bits : 0 - 3 (4 bit)

RDM : Region Digest Mismatch
bits : 4 - 7 (4 bit)

RBE : Region Bus Error
bits : 8 - 11 (4 bit)

RWC : Region Wrap Condition Detected
bits : 12 - 15 (4 bit)

REC : Region End bit Condition Detected
bits : 16 - 19 (4 bit)

RSU : Region Status Updated Detected
bits : 20 - 23 (4 bit)

URAD : Undefined Register Access Detection Status
bits : 24 - 24 (1 bit)


UASR

Undefined Access Status Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UASR UASR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 URAT

URAT : Undefined Register Access Trace
bits : 0 - 2 (3 bit)

Enumeration: URATSelect

0x0 : UNSPEC_STRUCT_MEMBER

Unspecified structure member set to one detected when the descriptor is loaded.

0x1 : ICM_CFG_MODIFIED

ICM_CFG modified during active monitoring.

0x2 : ICM_DSCR_MODIFIED

ICM_DSCR modified during active monitoring.

0x3 : ICM_HASH_MODIFIED

ICM_HASH modified during active monitoring

0x4 : READ_ACCESS

Write-only register read access

End of enumeration elements list.


DSCR

Region Descriptor Area Start Address Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSCR DSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DASA

DASA : Descriptor Area Start Address
bits : 6 - 31 (26 bit)


HASH

Region Hash Area Start Address Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HASH HASH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HASA

HASA : Hash Area Start Address
bits : 7 - 31 (25 bit)


UIHVAL0

User Initial Hash Value 0 Register 0
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UIHVAL0 UIHVAL0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VAL

VAL : Initial Hash Value
bits : 0 - 31 (32 bit)


UIHVAL1

User Initial Hash Value 0 Register 0
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UIHVAL1 UIHVAL1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VAL

VAL : Initial Hash Value
bits : 0 - 31 (32 bit)


CTRL

Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE DISABLE SWRST REHASH RMDIS RMEN

ENABLE : ICM Enable
bits : 0 - 0 (1 bit)

DISABLE : ICM Disable Register
bits : 1 - 1 (1 bit)

SWRST : Software Reset
bits : 2 - 2 (1 bit)

REHASH : Recompute Internal Hash
bits : 4 - 7 (4 bit)

RMDIS : Region Monitoring Disable
bits : 8 - 11 (4 bit)

RMEN : Region Monitoring Enable
bits : 12 - 15 (4 bit)


UIHVAL2

User Initial Hash Value 0 Register 0
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UIHVAL2 UIHVAL2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VAL

VAL : Initial Hash Value
bits : 0 - 31 (32 bit)


UIHVAL3

User Initial Hash Value 0 Register 0
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UIHVAL3 UIHVAL3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VAL

VAL : Initial Hash Value
bits : 0 - 31 (32 bit)


UIHVAL4

User Initial Hash Value 0 Register 0
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UIHVAL4 UIHVAL4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VAL

VAL : Initial Hash Value
bits : 0 - 31 (32 bit)


UIHVAL5

User Initial Hash Value 0 Register 0
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UIHVAL5 UIHVAL5 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VAL

VAL : Initial Hash Value
bits : 0 - 31 (32 bit)


UIHVAL6

User Initial Hash Value 0 Register 0
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UIHVAL6 UIHVAL6 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VAL

VAL : Initial Hash Value
bits : 0 - 31 (32 bit)


UIHVAL7

User Initial Hash Value 0 Register 0
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UIHVAL7 UIHVAL7 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VAL

VAL : Initial Hash Value
bits : 0 - 31 (32 bit)


SR

Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE RAWRMDIS RMDIS

ENABLE : ICM Controller Enable Register
bits : 0 - 0 (1 bit)

RAWRMDIS : Region Monitoring Disabled Raw Status
bits : 8 - 11 (4 bit)

RMDIS : Region Monitoring Disabled Status
bits : 12 - 15 (4 bit)



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