XDMAC

Channel Destination Address Register (chid = 0)
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)

CSUS3

Channel Source Microblock Stride (chid = 3)
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CDUS3

Channel Destination Microblock Stride (chid = 3)
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CIE4

Channel Interrupt Enable Register (chid = 4)
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only

CID4

Channel Interrupt Disable Register (chid = 4)
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only

CIM4

Channel Interrupt Mask Register (chid = 4)
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : write-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : write-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : write-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : write-only

CIS4

Channel Interrupt Status Register (chid = 4)
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only

CSA4

Channel Source Address Register (chid = 4)
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write

CDA4

Channel Destination Address Register (chid = 4)
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write

CNDA4

Channel Next Descriptor Address Register (chid = 4)
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write

CNDC4

Channel Next Descriptor Control Register (chid = 4)
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.

CUBC4

Channel Microblock Control Register (chid = 4)
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write

CBC4

Channel Block Control Register (chid = 4)
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write

CC4

Channel Configuration Register (chid = 4)
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self triggered mode (Memory to Memory Transfer).

1 : PER_TRAN

Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral to Memory transfer.

1 : MEM2PER

Memory to Peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : TERMINATED

Channel initialization is in progress.

1 : IN_PROGRESS

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active write transaction on the bus.

1 : IN_PROGRESS

A Write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write

CDS_MSP4

Channel Data Stride Memory Set Pattern (chid = 4)
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write

GIS

Global Interrupt Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IS0 : XDMAC Channel 0 Interrupt Status Bit
bits : 0 - 0 (1 bit)

IS1 : XDMAC Channel 1 Interrupt Status Bit
bits : 1 - 1 (1 bit)

IS2 : XDMAC Channel 2 Interrupt Status Bit
bits : 2 - 2 (1 bit)

IS3 : XDMAC Channel 3 Interrupt Status Bit
bits : 3 - 3 (1 bit)

IS4 : XDMAC Channel 4 Interrupt Status Bit
bits : 4 - 4 (1 bit)

IS5 : XDMAC Channel 5 Interrupt Status Bit
bits : 5 - 5 (1 bit)

IS6 : XDMAC Channel 6 Interrupt Status Bit
bits : 6 - 6 (1 bit)

IS7 : XDMAC Channel 7 Interrupt Status Bit
bits : 7 - 7 (1 bit)

IS8 : XDMAC Channel 8 Interrupt Status Bit
bits : 8 - 8 (1 bit)

IS9 : XDMAC Channel 9 Interrupt Status Bit
bits : 9 - 9 (1 bit)

IS10 : XDMAC Channel 10 Interrupt Status Bit
bits : 10 - 10 (1 bit)

IS11 : XDMAC Channel 11 Interrupt Status Bit
bits : 11 - 11 (1 bit)

IS12 : XDMAC Channel 12 Interrupt Status Bit
bits : 12 - 12 (1 bit)

IS13 : XDMAC Channel 13 Interrupt Status Bit
bits : 13 - 13 (1 bit)

IS14 : XDMAC Channel 14 Interrupt Status Bit
bits : 14 - 14 (1 bit)

IS15 : XDMAC Channel 15 Interrupt Status Bit
bits : 15 - 15 (1 bit)

IS16 : XDMAC Channel 16 Interrupt Status Bit
bits : 16 - 16 (1 bit)

IS17 : XDMAC Channel 17 Interrupt Status Bit
bits : 17 - 17 (1 bit)

IS18 : XDMAC Channel 18 Interrupt Status Bit
bits : 18 - 18 (1 bit)

IS19 : XDMAC Channel 19 Interrupt Status Bit
bits : 19 - 19 (1 bit)

IS20 : XDMAC Channel 20 Interrupt Status Bit
bits : 20 - 20 (1 bit)

IS21 : XDMAC Channel 21 Interrupt Status Bit
bits : 21 - 21 (1 bit)

IS22 : XDMAC Channel 22 Interrupt Status Bit
bits : 22 - 22 (1 bit)

IS23 : XDMAC Channel 23 Interrupt Status Bit
bits : 23 - 23 (1 bit)

CNDA

Channel Next Descriptor Address Register (chid = 0)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)

CSUS4

Channel Source Microblock Stride (chid = 4)
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CDUS4

Channel Destination Microblock Stride (chid = 4)
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CIE5

Channel Interrupt Enable Register (chid = 5)
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only

CID5

Channel Interrupt Disable Register (chid = 5)
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only

CIM5

Channel Interrupt Mask Register (chid = 5)
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : write-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : write-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : write-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : write-only

CIS5

Channel Interrupt Status Register (chid = 5)
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only

CSA5

Channel Source Address Register (chid = 5)
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write

CDA5

Channel Destination Address Register (chid = 5)
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write

CNDA5

Channel Next Descriptor Address Register (chid = 5)
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write

CNDC5

Channel Next Descriptor Control Register (chid = 5)
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.

CUBC5

Channel Microblock Control Register (chid = 5)
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write

CBC5

Channel Block Control Register (chid = 5)
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write

CC5

Channel Configuration Register (chid = 5)
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self triggered mode (Memory to Memory Transfer).

1 : PER_TRAN

Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral to Memory transfer.

1 : MEM2PER

Memory to Peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : TERMINATED

Channel initialization is in progress.

1 : IN_PROGRESS

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active write transaction on the bus.

1 : IN_PROGRESS

A Write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write

CDS_MSP5

Channel Data Stride Memory Set Pattern (chid = 5)
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write

GE

Global Channel Enable Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EN0 : XDMAC Channel 0 Enable Bit
bits : 0 - 0 (1 bit)

EN1 : XDMAC Channel 1 Enable Bit
bits : 1 - 1 (1 bit)

EN2 : XDMAC Channel 2 Enable Bit
bits : 2 - 2 (1 bit)

EN3 : XDMAC Channel 3 Enable Bit
bits : 3 - 3 (1 bit)

EN4 : XDMAC Channel 4 Enable Bit
bits : 4 - 4 (1 bit)

EN5 : XDMAC Channel 5 Enable Bit
bits : 5 - 5 (1 bit)

EN6 : XDMAC Channel 6 Enable Bit
bits : 6 - 6 (1 bit)

EN7 : XDMAC Channel 7 Enable Bit
bits : 7 - 7 (1 bit)

EN8 : XDMAC Channel 8 Enable Bit
bits : 8 - 8 (1 bit)

EN9 : XDMAC Channel 9 Enable Bit
bits : 9 - 9 (1 bit)

EN10 : XDMAC Channel 10 Enable Bit
bits : 10 - 10 (1 bit)

EN11 : XDMAC Channel 11 Enable Bit
bits : 11 - 11 (1 bit)

EN12 : XDMAC Channel 12 Enable Bit
bits : 12 - 12 (1 bit)

EN13 : XDMAC Channel 13 Enable Bit
bits : 13 - 13 (1 bit)

EN14 : XDMAC Channel 14 Enable Bit
bits : 14 - 14 (1 bit)

EN15 : XDMAC Channel 15 Enable Bit
bits : 15 - 15 (1 bit)

EN16 : XDMAC Channel 16 Enable Bit
bits : 16 - 16 (1 bit)

EN17 : XDMAC Channel 17 Enable Bit
bits : 17 - 17 (1 bit)

EN18 : XDMAC Channel 18 Enable Bit
bits : 18 - 18 (1 bit)

EN19 : XDMAC Channel 19 Enable Bit
bits : 19 - 19 (1 bit)

EN20 : XDMAC Channel 20 Enable Bit
bits : 20 - 20 (1 bit)

EN21 : XDMAC Channel 21 Enable Bit
bits : 21 - 21 (1 bit)

EN22 : XDMAC Channel 22 Enable Bit
bits : 22 - 22 (1 bit)

EN23 : XDMAC Channel 23 Enable Bit
bits : 23 - 23 (1 bit)

CNDC

Channel Next Descriptor Control Register (chid = 0)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)

Enumeration: NDESelect

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)

Enumeration: NDSUPSelect

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)

Enumeration: NDDUPSelect

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)

Enumeration: NDVIEWSelect

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.

CSUS5

Channel Source Microblock Stride (chid = 5)
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CDUS5

Channel Destination Microblock Stride (chid = 5)
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CIE6

Channel Interrupt Enable Register (chid = 6)
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only

CID6

Channel Interrupt Disable Register (chid = 6)
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only

CIM6

Channel Interrupt Mask Register (chid = 6)
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : write-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : write-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : write-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : write-only

CIS6

Channel Interrupt Status Register (chid = 6)
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only

CSA6

Channel Source Address Register (chid = 6)
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write

CDA6

Channel Destination Address Register (chid = 6)
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write

CNDA6

Channel Next Descriptor Address Register (chid = 6)
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write

CNDC6

Channel Next Descriptor Control Register (chid = 6)
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.

CUBC6

Channel Microblock Control Register (chid = 6)
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write

CBC6

Channel Block Control Register (chid = 6)
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write

CC6

Channel Configuration Register (chid = 6)
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self triggered mode (Memory to Memory Transfer).

1 : PER_TRAN

Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral to Memory transfer.

1 : MEM2PER

Memory to Peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : TERMINATED

Channel initialization is in progress.

1 : IN_PROGRESS

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active write transaction on the bus.

1 : IN_PROGRESS

A Write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write

CDS_MSP6

Channel Data Stride Memory Set Pattern (chid = 6)
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write

GD

Global Channel Disable Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DI0 : XDMAC Channel 0 Disable Bit
bits : 0 - 0 (1 bit)

DI1 : XDMAC Channel 1 Disable Bit
bits : 1 - 1 (1 bit)

DI2 : XDMAC Channel 2 Disable Bit
bits : 2 - 2 (1 bit)

DI3 : XDMAC Channel 3 Disable Bit
bits : 3 - 3 (1 bit)

DI4 : XDMAC Channel 4 Disable Bit
bits : 4 - 4 (1 bit)

DI5 : XDMAC Channel 5 Disable Bit
bits : 5 - 5 (1 bit)

DI6 : XDMAC Channel 6 Disable Bit
bits : 6 - 6 (1 bit)

DI7 : XDMAC Channel 7 Disable Bit
bits : 7 - 7 (1 bit)

DI8 : XDMAC Channel 8 Disable Bit
bits : 8 - 8 (1 bit)

DI9 : XDMAC Channel 9 Disable Bit
bits : 9 - 9 (1 bit)

DI10 : XDMAC Channel 10 Disable Bit
bits : 10 - 10 (1 bit)

DI11 : XDMAC Channel 11 Disable Bit
bits : 11 - 11 (1 bit)

DI12 : XDMAC Channel 12 Disable Bit
bits : 12 - 12 (1 bit)

DI13 : XDMAC Channel 13 Disable Bit
bits : 13 - 13 (1 bit)

DI14 : XDMAC Channel 14 Disable Bit
bits : 14 - 14 (1 bit)

DI15 : XDMAC Channel 15 Disable Bit
bits : 15 - 15 (1 bit)

DI16 : XDMAC Channel 16 Disable Bit
bits : 16 - 16 (1 bit)

DI17 : XDMAC Channel 17 Disable Bit
bits : 17 - 17 (1 bit)

DI18 : XDMAC Channel 18 Disable Bit
bits : 18 - 18 (1 bit)

DI19 : XDMAC Channel 19 Disable Bit
bits : 19 - 19 (1 bit)

DI20 : XDMAC Channel 20 Disable Bit
bits : 20 - 20 (1 bit)

DI21 : XDMAC Channel 21 Disable Bit
bits : 21 - 21 (1 bit)

DI22 : XDMAC Channel 22 Disable Bit
bits : 22 - 22 (1 bit)

DI23 : XDMAC Channel 23 Disable Bit
bits : 23 - 23 (1 bit)

CUBC

Channel Microblock Control Register (chid = 0)
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)

CSUS6

Channel Source Microblock Stride (chid = 6)
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CDUS6

Channel Destination Microblock Stride (chid = 6)
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CIE7

Channel Interrupt Enable Register (chid = 7)
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only

CID7

Channel Interrupt Disable Register (chid = 7)
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only

CIM7

Channel Interrupt Mask Register (chid = 7)
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : write-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : write-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : write-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : write-only

CIS7

Channel Interrupt Status Register (chid = 7)
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only

CSA7

Channel Source Address Register (chid = 7)
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write

CDA7

Channel Destination Address Register (chid = 7)
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write

CNDA7

Channel Next Descriptor Address Register (chid = 7)
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write

CNDC7

Channel Next Descriptor Control Register (chid = 7)
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.

CUBC7

Channel Microblock Control Register (chid = 7)
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write

CBC7

Channel Block Control Register (chid = 7)
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write

CC7

Channel Configuration Register (chid = 7)
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self triggered mode (Memory to Memory Transfer).

1 : PER_TRAN

Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral to Memory transfer.

1 : MEM2PER

Memory to Peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : TERMINATED

Channel initialization is in progress.

1 : IN_PROGRESS

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active write transaction on the bus.

1 : IN_PROGRESS

A Write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write

CDS_MSP7

Channel Data Stride Memory Set Pattern (chid = 7)
address_offset : 0x23C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write

GS

Global Channel Status Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ST0 : XDMAC Channel 0 Status Bit
bits : 0 - 0 (1 bit)

ST1 : XDMAC Channel 1 Status Bit
bits : 1 - 1 (1 bit)

ST2 : XDMAC Channel 2 Status Bit
bits : 2 - 2 (1 bit)

ST3 : XDMAC Channel 3 Status Bit
bits : 3 - 3 (1 bit)

ST4 : XDMAC Channel 4 Status Bit
bits : 4 - 4 (1 bit)

ST5 : XDMAC Channel 5 Status Bit
bits : 5 - 5 (1 bit)

ST6 : XDMAC Channel 6 Status Bit
bits : 6 - 6 (1 bit)

ST7 : XDMAC Channel 7 Status Bit
bits : 7 - 7 (1 bit)

ST8 : XDMAC Channel 8 Status Bit
bits : 8 - 8 (1 bit)

ST9 : XDMAC Channel 9 Status Bit
bits : 9 - 9 (1 bit)

ST10 : XDMAC Channel 10 Status Bit
bits : 10 - 10 (1 bit)

ST11 : XDMAC Channel 11 Status Bit
bits : 11 - 11 (1 bit)

ST12 : XDMAC Channel 12 Status Bit
bits : 12 - 12 (1 bit)

ST13 : XDMAC Channel 13 Status Bit
bits : 13 - 13 (1 bit)

ST14 : XDMAC Channel 14 Status Bit
bits : 14 - 14 (1 bit)

ST15 : XDMAC Channel 15 Status Bit
bits : 15 - 15 (1 bit)

ST16 : XDMAC Channel 16 Status Bit
bits : 16 - 16 (1 bit)

ST17 : XDMAC Channel 17 Status Bit
bits : 17 - 17 (1 bit)

ST18 : XDMAC Channel 18 Status Bit
bits : 18 - 18 (1 bit)

ST19 : XDMAC Channel 19 Status Bit
bits : 19 - 19 (1 bit)

ST20 : XDMAC Channel 20 Status Bit
bits : 20 - 20 (1 bit)

ST21 : XDMAC Channel 21 Status Bit
bits : 21 - 21 (1 bit)

ST22 : XDMAC Channel 22 Status Bit
bits : 22 - 22 (1 bit)

ST23 : XDMAC Channel 23 Status Bit
bits : 23 - 23 (1 bit)

CBC

Channel Block Control Register (chid = 0)
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)

CSUS7

Channel Source Microblock Stride (chid = 7)
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CDUS7

Channel Destination Microblock Stride (chid = 7)
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CIE8

Channel Interrupt Enable Register (chid = 8)
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only

CID8

Channel Interrupt Disable Register (chid = 8)
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only

CIM8

Channel Interrupt Mask Register (chid = 8)
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : write-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : write-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : write-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : write-only

CIS8

Channel Interrupt Status Register (chid = 8)
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only

CSA8

Channel Source Address Register (chid = 8)
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write

CDA8

Channel Destination Address Register (chid = 8)
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write

CNDA8

Channel Next Descriptor Address Register (chid = 8)
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write

CNDC8

Channel Next Descriptor Control Register (chid = 8)
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.

CUBC8

Channel Microblock Control Register (chid = 8)
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write

CBC8

Channel Block Control Register (chid = 8)
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write

CC8

Channel Configuration Register (chid = 8)
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self triggered mode (Memory to Memory Transfer).

1 : PER_TRAN

Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral to Memory transfer.

1 : MEM2PER

Memory to Peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : TERMINATED

Channel initialization is in progress.

1 : IN_PROGRESS

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active write transaction on the bus.

1 : IN_PROGRESS

A Write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write

CDS_MSP8

Channel Data Stride Memory Set Pattern (chid = 8)
address_offset : 0x27C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write

GRS

Global Channel Read Suspend Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RS0 : XDMAC Channel 0 Read Suspend Bit
bits : 0 - 0 (1 bit)

RS1 : XDMAC Channel 1 Read Suspend Bit
bits : 1 - 1 (1 bit)

RS2 : XDMAC Channel 2 Read Suspend Bit
bits : 2 - 2 (1 bit)

RS3 : XDMAC Channel 3 Read Suspend Bit
bits : 3 - 3 (1 bit)

RS4 : XDMAC Channel 4 Read Suspend Bit
bits : 4 - 4 (1 bit)

RS5 : XDMAC Channel 5 Read Suspend Bit
bits : 5 - 5 (1 bit)

RS6 : XDMAC Channel 6 Read Suspend Bit
bits : 6 - 6 (1 bit)

RS7 : XDMAC Channel 7 Read Suspend Bit
bits : 7 - 7 (1 bit)

RS8 : XDMAC Channel 8 Read Suspend Bit
bits : 8 - 8 (1 bit)

RS9 : XDMAC Channel 9 Read Suspend Bit
bits : 9 - 9 (1 bit)

RS10 : XDMAC Channel 10 Read Suspend Bit
bits : 10 - 10 (1 bit)

RS11 : XDMAC Channel 11 Read Suspend Bit
bits : 11 - 11 (1 bit)

RS12 : XDMAC Channel 12 Read Suspend Bit
bits : 12 - 12 (1 bit)

RS13 : XDMAC Channel 13 Read Suspend Bit
bits : 13 - 13 (1 bit)

RS14 : XDMAC Channel 14 Read Suspend Bit
bits : 14 - 14 (1 bit)

RS15 : XDMAC Channel 15 Read Suspend Bit
bits : 15 - 15 (1 bit)

RS16 : XDMAC Channel 16 Read Suspend Bit
bits : 16 - 16 (1 bit)

RS17 : XDMAC Channel 17 Read Suspend Bit
bits : 17 - 17 (1 bit)

RS18 : XDMAC Channel 18 Read Suspend Bit
bits : 18 - 18 (1 bit)

RS19 : XDMAC Channel 19 Read Suspend Bit
bits : 19 - 19 (1 bit)

RS20 : XDMAC Channel 20 Read Suspend Bit
bits : 20 - 20 (1 bit)

RS21 : XDMAC Channel 21 Read Suspend Bit
bits : 21 - 21 (1 bit)

RS22 : XDMAC Channel 22 Read Suspend Bit
bits : 22 - 22 (1 bit)

RS23 : XDMAC Channel 23 Read Suspend Bit
bits : 23 - 23 (1 bit)

CC

Channel Configuration Register (chid = 0)
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)

Enumeration: TYPESelect

0 : MEM_TRAN

Self triggered mode (Memory to Memory Transfer).

1 : PER_TRAN

Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)

Enumeration: MBSIZESelect

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)

Enumeration: DSYNCSelect

0 : PER2MEM

Peripheral to Memory transfer.

1 : MEM2PER

Memory to Peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)

Enumeration: SWREQSelect

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)

Enumeration: MEMSETSelect

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)

Enumeration: CSIZESelect

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)

Enumeration: DWIDTHSelect

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)

Enumeration: SIFSelect

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)

Enumeration: DIFSelect

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)

Enumeration: SAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)

Enumeration: DAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)

Enumeration: INITDSelect

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)

Enumeration: RDIPSelect

0 : DONE

No Active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)

Enumeration: WRIPSelect

0 : DONE

No Active write transaction on the bus.

1 : IN_PROGRESS

A Write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)

CSUS8

Channel Source Microblock Stride (chid = 8)
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CDUS8

Channel Destination Microblock Stride (chid = 8)
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CIE9

Channel Interrupt Enable Register (chid = 9)
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only

CID9

Channel Interrupt Disable Register (chid = 9)
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only

CIM9

Channel Interrupt Mask Register (chid = 9)
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : write-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : write-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : write-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : write-only

CIS9

Channel Interrupt Status Register (chid = 9)
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only

CSA9

Channel Source Address Register (chid = 9)
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write

CDA9

Channel Destination Address Register (chid = 9)
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write

CNDA9

Channel Next Descriptor Address Register (chid = 9)
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write

CNDC9

Channel Next Descriptor Control Register (chid = 9)
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.

CUBC9

Channel Microblock Control Register (chid = 9)
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write

CBC9

Channel Block Control Register (chid = 9)
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write

CC9

Channel Configuration Register (chid = 9)
address_offset : 0x2B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self triggered mode (Memory to Memory Transfer).

1 : PER_TRAN

Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral to Memory transfer.

1 : MEM2PER

Memory to Peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : TERMINATED

Channel initialization is in progress.

1 : IN_PROGRESS

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active write transaction on the bus.

1 : IN_PROGRESS

A Write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write

CDS_MSP9

Channel Data Stride Memory Set Pattern (chid = 9)
address_offset : 0x2BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write

GWS

Global Channel Write Suspend Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WS0 : XDMAC Channel 0 Write Suspend Bit
bits : 0 - 0 (1 bit)

WS1 : XDMAC Channel 1 Write Suspend Bit
bits : 1 - 1 (1 bit)

WS2 : XDMAC Channel 2 Write Suspend Bit
bits : 2 - 2 (1 bit)

WS3 : XDMAC Channel 3 Write Suspend Bit
bits : 3 - 3 (1 bit)

WS4 : XDMAC Channel 4 Write Suspend Bit
bits : 4 - 4 (1 bit)

WS5 : XDMAC Channel 5 Write Suspend Bit
bits : 5 - 5 (1 bit)

WS6 : XDMAC Channel 6 Write Suspend Bit
bits : 6 - 6 (1 bit)

WS7 : XDMAC Channel 7 Write Suspend Bit
bits : 7 - 7 (1 bit)

WS8 : XDMAC Channel 8 Write Suspend Bit
bits : 8 - 8 (1 bit)

WS9 : XDMAC Channel 9 Write Suspend Bit
bits : 9 - 9 (1 bit)

WS10 : XDMAC Channel 10 Write Suspend Bit
bits : 10 - 10 (1 bit)

WS11 : XDMAC Channel 11 Write Suspend Bit
bits : 11 - 11 (1 bit)

WS12 : XDMAC Channel 12 Write Suspend Bit
bits : 12 - 12 (1 bit)

WS13 : XDMAC Channel 13 Write Suspend Bit
bits : 13 - 13 (1 bit)

WS14 : XDMAC Channel 14 Write Suspend Bit
bits : 14 - 14 (1 bit)

WS15 : XDMAC Channel 15 Write Suspend Bit
bits : 15 - 15 (1 bit)

WS16 : XDMAC Channel 16 Write Suspend Bit
bits : 16 - 16 (1 bit)

WS17 : XDMAC Channel 17 Write Suspend Bit
bits : 17 - 17 (1 bit)

WS18 : XDMAC Channel 18 Write Suspend Bit
bits : 18 - 18 (1 bit)

WS19 : XDMAC Channel 19 Write Suspend Bit
bits : 19 - 19 (1 bit)

WS20 : XDMAC Channel 20 Write Suspend Bit
bits : 20 - 20 (1 bit)

WS21 : XDMAC Channel 21 Write Suspend Bit
bits : 21 - 21 (1 bit)

WS22 : XDMAC Channel 22 Write Suspend Bit
bits : 22 - 22 (1 bit)

WS23 : XDMAC Channel 23 Write Suspend Bit
bits : 23 - 23 (1 bit)

CDS_MSP

Channel Data Stride Memory Set Pattern (chid = 0)
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)

CSUS9

Channel Source Microblock Stride (chid = 9)
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CDUS9

Channel Destination Microblock Stride (chid = 9)
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CIE10

Channel Interrupt Enable Register (chid = 10)
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only

CID10

Channel Interrupt Disable Register (chid = 10)
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only

CIM10

Channel Interrupt Mask Register (chid = 10)
address_offset : 0x2D8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : write-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : write-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : write-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : write-only

CIS10

Channel Interrupt Status Register (chid = 10)
address_offset : 0x2DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only

CSA10

Channel Source Address Register (chid = 10)
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write

CDA10

Channel Destination Address Register (chid = 10)
address_offset : 0x2E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write

CNDA10

Channel Next Descriptor Address Register (chid = 10)
address_offset : 0x2E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write

CNDC10

Channel Next Descriptor Control Register (chid = 10)
address_offset : 0x2EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.

CUBC10

Channel Microblock Control Register (chid = 10)
address_offset : 0x2F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write

CBC10

Channel Block Control Register (chid = 10)
address_offset : 0x2F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write

CC10

Channel Configuration Register (chid = 10)
address_offset : 0x2F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self triggered mode (Memory to Memory Transfer).

1 : PER_TRAN

Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral to Memory transfer.

1 : MEM2PER

Memory to Peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : TERMINATED

Channel initialization is in progress.

1 : IN_PROGRESS

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active write transaction on the bus.

1 : IN_PROGRESS

A Write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write

CDS_MSP10

Channel Data Stride Memory Set Pattern (chid = 10)
address_offset : 0x2FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write

GRWS

Global Channel Read Write Suspend Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

RWS0 : XDMAC Channel 0 Read Write Suspend Bit
bits : 0 - 0 (1 bit)

RWS1 : XDMAC Channel 1 Read Write Suspend Bit
bits : 1 - 1 (1 bit)

RWS2 : XDMAC Channel 2 Read Write Suspend Bit
bits : 2 - 2 (1 bit)

RWS3 : XDMAC Channel 3 Read Write Suspend Bit
bits : 3 - 3 (1 bit)

RWS4 : XDMAC Channel 4 Read Write Suspend Bit
bits : 4 - 4 (1 bit)

RWS5 : XDMAC Channel 5 Read Write Suspend Bit
bits : 5 - 5 (1 bit)

RWS6 : XDMAC Channel 6 Read Write Suspend Bit
bits : 6 - 6 (1 bit)

RWS7 : XDMAC Channel 7 Read Write Suspend Bit
bits : 7 - 7 (1 bit)

RWS8 : XDMAC Channel 8 Read Write Suspend Bit
bits : 8 - 8 (1 bit)

RWS9 : XDMAC Channel 9 Read Write Suspend Bit
bits : 9 - 9 (1 bit)

RWS10 : XDMAC Channel 10 Read Write Suspend Bit
bits : 10 - 10 (1 bit)

RWS11 : XDMAC Channel 11 Read Write Suspend Bit
bits : 11 - 11 (1 bit)

RWS12 : XDMAC Channel 12 Read Write Suspend Bit
bits : 12 - 12 (1 bit)

RWS13 : XDMAC Channel 13 Read Write Suspend Bit
bits : 13 - 13 (1 bit)

RWS14 : XDMAC Channel 14 Read Write Suspend Bit
bits : 14 - 14 (1 bit)

RWS15 : XDMAC Channel 15 Read Write Suspend Bit
bits : 15 - 15 (1 bit)

RWS16 : XDMAC Channel 16 Read Write Suspend Bit
bits : 16 - 16 (1 bit)

RWS17 : XDMAC Channel 17 Read Write Suspend Bit
bits : 17 - 17 (1 bit)

RWS18 : XDMAC Channel 18 Read Write Suspend Bit
bits : 18 - 18 (1 bit)

RWS19 : XDMAC Channel 19 Read Write Suspend Bit
bits : 19 - 19 (1 bit)

RWS20 : XDMAC Channel 20 Read Write Suspend Bit
bits : 20 - 20 (1 bit)

RWS21 : XDMAC Channel 21 Read Write Suspend Bit
bits : 21 - 21 (1 bit)

RWS22 : XDMAC Channel 22 Read Write Suspend Bit
bits : 22 - 22 (1 bit)

RWS23 : XDMAC Channel 23 Read Write Suspend Bit
bits : 23 - 23 (1 bit)

CSUS

Channel Source Microblock Stride (chid = 0)
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)

CSUS10

Channel Source Microblock Stride (chid = 10)
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CDUS10

Channel Destination Microblock Stride (chid = 10)
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CIE11

Channel Interrupt Enable Register (chid = 11)
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only

CID11

Channel Interrupt Disable Register (chid = 11)
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only

CIM11

Channel Interrupt Mask Register (chid = 11)
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : write-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : write-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : write-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : write-only

CIS11

Channel Interrupt Status Register (chid = 11)
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only

CSA11

Channel Source Address Register (chid = 11)
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write

CDA11

Channel Destination Address Register (chid = 11)
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write

CNDA11

Channel Next Descriptor Address Register (chid = 11)
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write

CNDC11

Channel Next Descriptor Control Register (chid = 11)
address_offset : 0x32C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.

CUBC11

Channel Microblock Control Register (chid = 11)
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write

CBC11

Channel Block Control Register (chid = 11)
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write

CC11

Channel Configuration Register (chid = 11)
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self triggered mode (Memory to Memory Transfer).

1 : PER_TRAN

Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral to Memory transfer.

1 : MEM2PER

Memory to Peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : TERMINATED

Channel initialization is in progress.

1 : IN_PROGRESS

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active write transaction on the bus.

1 : IN_PROGRESS

A Write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write

CDS_MSP11

Channel Data Stride Memory Set Pattern (chid = 11)
address_offset : 0x33C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write

GRWR

Global Channel Read Write Resume Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

RWR0 : XDMAC Channel 0 Read Write Resume Bit
bits : 0 - 0 (1 bit)

RWR1 : XDMAC Channel 1 Read Write Resume Bit
bits : 1 - 1 (1 bit)

RWR2 : XDMAC Channel 2 Read Write Resume Bit
bits : 2 - 2 (1 bit)

RWR3 : XDMAC Channel 3 Read Write Resume Bit
bits : 3 - 3 (1 bit)

RWR4 : XDMAC Channel 4 Read Write Resume Bit
bits : 4 - 4 (1 bit)

RWR5 : XDMAC Channel 5 Read Write Resume Bit
bits : 5 - 5 (1 bit)

RWR6 : XDMAC Channel 6 Read Write Resume Bit
bits : 6 - 6 (1 bit)

RWR7 : XDMAC Channel 7 Read Write Resume Bit
bits : 7 - 7 (1 bit)

RWR8 : XDMAC Channel 8 Read Write Resume Bit
bits : 8 - 8 (1 bit)

RWR9 : XDMAC Channel 9 Read Write Resume Bit
bits : 9 - 9 (1 bit)

RWR10 : XDMAC Channel 10 Read Write Resume Bit
bits : 10 - 10 (1 bit)

RWR11 : XDMAC Channel 11 Read Write Resume Bit
bits : 11 - 11 (1 bit)

RWR12 : XDMAC Channel 12 Read Write Resume Bit
bits : 12 - 12 (1 bit)

RWR13 : XDMAC Channel 13 Read Write Resume Bit
bits : 13 - 13 (1 bit)

RWR14 : XDMAC Channel 14 Read Write Resume Bit
bits : 14 - 14 (1 bit)

RWR15 : XDMAC Channel 15 Read Write Resume Bit
bits : 15 - 15 (1 bit)

RWR16 : XDMAC Channel 16 Read Write Resume Bit
bits : 16 - 16 (1 bit)

RWR17 : XDMAC Channel 17 Read Write Resume Bit
bits : 17 - 17 (1 bit)

RWR18 : XDMAC Channel 18 Read Write Resume Bit
bits : 18 - 18 (1 bit)

RWR19 : XDMAC Channel 19 Read Write Resume Bit
bits : 19 - 19 (1 bit)

RWR20 : XDMAC Channel 20 Read Write Resume Bit
bits : 20 - 20 (1 bit)

RWR21 : XDMAC Channel 21 Read Write Resume Bit
bits : 21 - 21 (1 bit)

RWR22 : XDMAC Channel 22 Read Write Resume Bit
bits : 22 - 22 (1 bit)

RWR23 : XDMAC Channel 23 Read Write Resume Bit
bits : 23 - 23 (1 bit)

CDUS

Channel Destination Microblock Stride (chid = 0)
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)

CSUS11

Channel Source Microblock Stride (chid = 11)
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CDUS11

Channel Destination Microblock Stride (chid = 11)
address_offset : 0x344 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CIE12

Channel Interrupt Enable Register (chid = 12)
address_offset : 0x350 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only

CID12

Channel Interrupt Disable Register (chid = 12)
address_offset : 0x354 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only

CIM12

Channel Interrupt Mask Register (chid = 12)
address_offset : 0x358 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : write-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : write-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : write-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : write-only

CIS12

Channel Interrupt Status Register (chid = 12)
address_offset : 0x35C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only

CSA12

Channel Source Address Register (chid = 12)
address_offset : 0x360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write

CDA12

Channel Destination Address Register (chid = 12)
address_offset : 0x364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write

CNDA12

Channel Next Descriptor Address Register (chid = 12)
address_offset : 0x368 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write

CNDC12

Channel Next Descriptor Control Register (chid = 12)
address_offset : 0x36C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.

CUBC12

Channel Microblock Control Register (chid = 12)
address_offset : 0x370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write

CBC12

Channel Block Control Register (chid = 12)
address_offset : 0x374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write

CC12

Channel Configuration Register (chid = 12)
address_offset : 0x378 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self triggered mode (Memory to Memory Transfer).

1 : PER_TRAN

Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral to Memory transfer.

1 : MEM2PER

Memory to Peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : TERMINATED

Channel initialization is in progress.

1 : IN_PROGRESS

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active write transaction on the bus.

1 : IN_PROGRESS

A Write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write

CDS_MSP12

Channel Data Stride Memory Set Pattern (chid = 12)
address_offset : 0x37C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write

GSWR

Global Channel Software Request Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SWREQ0 : XDMAC Channel 0 Software Request Bit
bits : 0 - 0 (1 bit)

SWREQ1 : XDMAC Channel 1 Software Request Bit
bits : 1 - 1 (1 bit)

SWREQ2 : XDMAC Channel 2 Software Request Bit
bits : 2 - 2 (1 bit)

SWREQ3 : XDMAC Channel 3 Software Request Bit
bits : 3 - 3 (1 bit)

SWREQ4 : XDMAC Channel 4 Software Request Bit
bits : 4 - 4 (1 bit)

SWREQ5 : XDMAC Channel 5 Software Request Bit
bits : 5 - 5 (1 bit)

SWREQ6 : XDMAC Channel 6 Software Request Bit
bits : 6 - 6 (1 bit)

SWREQ7 : XDMAC Channel 7 Software Request Bit
bits : 7 - 7 (1 bit)

SWREQ8 : XDMAC Channel 8 Software Request Bit
bits : 8 - 8 (1 bit)

SWREQ9 : XDMAC Channel 9 Software Request Bit
bits : 9 - 9 (1 bit)

SWREQ10 : XDMAC Channel 10 Software Request Bit
bits : 10 - 10 (1 bit)

SWREQ11 : XDMAC Channel 11 Software Request Bit
bits : 11 - 11 (1 bit)

SWREQ12 : XDMAC Channel 12 Software Request Bit
bits : 12 - 12 (1 bit)

SWREQ13 : XDMAC Channel 13 Software Request Bit
bits : 13 - 13 (1 bit)

SWREQ14 : XDMAC Channel 14 Software Request Bit
bits : 14 - 14 (1 bit)

SWREQ15 : XDMAC Channel 15 Software Request Bit
bits : 15 - 15 (1 bit)

SWREQ16 : XDMAC Channel 16 Software Request Bit
bits : 16 - 16 (1 bit)

SWREQ17 : XDMAC Channel 17 Software Request Bit
bits : 17 - 17 (1 bit)

SWREQ18 : XDMAC Channel 18 Software Request Bit
bits : 18 - 18 (1 bit)

SWREQ19 : XDMAC Channel 19 Software Request Bit
bits : 19 - 19 (1 bit)

SWREQ20 : XDMAC Channel 20 Software Request Bit
bits : 20 - 20 (1 bit)

SWREQ21 : XDMAC Channel 21 Software Request Bit
bits : 21 - 21 (1 bit)

SWREQ22 : XDMAC Channel 22 Software Request Bit
bits : 22 - 22 (1 bit)

SWREQ23 : XDMAC Channel 23 Software Request Bit
bits : 23 - 23 (1 bit)

CSUS12

Channel Source Microblock Stride (chid = 12)
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CDUS12

Channel Destination Microblock Stride (chid = 12)
address_offset : 0x384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CIE13

Channel Interrupt Enable Register (chid = 13)
address_offset : 0x390 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only

CID13

Channel Interrupt Disable Register (chid = 13)
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only

CIM13

Channel Interrupt Mask Register (chid = 13)
address_offset : 0x398 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : write-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : write-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : write-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : write-only

CIS13

Channel Interrupt Status Register (chid = 13)
address_offset : 0x39C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only

CSA13

Channel Source Address Register (chid = 13)
address_offset : 0x3A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write

CDA13

Channel Destination Address Register (chid = 13)
address_offset : 0x3A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write

CNDA13

Channel Next Descriptor Address Register (chid = 13)
address_offset : 0x3A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write

CNDC13

Channel Next Descriptor Control Register (chid = 13)
address_offset : 0x3AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.

CUBC13

Channel Microblock Control Register (chid = 13)
address_offset : 0x3B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write

CBC13

Channel Block Control Register (chid = 13)
address_offset : 0x3B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write

CC13

Channel Configuration Register (chid = 13)
address_offset : 0x3B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self triggered mode (Memory to Memory Transfer).

1 : PER_TRAN

Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral to Memory transfer.

1 : MEM2PER

Memory to Peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : TERMINATED

Channel initialization is in progress.

1 : IN_PROGRESS

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active write transaction on the bus.

1 : IN_PROGRESS

A Write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write

CDS_MSP13

Channel Data Stride Memory Set Pattern (chid = 13)
address_offset : 0x3BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write

GSWS

Global Channel Software Request Status Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SWRS0 : XDMAC Channel 0 Software Request Status Bit
bits : 0 - 0 (1 bit)

SWRS1 : XDMAC Channel 1 Software Request Status Bit
bits : 1 - 1 (1 bit)

SWRS2 : XDMAC Channel 2 Software Request Status Bit
bits : 2 - 2 (1 bit)

SWRS3 : XDMAC Channel 3 Software Request Status Bit
bits : 3 - 3 (1 bit)

SWRS4 : XDMAC Channel 4 Software Request Status Bit
bits : 4 - 4 (1 bit)

SWRS5 : XDMAC Channel 5 Software Request Status Bit
bits : 5 - 5 (1 bit)

SWRS6 : XDMAC Channel 6 Software Request Status Bit
bits : 6 - 6 (1 bit)

SWRS7 : XDMAC Channel 7 Software Request Status Bit
bits : 7 - 7 (1 bit)

SWRS8 : XDMAC Channel 8 Software Request Status Bit
bits : 8 - 8 (1 bit)

SWRS9 : XDMAC Channel 9 Software Request Status Bit
bits : 9 - 9 (1 bit)

SWRS10 : XDMAC Channel 10 Software Request Status Bit
bits : 10 - 10 (1 bit)

SWRS11 : XDMAC Channel 11 Software Request Status Bit
bits : 11 - 11 (1 bit)

SWRS12 : XDMAC Channel 12 Software Request Status Bit
bits : 12 - 12 (1 bit)

SWRS13 : XDMAC Channel 13 Software Request Status Bit
bits : 13 - 13 (1 bit)

SWRS14 : XDMAC Channel 14 Software Request Status Bit
bits : 14 - 14 (1 bit)

SWRS15 : XDMAC Channel 15 Software Request Status Bit
bits : 15 - 15 (1 bit)

SWRS16 : XDMAC Channel 16 Software Request Status Bit
bits : 16 - 16 (1 bit)

SWRS17 : XDMAC Channel 17 Software Request Status Bit
bits : 17 - 17 (1 bit)

SWRS18 : XDMAC Channel 18 Software Request Status Bit
bits : 18 - 18 (1 bit)

SWRS19 : XDMAC Channel 19 Software Request Status Bit
bits : 19 - 19 (1 bit)

SWRS20 : XDMAC Channel 20 Software Request Status Bit
bits : 20 - 20 (1 bit)

SWRS21 : XDMAC Channel 21 Software Request Status Bit
bits : 21 - 21 (1 bit)

SWRS22 : XDMAC Channel 22 Software Request Status Bit
bits : 22 - 22 (1 bit)

SWRS23 : XDMAC Channel 23 Software Request Status Bit
bits : 23 - 23 (1 bit)

CSUS13

Channel Source Microblock Stride (chid = 13)
address_offset : 0x3C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CDUS13

Channel Destination Microblock Stride (chid = 13)
address_offset : 0x3C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CIE14

Channel Interrupt Enable Register (chid = 14)
address_offset : 0x3D0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only

CID14

Channel Interrupt Disable Register (chid = 14)
address_offset : 0x3D4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only

CIM14

Channel Interrupt Mask Register (chid = 14)
address_offset : 0x3D8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : write-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : write-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : write-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : write-only

CIS14

Channel Interrupt Status Register (chid = 14)
address_offset : 0x3DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only

CSA14

Channel Source Address Register (chid = 14)
address_offset : 0x3E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write

CDA14

Channel Destination Address Register (chid = 14)
address_offset : 0x3E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write

CNDA14

Channel Next Descriptor Address Register (chid = 14)
address_offset : 0x3E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write

CNDC14

Channel Next Descriptor Control Register (chid = 14)
address_offset : 0x3EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.

CUBC14

Channel Microblock Control Register (chid = 14)
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write

CBC14

Channel Block Control Register (chid = 14)
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write

CC14

Channel Configuration Register (chid = 14)
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self triggered mode (Memory to Memory Transfer).

1 : PER_TRAN

Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral to Memory transfer.

1 : MEM2PER

Memory to Peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : TERMINATED

Channel initialization is in progress.

1 : IN_PROGRESS

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active write transaction on the bus.

1 : IN_PROGRESS

A Write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write

CDS_MSP14

Channel Data Stride Memory Set Pattern (chid = 14)
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write

GCFG

Global Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CGDISREG : Configuration Registers Clock Gating Disable
bits : 0 - 0 (1 bit)

CGDISPIPE : Pipeline Clock Gating Disable
bits : 1 - 1 (1 bit)

CGDISFIFO : FIFO Clock Gating Disable
bits : 2 - 2 (1 bit)

CGDISIF : Bus Interface Clock Gating Disable
bits : 3 - 3 (1 bit)

BXKBEN : Boundary X Kilobyte Enable
bits : 8 - 8 (1 bit)

CID

Channel Interrupt Disable Register (chid = 0)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)

GSWF

Global Channel Software Flush Request Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SWF0 : XDMAC Channel 0 Software Flush Request Bit
bits : 0 - 0 (1 bit)

SWF1 : XDMAC Channel 1 Software Flush Request Bit
bits : 1 - 1 (1 bit)

SWF2 : XDMAC Channel 2 Software Flush Request Bit
bits : 2 - 2 (1 bit)

SWF3 : XDMAC Channel 3 Software Flush Request Bit
bits : 3 - 3 (1 bit)

SWF4 : XDMAC Channel 4 Software Flush Request Bit
bits : 4 - 4 (1 bit)

SWF5 : XDMAC Channel 5 Software Flush Request Bit
bits : 5 - 5 (1 bit)

SWF6 : XDMAC Channel 6 Software Flush Request Bit
bits : 6 - 6 (1 bit)

SWF7 : XDMAC Channel 7 Software Flush Request Bit
bits : 7 - 7 (1 bit)

SWF8 : XDMAC Channel 8 Software Flush Request Bit
bits : 8 - 8 (1 bit)

SWF9 : XDMAC Channel 9 Software Flush Request Bit
bits : 9 - 9 (1 bit)

SWF10 : XDMAC Channel 10 Software Flush Request Bit
bits : 10 - 10 (1 bit)

SWF11 : XDMAC Channel 11 Software Flush Request Bit
bits : 11 - 11 (1 bit)

SWF12 : XDMAC Channel 12 Software Flush Request Bit
bits : 12 - 12 (1 bit)

SWF13 : XDMAC Channel 13 Software Flush Request Bit
bits : 13 - 13 (1 bit)

SWF14 : XDMAC Channel 14 Software Flush Request Bit
bits : 14 - 14 (1 bit)

SWF15 : XDMAC Channel 15 Software Flush Request Bit
bits : 15 - 15 (1 bit)

SWF16 : XDMAC Channel 16 Software Flush Request Bit
bits : 16 - 16 (1 bit)

SWF17 : XDMAC Channel 17 Software Flush Request Bit
bits : 17 - 17 (1 bit)

SWF18 : XDMAC Channel 18 Software Flush Request Bit
bits : 18 - 18 (1 bit)

SWF19 : XDMAC Channel 19 Software Flush Request Bit
bits : 19 - 19 (1 bit)

SWF20 : XDMAC Channel 20 Software Flush Request Bit
bits : 20 - 20 (1 bit)

SWF21 : XDMAC Channel 21 Software Flush Request Bit
bits : 21 - 21 (1 bit)

SWF22 : XDMAC Channel 22 Software Flush Request Bit
bits : 22 - 22 (1 bit)

SWF23 : XDMAC Channel 23 Software Flush Request Bit
bits : 23 - 23 (1 bit)

CSUS14

Channel Source Microblock Stride (chid = 14)
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CDUS14

Channel Destination Microblock Stride (chid = 14)
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CIE15

Channel Interrupt Enable Register (chid = 15)
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only

CID15

Channel Interrupt Disable Register (chid = 15)
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only

CIM15

Channel Interrupt Mask Register (chid = 15)
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : write-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : write-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : write-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : write-only

CIS15

Channel Interrupt Status Register (chid = 15)
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only

CSA15

Channel Source Address Register (chid = 15)
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write

CDA15

Channel Destination Address Register (chid = 15)
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write

CNDA15

Channel Next Descriptor Address Register (chid = 15)
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write

CNDC15

Channel Next Descriptor Control Register (chid = 15)
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.

CUBC15

Channel Microblock Control Register (chid = 15)
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write

CBC15

Channel Block Control Register (chid = 15)
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write

CC15

Channel Configuration Register (chid = 15)
address_offset : 0x438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self triggered mode (Memory to Memory Transfer).

1 : PER_TRAN

Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral to Memory transfer.

1 : MEM2PER

Memory to Peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : TERMINATED

Channel initialization is in progress.

1 : IN_PROGRESS

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active write transaction on the bus.

1 : IN_PROGRESS

A Write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write

CDS_MSP15

Channel Data Stride Memory Set Pattern (chid = 15)
address_offset : 0x43C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write

CSUS15

Channel Source Microblock Stride (chid = 15)
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CDUS15

Channel Destination Microblock Stride (chid = 15)
address_offset : 0x444 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CIE16

Channel Interrupt Enable Register (chid = 16)
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only

CID16

Channel Interrupt Disable Register (chid = 16)
address_offset : 0x454 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only

CIM16

Channel Interrupt Mask Register (chid = 16)
address_offset : 0x458 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : write-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : write-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : write-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : write-only

CIS16

Channel Interrupt Status Register (chid = 16)
address_offset : 0x45C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only

CSA16

Channel Source Address Register (chid = 16)
address_offset : 0x460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write

CDA16

Channel Destination Address Register (chid = 16)
address_offset : 0x464 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write

CNDA16

Channel Next Descriptor Address Register (chid = 16)
address_offset : 0x468 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write

CNDC16

Channel Next Descriptor Control Register (chid = 16)
address_offset : 0x46C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.

CUBC16

Channel Microblock Control Register (chid = 16)
address_offset : 0x470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write

CBC16

Channel Block Control Register (chid = 16)
address_offset : 0x474 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write

CC16

Channel Configuration Register (chid = 16)
address_offset : 0x478 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self triggered mode (Memory to Memory Transfer).

1 : PER_TRAN

Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral to Memory transfer.

1 : MEM2PER

Memory to Peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : TERMINATED

Channel initialization is in progress.

1 : IN_PROGRESS

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active write transaction on the bus.

1 : IN_PROGRESS

A Write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write

CDS_MSP16

Channel Data Stride Memory Set Pattern (chid = 16)
address_offset : 0x47C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write

CSUS16

Channel Source Microblock Stride (chid = 16)
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CDUS16

Channel Destination Microblock Stride (chid = 16)
address_offset : 0x484 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CIE17

Channel Interrupt Enable Register (chid = 17)
address_offset : 0x490 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only

CID17

Channel Interrupt Disable Register (chid = 17)
address_offset : 0x494 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only

CIM17

Channel Interrupt Mask Register (chid = 17)
address_offset : 0x498 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : write-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : write-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : write-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : write-only

CIS17

Channel Interrupt Status Register (chid = 17)
address_offset : 0x49C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only

CSA17

Channel Source Address Register (chid = 17)
address_offset : 0x4A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write

CDA17

Channel Destination Address Register (chid = 17)
address_offset : 0x4A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write

CNDA17

Channel Next Descriptor Address Register (chid = 17)
address_offset : 0x4A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write

CNDC17

Channel Next Descriptor Control Register (chid = 17)
address_offset : 0x4AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.

CUBC17

Channel Microblock Control Register (chid = 17)
address_offset : 0x4B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write

CBC17

Channel Block Control Register (chid = 17)
address_offset : 0x4B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write

CC17

Channel Configuration Register (chid = 17)
address_offset : 0x4B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self triggered mode (Memory to Memory Transfer).

1 : PER_TRAN

Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral to Memory transfer.

1 : MEM2PER

Memory to Peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : TERMINATED

Channel initialization is in progress.

1 : IN_PROGRESS

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active write transaction on the bus.

1 : IN_PROGRESS

A Write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write

CDS_MSP17

Channel Data Stride Memory Set Pattern (chid = 17)
address_offset : 0x4BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write

CSUS17

Channel Source Microblock Stride (chid = 17)
address_offset : 0x4C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CDUS17

Channel Destination Microblock Stride (chid = 17)
address_offset : 0x4C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CIE18

Channel Interrupt Enable Register (chid = 18)
address_offset : 0x4D0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only

CID18

Channel Interrupt Disable Register (chid = 18)
address_offset : 0x4D4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only

CIM18

Channel Interrupt Mask Register (chid = 18)
address_offset : 0x4D8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : write-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : write-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : write-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : write-only

CIS18

Channel Interrupt Status Register (chid = 18)
address_offset : 0x4DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only

CSA18

Channel Source Address Register (chid = 18)
address_offset : 0x4E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write

CDA18

Channel Destination Address Register (chid = 18)
address_offset : 0x4E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write

CNDA18

Channel Next Descriptor Address Register (chid = 18)
address_offset : 0x4E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write

CNDC18

Channel Next Descriptor Control Register (chid = 18)
address_offset : 0x4EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.

CUBC18

Channel Microblock Control Register (chid = 18)
address_offset : 0x4F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write

CBC18

Channel Block Control Register (chid = 18)
address_offset : 0x4F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write

CC18

Channel Configuration Register (chid = 18)
address_offset : 0x4F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self triggered mode (Memory to Memory Transfer).

1 : PER_TRAN

Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral to Memory transfer.

1 : MEM2PER

Memory to Peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : TERMINATED

Channel initialization is in progress.

1 : IN_PROGRESS

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active write transaction on the bus.

1 : IN_PROGRESS

A Write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write

CDS_MSP18

Channel Data Stride Memory Set Pattern (chid = 18)
address_offset : 0x4FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write

CIE0

Channel Interrupt Enable Register (chid = 0)
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only

CSUS18

Channel Source Microblock Stride (chid = 18)
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CDUS18

Channel Destination Microblock Stride (chid = 18)
address_offset : 0x504 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CIE19

Channel Interrupt Enable Register (chid = 19)
address_offset : 0x510 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only

CID19

Channel Interrupt Disable Register (chid = 19)
address_offset : 0x514 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only

CIM19

Channel Interrupt Mask Register (chid = 19)
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : write-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : write-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : write-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : write-only

CIS19

Channel Interrupt Status Register (chid = 19)
address_offset : 0x51C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only

CSA19

Channel Source Address Register (chid = 19)
address_offset : 0x520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write

CDA19

Channel Destination Address Register (chid = 19)
address_offset : 0x524 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write

CNDA19

Channel Next Descriptor Address Register (chid = 19)
address_offset : 0x528 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write

CNDC19

Channel Next Descriptor Control Register (chid = 19)
address_offset : 0x52C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.

CUBC19

Channel Microblock Control Register (chid = 19)
address_offset : 0x530 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write

CBC19

Channel Block Control Register (chid = 19)
address_offset : 0x534 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write

CC19

Channel Configuration Register (chid = 19)
address_offset : 0x538 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self triggered mode (Memory to Memory Transfer).

1 : PER_TRAN

Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral to Memory transfer.

1 : MEM2PER

Memory to Peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : TERMINATED

Channel initialization is in progress.

1 : IN_PROGRESS

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active write transaction on the bus.

1 : IN_PROGRESS

A Write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write

CDS_MSP19

Channel Data Stride Memory Set Pattern (chid = 19)
address_offset : 0x53C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write

CID0

Channel Interrupt Disable Register (chid = 0)
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only

CSUS19

Channel Source Microblock Stride (chid = 19)
address_offset : 0x540 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CDUS19

Channel Destination Microblock Stride (chid = 19)
address_offset : 0x544 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CIE20

Channel Interrupt Enable Register (chid = 20)
address_offset : 0x550 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only

CID20

Channel Interrupt Disable Register (chid = 20)
address_offset : 0x554 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only

CIM20

Channel Interrupt Mask Register (chid = 20)
address_offset : 0x558 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : write-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : write-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : write-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : write-only

CIS20

Channel Interrupt Status Register (chid = 20)
address_offset : 0x55C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only

CSA20

Channel Source Address Register (chid = 20)
address_offset : 0x560 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write

CDA20

Channel Destination Address Register (chid = 20)
address_offset : 0x564 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write

CNDA20

Channel Next Descriptor Address Register (chid = 20)
address_offset : 0x568 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write

CNDC20

Channel Next Descriptor Control Register (chid = 20)
address_offset : 0x56C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.

CUBC20

Channel Microblock Control Register (chid = 20)
address_offset : 0x570 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write

CBC20

Channel Block Control Register (chid = 20)
address_offset : 0x574 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write

CC20

Channel Configuration Register (chid = 20)
address_offset : 0x578 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self triggered mode (Memory to Memory Transfer).

1 : PER_TRAN

Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral to Memory transfer.

1 : MEM2PER

Memory to Peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : TERMINATED

Channel initialization is in progress.

1 : IN_PROGRESS

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active write transaction on the bus.

1 : IN_PROGRESS

A Write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write

CDS_MSP20

Channel Data Stride Memory Set Pattern (chid = 20)
address_offset : 0x57C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write

CIM0

Channel Interrupt Mask Register (chid = 0)
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : write-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : write-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : write-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : write-only

CSUS20

Channel Source Microblock Stride (chid = 20)
address_offset : 0x580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CDUS20

Channel Destination Microblock Stride (chid = 20)
address_offset : 0x584 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CIE21

Channel Interrupt Enable Register (chid = 21)
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only

CID21

Channel Interrupt Disable Register (chid = 21)
address_offset : 0x594 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only

CIM21

Channel Interrupt Mask Register (chid = 21)
address_offset : 0x598 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : write-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : write-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : write-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : write-only

CIS21

Channel Interrupt Status Register (chid = 21)
address_offset : 0x59C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only

CSA21

Channel Source Address Register (chid = 21)
address_offset : 0x5A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write

CDA21

Channel Destination Address Register (chid = 21)
address_offset : 0x5A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write

CNDA21

Channel Next Descriptor Address Register (chid = 21)
address_offset : 0x5A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write

CNDC21

Channel Next Descriptor Control Register (chid = 21)
address_offset : 0x5AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.

CUBC21

Channel Microblock Control Register (chid = 21)
address_offset : 0x5B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write

CBC21

Channel Block Control Register (chid = 21)
address_offset : 0x5B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write

CC21

Channel Configuration Register (chid = 21)
address_offset : 0x5B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self triggered mode (Memory to Memory Transfer).

1 : PER_TRAN

Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral to Memory transfer.

1 : MEM2PER

Memory to Peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : TERMINATED

Channel initialization is in progress.

1 : IN_PROGRESS

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active write transaction on the bus.

1 : IN_PROGRESS

A Write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write

CDS_MSP21

Channel Data Stride Memory Set Pattern (chid = 21)
address_offset : 0x5BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write

CIS0

Channel Interrupt Status Register (chid = 0)
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only

CSUS21

Channel Source Microblock Stride (chid = 21)
address_offset : 0x5C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CDUS21

Channel Destination Microblock Stride (chid = 21)
address_offset : 0x5C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CIE22

Channel Interrupt Enable Register (chid = 22)
address_offset : 0x5D0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only

CID22

Channel Interrupt Disable Register (chid = 22)
address_offset : 0x5D4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only

CIM22

Channel Interrupt Mask Register (chid = 22)
address_offset : 0x5D8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : write-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : write-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : write-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : write-only

CIS22

Channel Interrupt Status Register (chid = 22)
address_offset : 0x5DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only

CSA22

Channel Source Address Register (chid = 22)
address_offset : 0x5E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write

CDA22

Channel Destination Address Register (chid = 22)
address_offset : 0x5E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write

CNDA22

Channel Next Descriptor Address Register (chid = 22)
address_offset : 0x5E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write

CNDC22

Channel Next Descriptor Control Register (chid = 22)
address_offset : 0x5EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.

CUBC22

Channel Microblock Control Register (chid = 22)
address_offset : 0x5F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write

CBC22

Channel Block Control Register (chid = 22)
address_offset : 0x5F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write

CC22

Channel Configuration Register (chid = 22)
address_offset : 0x5F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self triggered mode (Memory to Memory Transfer).

1 : PER_TRAN

Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral to Memory transfer.

1 : MEM2PER

Memory to Peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : TERMINATED

Channel initialization is in progress.

1 : IN_PROGRESS

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active write transaction on the bus.

1 : IN_PROGRESS

A Write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write

CDS_MSP22

Channel Data Stride Memory Set Pattern (chid = 22)
address_offset : 0x5FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write

CSA0

Channel Source Address Register (chid = 0)
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write

CSUS22

Channel Source Microblock Stride (chid = 22)
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CDUS22

Channel Destination Microblock Stride (chid = 22)
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CIE23

Channel Interrupt Enable Register (chid = 23)
address_offset : 0x610 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only

CID23

Channel Interrupt Disable Register (chid = 23)
address_offset : 0x614 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only

CIM23

Channel Interrupt Mask Register (chid = 23)
address_offset : 0x618 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : write-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : write-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : write-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : write-only

CIS23

Channel Interrupt Status Register (chid = 23)
address_offset : 0x61C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only

CSA23

Channel Source Address Register (chid = 23)
address_offset : 0x620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write

CDA23

Channel Destination Address Register (chid = 23)
address_offset : 0x624 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write

CNDA23

Channel Next Descriptor Address Register (chid = 23)
address_offset : 0x628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write

CNDC23

Channel Next Descriptor Control Register (chid = 23)
address_offset : 0x62C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.

CUBC23

Channel Microblock Control Register (chid = 23)
address_offset : 0x630 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write

CBC23

Channel Block Control Register (chid = 23)
address_offset : 0x634 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write

CC23

Channel Configuration Register (chid = 23)
address_offset : 0x638 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self triggered mode (Memory to Memory Transfer).

1 : PER_TRAN

Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral to Memory transfer.

1 : MEM2PER

Memory to Peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : TERMINATED

Channel initialization is in progress.

1 : IN_PROGRESS

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active write transaction on the bus.

1 : IN_PROGRESS

A Write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write

CDS_MSP23

Channel Data Stride Memory Set Pattern (chid = 23)
address_offset : 0x63C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write

CDA0

Channel Destination Address Register (chid = 0)
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write

CSUS23

Channel Source Microblock Stride (chid = 23)
address_offset : 0x640 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CDUS23

Channel Destination Microblock Stride (chid = 23)
address_offset : 0x644 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CNDA0

Channel Next Descriptor Address Register (chid = 0)
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write

CNDC0

Channel Next Descriptor Control Register (chid = 0)
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.

CUBC0

Channel Microblock Control Register (chid = 0)
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write

CBC0

Channel Block Control Register (chid = 0)
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write

CC0

Channel Configuration Register (chid = 0)
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self triggered mode (Memory to Memory Transfer).

1 : PER_TRAN

Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral to Memory transfer.

1 : MEM2PER

Memory to Peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : TERMINATED

Channel initialization is in progress.

1 : IN_PROGRESS

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active write transaction on the bus.

1 : IN_PROGRESS

A Write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write

CDS_MSP0

Channel Data Stride Memory Set Pattern (chid = 0)
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write

GWAC

Global Weighted Arbiter Configuration Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PW0 : Pool Weight 0
bits : 0 - 3 (4 bit)

PW1 : Pool Weight 1
bits : 4 - 7 (4 bit)

PW2 : Pool Weight 2
bits : 8 - 11 (4 bit)

PW3 : Pool Weight 3
bits : 12 - 15 (4 bit)

CIM

Channel Interrupt Mask Register (chid = 0)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)

CSUS0

Channel Source Microblock Stride (chid = 0)
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CDUS0

Channel Destination Microblock Stride (chid = 0)
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CIE1

Channel Interrupt Enable Register (chid = 1)
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only

CID1

Channel Interrupt Disable Register (chid = 1)
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only

CIM1

Channel Interrupt Mask Register (chid = 1)
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : write-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : write-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : write-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : write-only

CIS1

Channel Interrupt Status Register (chid = 1)
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only

CSA1

Channel Source Address Register (chid = 1)
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write

CDA1

Channel Destination Address Register (chid = 1)
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write

CNDA1

Channel Next Descriptor Address Register (chid = 1)
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write

CNDC1

Channel Next Descriptor Control Register (chid = 1)
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.

CUBC1

Channel Microblock Control Register (chid = 1)
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write

CBC1

Channel Block Control Register (chid = 1)
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write

CC1

Channel Configuration Register (chid = 1)
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self triggered mode (Memory to Memory Transfer).

1 : PER_TRAN

Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral to Memory transfer.

1 : MEM2PER

Memory to Peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : TERMINATED

Channel initialization is in progress.

1 : IN_PROGRESS

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active write transaction on the bus.

1 : IN_PROGRESS

A Write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write

CDS_MSP1

Channel Data Stride Memory Set Pattern (chid = 1)
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write

GIE

Global Interrupt Enable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IE0 : XDMAC Channel 0 Interrupt Enable Bit
bits : 0 - 0 (1 bit)

IE1 : XDMAC Channel 1 Interrupt Enable Bit
bits : 1 - 1 (1 bit)

IE2 : XDMAC Channel 2 Interrupt Enable Bit
bits : 2 - 2 (1 bit)

IE3 : XDMAC Channel 3 Interrupt Enable Bit
bits : 3 - 3 (1 bit)

IE4 : XDMAC Channel 4 Interrupt Enable Bit
bits : 4 - 4 (1 bit)

IE5 : XDMAC Channel 5 Interrupt Enable Bit
bits : 5 - 5 (1 bit)

IE6 : XDMAC Channel 6 Interrupt Enable Bit
bits : 6 - 6 (1 bit)

IE7 : XDMAC Channel 7 Interrupt Enable Bit
bits : 7 - 7 (1 bit)

IE8 : XDMAC Channel 8 Interrupt Enable Bit
bits : 8 - 8 (1 bit)

IE9 : XDMAC Channel 9 Interrupt Enable Bit
bits : 9 - 9 (1 bit)

IE10 : XDMAC Channel 10 Interrupt Enable Bit
bits : 10 - 10 (1 bit)

IE11 : XDMAC Channel 11 Interrupt Enable Bit
bits : 11 - 11 (1 bit)

IE12 : XDMAC Channel 12 Interrupt Enable Bit
bits : 12 - 12 (1 bit)

IE13 : XDMAC Channel 13 Interrupt Enable Bit
bits : 13 - 13 (1 bit)

IE14 : XDMAC Channel 14 Interrupt Enable Bit
bits : 14 - 14 (1 bit)

IE15 : XDMAC Channel 15 Interrupt Enable Bit
bits : 15 - 15 (1 bit)

IE16 : XDMAC Channel 16 Interrupt Enable Bit
bits : 16 - 16 (1 bit)

IE17 : XDMAC Channel 17 Interrupt Enable Bit
bits : 17 - 17 (1 bit)

IE18 : XDMAC Channel 18 Interrupt Enable Bit
bits : 18 - 18 (1 bit)

IE19 : XDMAC Channel 19 Interrupt Enable Bit
bits : 19 - 19 (1 bit)

IE20 : XDMAC Channel 20 Interrupt Enable Bit
bits : 20 - 20 (1 bit)

IE21 : XDMAC Channel 21 Interrupt Enable Bit
bits : 21 - 21 (1 bit)

IE22 : XDMAC Channel 22 Interrupt Enable Bit
bits : 22 - 22 (1 bit)

IE23 : XDMAC Channel 23 Interrupt Enable Bit
bits : 23 - 23 (1 bit)

CIS

Channel Interrupt Status Register (chid = 0)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)

CSUS1

Channel Source Microblock Stride (chid = 1)
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CDUS1

Channel Destination Microblock Stride (chid = 1)
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write

CIE2

Channel Interrupt Enable Register (chid = 2)
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only

CID2

Channel Interrupt Disable Register (chid = 2)
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only

CIM2

Channel Interrupt Mask Register (chid = 2)
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : write-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : write-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : write-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : write-only

CIS2

Channel Interrupt Status Register (chid = 2)
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only

CSA2

Channel Source Address Register (chid = 2)
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write

CDA2

Channel Destination Address Register (chid = 2)
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write

CNDA2

Channel Next Descriptor Address Register (chid = 2)
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write

CNDC2

Channel Next Descriptor Control Register (chid = 2)
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.

CUBC2

Channel Microblock Control Register (chid = 2)
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write

CBC2

Channel Block Control Register (chid = 2)
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write

CC2

Channel Configuration Register (chid = 2)
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self triggered mode (Memory to Memory Transfer).

1 : PER_TRAN

Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral to Memory transfer.

1 : MEM2PER

Memory to Peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : TERMINATED

Channel initialization is in progress.

1 : IN_PROGRESS

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No Active write transaction on the bus.

1 : IN_PROGRESS

A Write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write

CDS_MSP2

Channel Data Stride Memory Set Pattern (chid = 2)
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write

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XDMAC

Peripheral Memory Blocks

Registers

GTYPE

CIE

GID

CSA

CSUS2

CDUS2

CIE3

CID3

CIM3

CIS3

CSA3

CDA3

CNDA3

CNDC3

CUBC3

CBC3

CC3

CDS_MSP3

GIM

CDA

CSUS3

CDUS3

CIE4

CID4

CIM4

CIS4

CSA4

CDA4

CNDA4

CNDC4

CUBC4

CBC4

CC4

CDS_MSP4

GIS

CNDA

CSUS4

CDUS4

CIE5

CID5

CIM5

CIS5

CSA5

CDA5

CNDA5

CNDC5

CUBC5

CBC5

CC5

CDS_MSP5

GE

CNDC

CSUS5

CDUS5

CIE6

CID6

CIM6

CIS6

CSA6

CDA6

CNDA6

CNDC6

CUBC6

CBC6

CC6

CDS_MSP6

GD

CUBC

CSUS6

CDUS6

CIE7

CID7

CIM7

CIS7

CSA7

CDA7