\n
address_offset : 0x0 Bytes (0x0)
size : 0xEC byte (0x0)
mem_usage : registers
protection :
address_offset : 0x0 Bytes (0x0)
size : 0xEC byte (0x0)
mem_usage : registers
protection :
address_offset : 0x0 Bytes (0x0)
size : 0xEC byte (0x0)
mem_usage : registers
protection :
AFEC Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
START : Start Conversion
bits : 1 - 1 (1 bit)
AFEC Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
access : write-only
START : Start Conversion
bits : 1 - 1 (1 bit)
access : write-only
AFEC Channel Sequence 2 Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USCH8 : User Sequence Number 8
bits : 0 - 3 (4 bit)
USCH9 : User Sequence Number 9
bits : 4 - 7 (4 bit)
USCH10 : User Sequence Number 10
bits : 8 - 11 (4 bit)
USCH11 : User Sequence Number 11
bits : 12 - 15 (4 bit)
AFEC Channel Sequence 2 Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
USCH8 : User Sequence Number 8
bits : 0 - 3 (4 bit)
access : read-write
USCH9 : User Sequence Number 9
bits : 4 - 7 (4 bit)
access : read-write
USCH10 : User Sequence Number 10
bits : 8 - 11 (4 bit)
access : read-write
USCH11 : User Sequence Number 11
bits : 12 - 15 (4 bit)
access : read-write
USCH12 : User Sequence Number 12
bits : 16 - 19 (4 bit)
access : read-write
USCH13 : User Sequence Number 13
bits : 20 - 23 (4 bit)
access : read-write
USCH14 : User Sequence Number 14
bits : 24 - 27 (4 bit)
access : read-write
USCH15 : User Sequence Number 15
bits : 28 - 31 (4 bit)
access : read-write
AFEC Channel Enable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CH0 : Channel 0 Enable
bits : 0 - 0 (1 bit)
CH1 : Channel 1 Enable
bits : 1 - 1 (1 bit)
CH2 : Channel 2 Enable
bits : 2 - 2 (1 bit)
CH3 : Channel 3 Enable
bits : 3 - 3 (1 bit)
CH4 : Channel 4 Enable
bits : 4 - 4 (1 bit)
CH5 : Channel 5 Enable
bits : 5 - 5 (1 bit)
CH6 : Channel 6 Enable
bits : 6 - 6 (1 bit)
CH7 : Channel 7 Enable
bits : 7 - 7 (1 bit)
CH8 : Channel 8 Enable
bits : 8 - 8 (1 bit)
CH9 : Channel 9 Enable
bits : 9 - 9 (1 bit)
CH10 : Channel 10 Enable
bits : 10 - 10 (1 bit)
CH11 : Channel 11 Enable
bits : 11 - 11 (1 bit)
AFEC Channel Enable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
CH0 : Channel 0 Enable
bits : 0 - 0 (1 bit)
access : write-only
CH1 : Channel 1 Enable
bits : 1 - 1 (1 bit)
access : write-only
CH2 : Channel 2 Enable
bits : 2 - 2 (1 bit)
access : write-only
CH3 : Channel 3 Enable
bits : 3 - 3 (1 bit)
access : write-only
CH4 : Channel 4 Enable
bits : 4 - 4 (1 bit)
access : write-only
CH5 : Channel 5 Enable
bits : 5 - 5 (1 bit)
access : write-only
CH6 : Channel 6 Enable
bits : 6 - 6 (1 bit)
access : write-only
CH7 : Channel 7 Enable
bits : 7 - 7 (1 bit)
access : write-only
CH8 : Channel 8 Enable
bits : 8 - 8 (1 bit)
access : write-only
CH9 : Channel 9 Enable
bits : 9 - 9 (1 bit)
access : write-only
CH10 : Channel 10 Enable
bits : 10 - 10 (1 bit)
access : write-only
CH11 : Channel 11 Enable
bits : 11 - 11 (1 bit)
access : write-only
AFEC Channel Disable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CH0 : Channel 0 Disable
bits : 0 - 0 (1 bit)
CH1 : Channel 1 Disable
bits : 1 - 1 (1 bit)
CH2 : Channel 2 Disable
bits : 2 - 2 (1 bit)
CH3 : Channel 3 Disable
bits : 3 - 3 (1 bit)
CH4 : Channel 4 Disable
bits : 4 - 4 (1 bit)
CH5 : Channel 5 Disable
bits : 5 - 5 (1 bit)
CH6 : Channel 6 Disable
bits : 6 - 6 (1 bit)
CH7 : Channel 7 Disable
bits : 7 - 7 (1 bit)
CH8 : Channel 8 Disable
bits : 8 - 8 (1 bit)
CH9 : Channel 9 Disable
bits : 9 - 9 (1 bit)
CH10 : Channel 10 Disable
bits : 10 - 10 (1 bit)
CH11 : Channel 11 Disable
bits : 11 - 11 (1 bit)
AFEC Channel Disable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
CH0 : Channel 0 Disable
bits : 0 - 0 (1 bit)
access : write-only
CH1 : Channel 1 Disable
bits : 1 - 1 (1 bit)
access : write-only
CH2 : Channel 2 Disable
bits : 2 - 2 (1 bit)
access : write-only
CH3 : Channel 3 Disable
bits : 3 - 3 (1 bit)
access : write-only
CH4 : Channel 4 Disable
bits : 4 - 4 (1 bit)
access : write-only
CH5 : Channel 5 Disable
bits : 5 - 5 (1 bit)
access : write-only
CH6 : Channel 6 Disable
bits : 6 - 6 (1 bit)
access : write-only
CH7 : Channel 7 Disable
bits : 7 - 7 (1 bit)
access : write-only
CH8 : Channel 8 Disable
bits : 8 - 8 (1 bit)
access : write-only
CH9 : Channel 9 Disable
bits : 9 - 9 (1 bit)
access : write-only
CH10 : Channel 10 Disable
bits : 10 - 10 (1 bit)
access : write-only
CH11 : Channel 11 Disable
bits : 11 - 11 (1 bit)
access : write-only
AFEC Channel Status Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH0 : Channel 0 Status
bits : 0 - 0 (1 bit)
CH1 : Channel 1 Status
bits : 1 - 1 (1 bit)
CH2 : Channel 2 Status
bits : 2 - 2 (1 bit)
CH3 : Channel 3 Status
bits : 3 - 3 (1 bit)
CH4 : Channel 4 Status
bits : 4 - 4 (1 bit)
CH5 : Channel 5 Status
bits : 5 - 5 (1 bit)
CH6 : Channel 6 Status
bits : 6 - 6 (1 bit)
CH7 : Channel 7 Status
bits : 7 - 7 (1 bit)
CH8 : Channel 8 Status
bits : 8 - 8 (1 bit)
CH9 : Channel 9 Status
bits : 9 - 9 (1 bit)
CH10 : Channel 10 Status
bits : 10 - 10 (1 bit)
CH11 : Channel 11 Status
bits : 11 - 11 (1 bit)
AFEC Channel Status Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
CH0 : Channel 0 Status
bits : 0 - 0 (1 bit)
access : read-only
CH1 : Channel 1 Status
bits : 1 - 1 (1 bit)
access : read-only
CH2 : Channel 2 Status
bits : 2 - 2 (1 bit)
access : read-only
CH3 : Channel 3 Status
bits : 3 - 3 (1 bit)
access : read-only
CH4 : Channel 4 Status
bits : 4 - 4 (1 bit)
access : read-only
CH5 : Channel 5 Status
bits : 5 - 5 (1 bit)
access : read-only
CH6 : Channel 6 Status
bits : 6 - 6 (1 bit)
access : read-only
CH7 : Channel 7 Status
bits : 7 - 7 (1 bit)
access : read-only
CH8 : Channel 8 Status
bits : 8 - 8 (1 bit)
access : read-only
CH9 : Channel 9 Status
bits : 9 - 9 (1 bit)
access : read-only
CH10 : Channel 10 Status
bits : 10 - 10 (1 bit)
access : read-only
CH11 : Channel 11 Status
bits : 11 - 11 (1 bit)
access : read-only
AFEC Last Converted Data Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LDATA : Last Data Converted
bits : 0 - 15 (16 bit)
CHNB : Channel Number
bits : 24 - 27 (4 bit)
AFEC Last Converted Data Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
LDATA : Last Data Converted
bits : 0 - 15 (16 bit)
access : read-only
CHNB : Channel Number
bits : 24 - 27 (4 bit)
access : read-only
AFEC Interrupt Enable Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EOC0 : End of Conversion Interrupt Enable 0
bits : 0 - 0 (1 bit)
EOC1 : End of Conversion Interrupt Enable 1
bits : 1 - 1 (1 bit)
EOC2 : End of Conversion Interrupt Enable 2
bits : 2 - 2 (1 bit)
EOC3 : End of Conversion Interrupt Enable 3
bits : 3 - 3 (1 bit)
EOC4 : End of Conversion Interrupt Enable 4
bits : 4 - 4 (1 bit)
EOC5 : End of Conversion Interrupt Enable 5
bits : 5 - 5 (1 bit)
EOC6 : End of Conversion Interrupt Enable 6
bits : 6 - 6 (1 bit)
EOC7 : End of Conversion Interrupt Enable 7
bits : 7 - 7 (1 bit)
EOC8 : End of Conversion Interrupt Enable 8
bits : 8 - 8 (1 bit)
EOC9 : End of Conversion Interrupt Enable 9
bits : 9 - 9 (1 bit)
EOC10 : End of Conversion Interrupt Enable 10
bits : 10 - 10 (1 bit)
EOC11 : End of Conversion Interrupt Enable 11
bits : 11 - 11 (1 bit)
DRDY : Data Ready Interrupt Enable
bits : 24 - 24 (1 bit)
GOVRE : General Overrun Error Interrupt Enable
bits : 25 - 25 (1 bit)
COMPE : Comparison Event Interrupt Enable
bits : 26 - 26 (1 bit)
TEMPCHG : Temperature Change Interrupt Enable
bits : 30 - 30 (1 bit)
AFEC Interrupt Enable Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
EOC0 : End of Conversion Interrupt Enable 0
bits : 0 - 0 (1 bit)
access : write-only
EOC1 : End of Conversion Interrupt Enable 1
bits : 1 - 1 (1 bit)
access : write-only
EOC2 : End of Conversion Interrupt Enable 2
bits : 2 - 2 (1 bit)
access : write-only
EOC3 : End of Conversion Interrupt Enable 3
bits : 3 - 3 (1 bit)
access : write-only
EOC4 : End of Conversion Interrupt Enable 4
bits : 4 - 4 (1 bit)
access : write-only
EOC5 : End of Conversion Interrupt Enable 5
bits : 5 - 5 (1 bit)
access : write-only
EOC6 : End of Conversion Interrupt Enable 6
bits : 6 - 6 (1 bit)
access : write-only
EOC7 : End of Conversion Interrupt Enable 7
bits : 7 - 7 (1 bit)
access : write-only
EOC8 : End of Conversion Interrupt Enable 8
bits : 8 - 8 (1 bit)
access : write-only
EOC9 : End of Conversion Interrupt Enable 9
bits : 9 - 9 (1 bit)
access : write-only
EOC10 : End of Conversion Interrupt Enable 10
bits : 10 - 10 (1 bit)
access : write-only
EOC11 : End of Conversion Interrupt Enable 11
bits : 11 - 11 (1 bit)
access : write-only
DRDY : Data Ready Interrupt Enable
bits : 24 - 24 (1 bit)
access : write-only
GOVRE : General Overrun Error Interrupt Enable
bits : 25 - 25 (1 bit)
access : write-only
COMPE : Comparison Event Interrupt Enable
bits : 26 - 26 (1 bit)
access : write-only
TEMPCHG : Temperature Change Interrupt Enable
bits : 30 - 30 (1 bit)
access : write-only
AFEC Interrupt Disable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EOC0 : End of Conversion Interrupt Disable 0
bits : 0 - 0 (1 bit)
EOC1 : End of Conversion Interrupt Disable 1
bits : 1 - 1 (1 bit)
EOC2 : End of Conversion Interrupt Disable 2
bits : 2 - 2 (1 bit)
EOC3 : End of Conversion Interrupt Disable 3
bits : 3 - 3 (1 bit)
EOC4 : End of Conversion Interrupt Disable 4
bits : 4 - 4 (1 bit)
EOC5 : End of Conversion Interrupt Disable 5
bits : 5 - 5 (1 bit)
EOC6 : End of Conversion Interrupt Disable 6
bits : 6 - 6 (1 bit)
EOC7 : End of Conversion Interrupt Disable 7
bits : 7 - 7 (1 bit)
EOC8 : End of Conversion Interrupt Disable 8
bits : 8 - 8 (1 bit)
EOC9 : End of Conversion Interrupt Disable 9
bits : 9 - 9 (1 bit)
EOC10 : End of Conversion Interrupt Disable 10
bits : 10 - 10 (1 bit)
EOC11 : End of Conversion Interrupt Disable 11
bits : 11 - 11 (1 bit)
DRDY : Data Ready Interrupt Disable
bits : 24 - 24 (1 bit)
GOVRE : General Overrun Error Interrupt Disable
bits : 25 - 25 (1 bit)
COMPE : Comparison Event Interrupt Disable
bits : 26 - 26 (1 bit)
TEMPCHG : Temperature Change Interrupt Disable
bits : 30 - 30 (1 bit)
AFEC Interrupt Disable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
EOC0 : End of Conversion Interrupt Disable 0
bits : 0 - 0 (1 bit)
access : write-only
EOC1 : End of Conversion Interrupt Disable 1
bits : 1 - 1 (1 bit)
access : write-only
EOC2 : End of Conversion Interrupt Disable 2
bits : 2 - 2 (1 bit)
access : write-only
EOC3 : End of Conversion Interrupt Disable 3
bits : 3 - 3 (1 bit)
access : write-only
EOC4 : End of Conversion Interrupt Disable 4
bits : 4 - 4 (1 bit)
access : write-only
EOC5 : End of Conversion Interrupt Disable 5
bits : 5 - 5 (1 bit)
access : write-only
EOC6 : End of Conversion Interrupt Disable 6
bits : 6 - 6 (1 bit)
access : write-only
EOC7 : End of Conversion Interrupt Disable 7
bits : 7 - 7 (1 bit)
access : write-only
EOC8 : End of Conversion Interrupt Disable 8
bits : 8 - 8 (1 bit)
access : write-only
EOC9 : End of Conversion Interrupt Disable 9
bits : 9 - 9 (1 bit)
access : write-only
EOC10 : End of Conversion Interrupt Disable 10
bits : 10 - 10 (1 bit)
access : write-only
EOC11 : End of Conversion Interrupt Disable 11
bits : 11 - 11 (1 bit)
access : write-only
DRDY : Data Ready Interrupt Disable
bits : 24 - 24 (1 bit)
access : write-only
GOVRE : General Overrun Error Interrupt Disable
bits : 25 - 25 (1 bit)
access : write-only
COMPE : Comparison Event Interrupt Disable
bits : 26 - 26 (1 bit)
access : write-only
TEMPCHG : Temperature Change Interrupt Disable
bits : 30 - 30 (1 bit)
access : write-only
AFEC Interrupt Mask Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EOC0 : End of Conversion Interrupt Mask 0
bits : 0 - 0 (1 bit)
EOC1 : End of Conversion Interrupt Mask 1
bits : 1 - 1 (1 bit)
EOC2 : End of Conversion Interrupt Mask 2
bits : 2 - 2 (1 bit)
EOC3 : End of Conversion Interrupt Mask 3
bits : 3 - 3 (1 bit)
EOC4 : End of Conversion Interrupt Mask 4
bits : 4 - 4 (1 bit)
EOC5 : End of Conversion Interrupt Mask 5
bits : 5 - 5 (1 bit)
EOC6 : End of Conversion Interrupt Mask 6
bits : 6 - 6 (1 bit)
EOC7 : End of Conversion Interrupt Mask 7
bits : 7 - 7 (1 bit)
EOC8 : End of Conversion Interrupt Mask 8
bits : 8 - 8 (1 bit)
EOC9 : End of Conversion Interrupt Mask 9
bits : 9 - 9 (1 bit)
EOC10 : End of Conversion Interrupt Mask 10
bits : 10 - 10 (1 bit)
EOC11 : End of Conversion Interrupt Mask 11
bits : 11 - 11 (1 bit)
DRDY : Data Ready Interrupt Mask
bits : 24 - 24 (1 bit)
GOVRE : General Overrun Error Interrupt Mask
bits : 25 - 25 (1 bit)
COMPE : Comparison Event Interrupt Mask
bits : 26 - 26 (1 bit)
TEMPCHG : Temperature Change Interrupt Mask
bits : 30 - 30 (1 bit)
AFEC Interrupt Mask Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
EOC0 : End of Conversion Interrupt Mask 0
bits : 0 - 0 (1 bit)
access : read-only
EOC1 : End of Conversion Interrupt Mask 1
bits : 1 - 1 (1 bit)
access : read-only
EOC2 : End of Conversion Interrupt Mask 2
bits : 2 - 2 (1 bit)
access : read-only
EOC3 : End of Conversion Interrupt Mask 3
bits : 3 - 3 (1 bit)
access : read-only
EOC4 : End of Conversion Interrupt Mask 4
bits : 4 - 4 (1 bit)
access : read-only
EOC5 : End of Conversion Interrupt Mask 5
bits : 5 - 5 (1 bit)
access : read-only
EOC6 : End of Conversion Interrupt Mask 6
bits : 6 - 6 (1 bit)
access : read-only
EOC7 : End of Conversion Interrupt Mask 7
bits : 7 - 7 (1 bit)
access : read-only
EOC8 : End of Conversion Interrupt Mask 8
bits : 8 - 8 (1 bit)
access : read-only
EOC9 : End of Conversion Interrupt Mask 9
bits : 9 - 9 (1 bit)
access : read-only
EOC10 : End of Conversion Interrupt Mask 10
bits : 10 - 10 (1 bit)
access : read-only
EOC11 : End of Conversion Interrupt Mask 11
bits : 11 - 11 (1 bit)
access : read-only
DRDY : Data Ready Interrupt Mask
bits : 24 - 24 (1 bit)
access : read-only
GOVRE : General Overrun Error Interrupt Mask
bits : 25 - 25 (1 bit)
access : read-only
COMPE : Comparison Event Interrupt Mask
bits : 26 - 26 (1 bit)
access : read-only
TEMPCHG : Temperature Change Interrupt Mask
bits : 30 - 30 (1 bit)
access : read-only
AFEC Interrupt Status Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EOC0 : End of Conversion 0 (cleared by reading AFEC_CDRx)
bits : 0 - 0 (1 bit)
EOC1 : End of Conversion 1 (cleared by reading AFEC_CDRx)
bits : 1 - 1 (1 bit)
EOC2 : End of Conversion 2 (cleared by reading AFEC_CDRx)
bits : 2 - 2 (1 bit)
EOC3 : End of Conversion 3 (cleared by reading AFEC_CDRx)
bits : 3 - 3 (1 bit)
EOC4 : End of Conversion 4 (cleared by reading AFEC_CDRx)
bits : 4 - 4 (1 bit)
EOC5 : End of Conversion 5 (cleared by reading AFEC_CDRx)
bits : 5 - 5 (1 bit)
EOC6 : End of Conversion 6 (cleared by reading AFEC_CDRx)
bits : 6 - 6 (1 bit)
EOC7 : End of Conversion 7 (cleared by reading AFEC_CDRx)
bits : 7 - 7 (1 bit)
EOC8 : End of Conversion 8 (cleared by reading AFEC_CDRx)
bits : 8 - 8 (1 bit)
EOC9 : End of Conversion 9 (cleared by reading AFEC_CDRx)
bits : 9 - 9 (1 bit)
EOC10 : End of Conversion 10 (cleared by reading AFEC_CDRx)
bits : 10 - 10 (1 bit)
EOC11 : End of Conversion 11 (cleared by reading AFEC_CDRx)
bits : 11 - 11 (1 bit)
DRDY : Data Ready (cleared by reading AFEC_LCDR)
bits : 24 - 24 (1 bit)
GOVRE : General Overrun Error (cleared by reading AFEC_ISR)
bits : 25 - 25 (1 bit)
COMPE : Comparison Error (cleared by reading AFEC_ISR)
bits : 26 - 26 (1 bit)
TEMPCHG : Temperature Change (cleared on read)
bits : 30 - 30 (1 bit)
AFEC Interrupt Status Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
EOC0 : End of Conversion 0 (cleared by reading AFEC_CDRx)
bits : 0 - 0 (1 bit)
access : read-only
EOC1 : End of Conversion 1 (cleared by reading AFEC_CDRx)
bits : 1 - 1 (1 bit)
access : read-only
EOC2 : End of Conversion 2 (cleared by reading AFEC_CDRx)
bits : 2 - 2 (1 bit)
access : read-only
EOC3 : End of Conversion 3 (cleared by reading AFEC_CDRx)
bits : 3 - 3 (1 bit)
access : read-only
EOC4 : End of Conversion 4 (cleared by reading AFEC_CDRx)
bits : 4 - 4 (1 bit)
access : read-only
EOC5 : End of Conversion 5 (cleared by reading AFEC_CDRx)
bits : 5 - 5 (1 bit)
access : read-only
EOC6 : End of Conversion 6 (cleared by reading AFEC_CDRx)
bits : 6 - 6 (1 bit)
access : read-only
EOC7 : End of Conversion 7 (cleared by reading AFEC_CDRx)
bits : 7 - 7 (1 bit)
access : read-only
EOC8 : End of Conversion 8 (cleared by reading AFEC_CDRx)
bits : 8 - 8 (1 bit)
access : read-only
EOC9 : End of Conversion 9 (cleared by reading AFEC_CDRx)
bits : 9 - 9 (1 bit)
access : read-only
EOC10 : End of Conversion 10 (cleared by reading AFEC_CDRx)
bits : 10 - 10 (1 bit)
access : read-only
EOC11 : End of Conversion 11 (cleared by reading AFEC_CDRx)
bits : 11 - 11 (1 bit)
access : read-only
DRDY : Data Ready (cleared by reading AFEC_LCDR)
bits : 24 - 24 (1 bit)
access : read-only
GOVRE : General Overrun Error (cleared by reading AFEC_ISR)
bits : 25 - 25 (1 bit)
access : read-only
COMPE : Comparison Error (cleared by reading AFEC_ISR)
bits : 26 - 26 (1 bit)
access : read-only
TEMPCHG : Temperature Change (cleared on read)
bits : 30 - 30 (1 bit)
access : read-only
AFEC Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGEN : Trigger Enable
bits : 0 - 0 (1 bit)
Enumeration: TRGENSelect
0 : DIS
Hardware triggers are disabled. Starting a conversion is only possible by software.
1 : EN
Hardware trigger selected by TRGSEL field is enabled.
End of enumeration elements list.
TRGSEL : Trigger Selection
bits : 1 - 3 (3 bit)
Enumeration: TRGSELSelect
0x0 : AFEC_TRIG0
AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1
0x1 : AFEC_TRIG1
TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1
0x2 : AFEC_TRIG2
TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1
0x3 : AFEC_TRIG3
TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1
0x4 : AFEC_TRIG4
PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1
0x5 : AFEC_TRIG5
PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1
0x6 : AFEC_TRIG6
Analog Comparator
End of enumeration elements list.
SLEEP : Sleep Mode
bits : 5 - 5 (1 bit)
Enumeration: SLEEPSelect
0 : NORMAL
Normal mode: The AFE and reference voltage circuitry are kept ON between conversions.
1 : SLEEP
Sleep mode: The AFE and reference voltage circuitry are OFF between conversions.
End of enumeration elements list.
FWUP : Fast Wake-up
bits : 6 - 6 (1 bit)
Enumeration: FWUPSelect
0 : OFF
Normal Sleep mode: The sleep mode is defined by the SLEEP bit.
1 : ON
Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF.
End of enumeration elements list.
FREERUN : Free Run Mode
bits : 7 - 7 (1 bit)
Enumeration: FREERUNSelect
0 : OFF
Normal mode
1 : ON
Free Run mode: Never wait for any trigger.
End of enumeration elements list.
PRESCAL : Prescaler Rate Selection
bits : 8 - 15 (8 bit)
STARTUP : Start-up Time
bits : 16 - 19 (4 bit)
Enumeration: STARTUPSelect
0x0 : SUT0
0 periods of AFE clock
0x1 : SUT8
8 periods of AFE clock
0x2 : SUT16
16 periods of AFE clock
0x3 : SUT24
24 periods of AFE clock
0x4 : SUT64
64 periods of AFE clock
0x5 : SUT80
80 periods of AFE clock
0x6 : SUT96
96 periods of AFE clock
0x7 : SUT112
112 periods of AFE clock
0x8 : SUT512
512 periods of AFE clock
0x9 : SUT576
576 periods of AFE clock
0xA : SUT640
640 periods of AFE clock
0xB : SUT704
704 periods of AFE clock
0xC : SUT768
768 periods of AFE clock
0xD : SUT832
832 periods of AFE clock
0xE : SUT896
896 periods of AFE clock
0xF : SUT960
960 periods of AFE clock
End of enumeration elements list.
ONE : One
bits : 23 - 23 (1 bit)
TRACKTIM : Tracking Time
bits : 24 - 27 (4 bit)
TRANSFER : Transfer Period
bits : 28 - 29 (2 bit)
USEQ : User Sequence Enable
bits : 31 - 31 (1 bit)
Enumeration: USEQSelect
0 : NUM_ORDER
Normal mode: The controller converts channels in a simple numeric order.
1 : REG_ORDER
User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R.
End of enumeration elements list.
AFEC Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TRGEN : Trigger Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DIS
Hardware triggers are disabled. Starting a conversion is only possible by software.
1 : EN
Hardware trigger selected by TRGSEL field is enabled.
End of enumeration elements list.
TRGSEL : Trigger Selection
bits : 1 - 3 (3 bit)
access : read-write
Enumeration:
0x0 : AFEC_TRIG0
AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1
0x1 : AFEC_TRIG1
TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1
0x2 : AFEC_TRIG2
TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1
0x3 : AFEC_TRIG3
TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1
0x4 : AFEC_TRIG4
PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1
0x5 : AFEC_TRIG5
PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1
0x6 : AFEC_TRIG6
Analog Comparator
End of enumeration elements list.
SLEEP : Sleep Mode
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NORMAL
Normal mode: The AFE and reference voltage circuitry are kept ON between conversions.
1 : SLEEP
Sleep mode: The AFE and reference voltage circuitry are OFF between conversions.
End of enumeration elements list.
FWUP : Fast Wake-up
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : OFF
Normal Sleep mode: The sleep mode is defined by the SLEEP bit.
1 : ON
Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF.
End of enumeration elements list.
FREERUN : Free Run Mode
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : OFF
Normal mode
1 : ON
Free Run mode: Never wait for any trigger.
End of enumeration elements list.
PRESCAL : Prescaler Rate Selection
bits : 8 - 15 (8 bit)
access : read-write
STARTUP : Start-up Time
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0x0 : SUT0
0 periods of AFE clock
0x1 : SUT8
8 periods of AFE clock
0x2 : SUT16
16 periods of AFE clock
0x3 : SUT24
24 periods of AFE clock
0x4 : SUT64
64 periods of AFE clock
0x5 : SUT80
80 periods of AFE clock
0x6 : SUT96
96 periods of AFE clock
0x7 : SUT112
112 periods of AFE clock
0x8 : SUT512
512 periods of AFE clock
0x9 : SUT576
576 periods of AFE clock
0xA : SUT640
640 periods of AFE clock
0xB : SUT704
704 periods of AFE clock
0xC : SUT768
768 periods of AFE clock
0xD : SUT832
832 periods of AFE clock
0xE : SUT896
896 periods of AFE clock
0xF : SUT960
960 periods of AFE clock
End of enumeration elements list.
ONE : One
bits : 23 - 23 (1 bit)
access : read-write
TRACKTIM : Tracking Time
bits : 24 - 27 (4 bit)
access : read-write
TRANSFER : Transfer Period
bits : 28 - 29 (2 bit)
access : read-write
USEQ : User Sequence Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NUM_ORDER
Normal mode: The controller converts channels in a simple numeric order.
1 : REG_ORDER
User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R.
End of enumeration elements list.
AFEC Overrun Status Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
OVRE0 : Overrun Error 0
bits : 0 - 0 (1 bit)
OVRE1 : Overrun Error 1
bits : 1 - 1 (1 bit)
OVRE2 : Overrun Error 2
bits : 2 - 2 (1 bit)
OVRE3 : Overrun Error 3
bits : 3 - 3 (1 bit)
OVRE4 : Overrun Error 4
bits : 4 - 4 (1 bit)
OVRE5 : Overrun Error 5
bits : 5 - 5 (1 bit)
OVRE6 : Overrun Error 6
bits : 6 - 6 (1 bit)
OVRE7 : Overrun Error 7
bits : 7 - 7 (1 bit)
OVRE8 : Overrun Error 8
bits : 8 - 8 (1 bit)
OVRE9 : Overrun Error 9
bits : 9 - 9 (1 bit)
OVRE10 : Overrun Error 10
bits : 10 - 10 (1 bit)
OVRE11 : Overrun Error 11
bits : 11 - 11 (1 bit)
AFEC Overrun Status Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
OVRE0 : Overrun Error 0
bits : 0 - 0 (1 bit)
access : read-only
OVRE1 : Overrun Error 1
bits : 1 - 1 (1 bit)
access : read-only
OVRE2 : Overrun Error 2
bits : 2 - 2 (1 bit)
access : read-only
OVRE3 : Overrun Error 3
bits : 3 - 3 (1 bit)
access : read-only
OVRE4 : Overrun Error 4
bits : 4 - 4 (1 bit)
access : read-only
OVRE5 : Overrun Error 5
bits : 5 - 5 (1 bit)
access : read-only
OVRE6 : Overrun Error 6
bits : 6 - 6 (1 bit)
access : read-only
OVRE7 : Overrun Error 7
bits : 7 - 7 (1 bit)
access : read-only
OVRE8 : Overrun Error 8
bits : 8 - 8 (1 bit)
access : read-only
OVRE9 : Overrun Error 9
bits : 9 - 9 (1 bit)
access : read-only
OVRE10 : Overrun Error 10
bits : 10 - 10 (1 bit)
access : read-only
OVRE11 : Overrun Error 11
bits : 11 - 11 (1 bit)
access : read-only
AFEC Compare Window Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOWTHRES : Low Threshold
bits : 0 - 15 (16 bit)
HIGHTHRES : High Threshold
bits : 16 - 31 (16 bit)
AFEC Compare Window Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
LOWTHRES : Low Threshold
bits : 0 - 15 (16 bit)
access : read-write
HIGHTHRES : High Threshold
bits : 16 - 31 (16 bit)
access : read-write
AFEC Channel Gain Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAIN0 : Gain for Channel 0
bits : 0 - 1 (2 bit)
GAIN1 : Gain for Channel 1
bits : 2 - 3 (2 bit)
GAIN2 : Gain for Channel 2
bits : 4 - 5 (2 bit)
GAIN3 : Gain for Channel 3
bits : 6 - 7 (2 bit)
GAIN4 : Gain for Channel 4
bits : 8 - 9 (2 bit)
GAIN5 : Gain for Channel 5
bits : 10 - 11 (2 bit)
GAIN6 : Gain for Channel 6
bits : 12 - 13 (2 bit)
GAIN7 : Gain for Channel 7
bits : 14 - 15 (2 bit)
GAIN8 : Gain for Channel 8
bits : 16 - 17 (2 bit)
GAIN9 : Gain for Channel 9
bits : 18 - 19 (2 bit)
GAIN10 : Gain for Channel 10
bits : 20 - 21 (2 bit)
GAIN11 : Gain for Channel 11
bits : 22 - 23 (2 bit)
AFEC Channel Gain Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
GAIN0 : Gain for Channel 0
bits : 0 - 1 (2 bit)
access : read-write
GAIN1 : Gain for Channel 1
bits : 2 - 3 (2 bit)
access : read-write
GAIN2 : Gain for Channel 2
bits : 4 - 5 (2 bit)
access : read-write
GAIN3 : Gain for Channel 3
bits : 6 - 7 (2 bit)
access : read-write
GAIN4 : Gain for Channel 4
bits : 8 - 9 (2 bit)
access : read-write
GAIN5 : Gain for Channel 5
bits : 10 - 11 (2 bit)
access : read-write
GAIN6 : Gain for Channel 6
bits : 12 - 13 (2 bit)
access : read-write
GAIN7 : Gain for Channel 7
bits : 14 - 15 (2 bit)
access : read-write
GAIN8 : Gain for Channel 8
bits : 16 - 17 (2 bit)
access : read-write
GAIN9 : Gain for Channel 9
bits : 18 - 19 (2 bit)
access : read-write
GAIN10 : Gain for Channel 10
bits : 20 - 21 (2 bit)
access : read-write
GAIN11 : Gain for Channel 11
bits : 22 - 23 (2 bit)
access : read-write
AFEC Channel Differential Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIFF0 : Differential inputs for channel 0
bits : 0 - 0 (1 bit)
DIFF1 : Differential inputs for channel 1
bits : 1 - 1 (1 bit)
DIFF2 : Differential inputs for channel 2
bits : 2 - 2 (1 bit)
DIFF3 : Differential inputs for channel 3
bits : 3 - 3 (1 bit)
DIFF4 : Differential inputs for channel 4
bits : 4 - 4 (1 bit)
DIFF5 : Differential inputs for channel 5
bits : 5 - 5 (1 bit)
DIFF6 : Differential inputs for channel 6
bits : 6 - 6 (1 bit)
DIFF7 : Differential inputs for channel 7
bits : 7 - 7 (1 bit)
DIFF8 : Differential inputs for channel 8
bits : 8 - 8 (1 bit)
DIFF9 : Differential inputs for channel 9
bits : 9 - 9 (1 bit)
DIFF10 : Differential inputs for channel 10
bits : 10 - 10 (1 bit)
DIFF11 : Differential inputs for channel 11
bits : 11 - 11 (1 bit)
AFEC Channel Differential Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DIFF0 : Differential inputs for channel 0
bits : 0 - 0 (1 bit)
access : read-write
DIFF1 : Differential inputs for channel 1
bits : 1 - 1 (1 bit)
access : read-write
DIFF2 : Differential inputs for channel 2
bits : 2 - 2 (1 bit)
access : read-write
DIFF3 : Differential inputs for channel 3
bits : 3 - 3 (1 bit)
access : read-write
DIFF4 : Differential inputs for channel 4
bits : 4 - 4 (1 bit)
access : read-write
DIFF5 : Differential inputs for channel 5
bits : 5 - 5 (1 bit)
access : read-write
DIFF6 : Differential inputs for channel 6
bits : 6 - 6 (1 bit)
access : read-write
DIFF7 : Differential inputs for channel 7
bits : 7 - 7 (1 bit)
access : read-write
DIFF8 : Differential inputs for channel 8
bits : 8 - 8 (1 bit)
access : read-write
DIFF9 : Differential inputs for channel 9
bits : 9 - 9 (1 bit)
access : read-write
DIFF10 : Differential inputs for channel 10
bits : 10 - 10 (1 bit)
access : read-write
DIFF11 : Differential inputs for channel 11
bits : 11 - 11 (1 bit)
access : read-write
AFEC Channel Selection Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL : Channel Selection
bits : 0 - 3 (4 bit)
AFEC Channel Selection Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CSEL : Channel Selection
bits : 0 - 3 (4 bit)
access : read-write
AFEC Channel Data Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Converted Data
bits : 0 - 15 (16 bit)
AFEC Channel Data Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
DATA : Converted Data
bits : 0 - 15 (16 bit)
access : read-only
AFEC Channel Offset Compensation Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AOFF : Analog Offset
bits : 0 - 9 (10 bit)
AFEC Channel Offset Compensation Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
AOFF : Analog Offset
bits : 0 - 9 (10 bit)
access : read-write
AFEC Temperature Sensor Mode Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTCT : Temperature Sensor RTC Trigger Mode
bits : 0 - 0 (1 bit)
TEMPCMPMOD : Temperature Comparison Mode
bits : 4 - 5 (2 bit)
Enumeration: TEMPCMPMODSelect
0x0 : LOW
Generates an event when the converted data is lower than the low threshold of the window.
0x1 : HIGH
Generates an event when the converted data is higher than the high threshold of the window.
0x2 : IN
Generates an event when the converted data is in the comparison window.
0x3 : OUT
Generates an event when the converted data is out of the comparison window.
End of enumeration elements list.
AFEC Temperature Sensor Mode Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RTCT : Temperature Sensor RTC Trigger Mode
bits : 0 - 0 (1 bit)
access : read-write
TEMPCMPMOD : Temperature Comparison Mode
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : LOW
Generates an event when the converted data is lower than the low threshold of the window.
0x1 : HIGH
Generates an event when the converted data is higher than the high threshold of the window.
0x2 : IN
Generates an event when the converted data is in the comparison window.
0x3 : OUT
Generates an event when the converted data is out of the comparison window.
End of enumeration elements list.
AFEC Temperature Compare Window Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TLOWTHRES : Temperature Low Threshold
bits : 0 - 15 (16 bit)
THIGHTHRES : Temperature High Threshold
bits : 16 - 31 (16 bit)
AFEC Temperature Compare Window Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TLOWTHRES : Temperature Low Threshold
bits : 0 - 15 (16 bit)
access : read-write
THIGHTHRES : Temperature High Threshold
bits : 16 - 31 (16 bit)
access : read-write
AFEC Extended Mode Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPMODE : Comparison Mode
bits : 0 - 1 (2 bit)
Enumeration: CMPMODESelect
0x0 : LOW
Generates an event when the converted data is lower than the low threshold of the window.
0x1 : HIGH
Generates an event when the converted data is higher than the high threshold of the window.
0x2 : IN
Generates an event when the converted data is in the comparison window.
0x3 : OUT
Generates an event when the converted data is out of the comparison window.
End of enumeration elements list.
CMPSEL : Comparison Selected Channel
bits : 3 - 7 (5 bit)
CMPALL : Compare All Channels
bits : 9 - 9 (1 bit)
CMPFILTER : Compare Event Filtering
bits : 12 - 13 (2 bit)
RES : Resolution
bits : 16 - 18 (3 bit)
Enumeration: RESSelect
0x0 : NO_AVERAGE
12-bit resolution, AFE sample rate is maximum (no averaging).
0x2 : OSR4
13-bit resolution, AFE sample rate divided by 4 (averaging).
0x3 : OSR16
14-bit resolution, AFE sample rate divided by 16 (averaging).
0x4 : OSR64
15-bit resolution, AFE sample rate divided by 64 (averaging).
0x5 : OSR256
16-bit resolution, AFE sample rate divided by 256 (averaging).
End of enumeration elements list.
TAG : TAG of the AFEC_LDCR
bits : 24 - 24 (1 bit)
STM : Single Trigger Mode
bits : 25 - 25 (1 bit)
SIGNMODE : Sign Mode
bits : 28 - 29 (2 bit)
Enumeration: SIGNMODESelect
0x0 : SE_UNSG_DF_SIGN
Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions.
0x1 : SE_SIGN_DF_UNSG
Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions.
0x2 : ALL_UNSIGNED
All channels: Unsigned conversions.
0x3 : ALL_SIGNED
All channels: Signed conversions.
End of enumeration elements list.
AFEC Extended Mode Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CMPMODE : Comparison Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : LOW
Generates an event when the converted data is lower than the low threshold of the window.
0x1 : HIGH
Generates an event when the converted data is higher than the high threshold of the window.
0x2 : IN
Generates an event when the converted data is in the comparison window.
0x3 : OUT
Generates an event when the converted data is out of the comparison window.
End of enumeration elements list.
CMPSEL : Comparison Selected Channel
bits : 3 - 7 (5 bit)
access : read-write
CMPALL : Compare All Channels
bits : 9 - 9 (1 bit)
access : read-write
CMPFILTER : Compare Event Filtering
bits : 12 - 13 (2 bit)
access : read-write
RES : Resolution
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0x0 : NO_AVERAGE
12-bit resolution, AFE sample rate is maximum (no averaging).
0x2 : OSR4
13-bit resolution, AFE sample rate divided by 4 (averaging).
0x3 : OSR16
14-bit resolution, AFE sample rate divided by 16 (averaging).
0x4 : OSR64
15-bit resolution, AFE sample rate divided by 64 (averaging).
0x5 : OSR256
16-bit resolution, AFE sample rate divided by 256 (averaging).
End of enumeration elements list.
TAG : TAG of the AFEC_LDCR
bits : 24 - 24 (1 bit)
access : read-write
STM : Single Trigger Mode
bits : 25 - 25 (1 bit)
access : read-write
SIGNMODE : Sign Mode
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : SE_UNSG_DF_SIGN
Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions.
0x1 : SE_SIGN_DF_UNSG
Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions.
0x2 : ALL_UNSIGNED
All channels: Unsigned conversions.
0x3 : ALL_SIGNED
All channels: Signed conversions.
End of enumeration elements list.
AFEC Analog Control Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PGA0EN : PGA0 Enable
bits : 2 - 2 (1 bit)
PGA1EN : PGA1 Enable
bits : 3 - 3 (1 bit)
IBCTL : AFE Bias Current Control
bits : 8 - 9 (2 bit)
AFEC Analog Control Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
PGA0EN : PGA0 Enable
bits : 2 - 2 (1 bit)
access : read-write
PGA1EN : PGA1 Enable
bits : 3 - 3 (1 bit)
access : read-write
IBCTL : AFE Bias Current Control
bits : 8 - 9 (2 bit)
access : read-write
AFEC Sample and Hold Mode Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUAL0 : Dual Sample and Hold for channel 0
bits : 0 - 0 (1 bit)
DUAL1 : Dual Sample and Hold for channel 1
bits : 1 - 1 (1 bit)
DUAL2 : Dual Sample and Hold for channel 2
bits : 2 - 2 (1 bit)
DUAL3 : Dual Sample and Hold for channel 3
bits : 3 - 3 (1 bit)
DUAL4 : Dual Sample and Hold for channel 4
bits : 4 - 4 (1 bit)
DUAL5 : Dual Sample and Hold for channel 5
bits : 5 - 5 (1 bit)
DUAL6 : Dual Sample and Hold for channel 6
bits : 6 - 6 (1 bit)
DUAL7 : Dual Sample and Hold for channel 7
bits : 7 - 7 (1 bit)
DUAL8 : Dual Sample and Hold for channel 8
bits : 8 - 8 (1 bit)
DUAL9 : Dual Sample and Hold for channel 9
bits : 9 - 9 (1 bit)
DUAL10 : Dual Sample and Hold for channel 10
bits : 10 - 10 (1 bit)
DUAL11 : Dual Sample and Hold for channel 11
bits : 11 - 11 (1 bit)
AFEC Sample and Hold Mode Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DUAL0 : Dual Sample and Hold for channel 0
bits : 0 - 0 (1 bit)
access : read-write
DUAL1 : Dual Sample and Hold for channel 1
bits : 1 - 1 (1 bit)
access : read-write
DUAL2 : Dual Sample and Hold for channel 2
bits : 2 - 2 (1 bit)
access : read-write
DUAL3 : Dual Sample and Hold for channel 3
bits : 3 - 3 (1 bit)
access : read-write
DUAL4 : Dual Sample and Hold for channel 4
bits : 4 - 4 (1 bit)
access : read-write
DUAL5 : Dual Sample and Hold for channel 5
bits : 5 - 5 (1 bit)
access : read-write
DUAL6 : Dual Sample and Hold for channel 6
bits : 6 - 6 (1 bit)
access : read-write
DUAL7 : Dual Sample and Hold for channel 7
bits : 7 - 7 (1 bit)
access : read-write
DUAL8 : Dual Sample and Hold for channel 8
bits : 8 - 8 (1 bit)
access : read-write
DUAL9 : Dual Sample and Hold for channel 9
bits : 9 - 9 (1 bit)
access : read-write
DUAL10 : Dual Sample and Hold for channel 10
bits : 10 - 10 (1 bit)
access : read-write
DUAL11 : Dual Sample and Hold for channel 11
bits : 11 - 11 (1 bit)
access : read-write
AFEC Channel Sequence 1 Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USCH0 : User Sequence Number 0
bits : 0 - 3 (4 bit)
USCH1 : User Sequence Number 1
bits : 4 - 7 (4 bit)
USCH2 : User Sequence Number 2
bits : 8 - 11 (4 bit)
USCH3 : User Sequence Number 3
bits : 12 - 15 (4 bit)
USCH4 : User Sequence Number 4
bits : 16 - 19 (4 bit)
USCH5 : User Sequence Number 5
bits : 20 - 23 (4 bit)
USCH6 : User Sequence Number 6
bits : 24 - 27 (4 bit)
USCH7 : User Sequence Number 7
bits : 28 - 31 (4 bit)
AFEC Channel Sequence 1 Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
USCH0 : User Sequence Number 0
bits : 0 - 3 (4 bit)
access : read-write
USCH1 : User Sequence Number 1
bits : 4 - 7 (4 bit)
access : read-write
USCH2 : User Sequence Number 2
bits : 8 - 11 (4 bit)
access : read-write
USCH3 : User Sequence Number 3
bits : 12 - 15 (4 bit)
access : read-write
USCH4 : User Sequence Number 4
bits : 16 - 19 (4 bit)
access : read-write
USCH5 : User Sequence Number 5
bits : 20 - 23 (4 bit)
access : read-write
USCH6 : User Sequence Number 6
bits : 24 - 27 (4 bit)
access : read-write
USCH7 : User Sequence Number 7
bits : 28 - 31 (4 bit)
access : read-write
AFEC Correction Select Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL : Sample and Hold unit Correction Select
bits : 0 - 0 (1 bit)
AFEC Correction Select Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CSEL : Sample and Hold unit Correction Select
bits : 0 - 0 (1 bit)
access : read-write
AFEC Correction Values Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSETCORR : Offset Correction
bits : 0 - 15 (16 bit)
GAINCORR : Gain Correction
bits : 16 - 31 (16 bit)
AFEC Correction Values Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
OFFSETCORR : Offset Correction
bits : 0 - 15 (16 bit)
access : read-write
GAINCORR : Gain Correction
bits : 16 - 31 (16 bit)
access : read-write
AFEC Channel Error Correction Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECORR0 : Error Correction Enable for channel 0
bits : 0 - 0 (1 bit)
ECORR1 : Error Correction Enable for channel 1
bits : 1 - 1 (1 bit)
ECORR2 : Error Correction Enable for channel 2
bits : 2 - 2 (1 bit)
ECORR3 : Error Correction Enable for channel 3
bits : 3 - 3 (1 bit)
ECORR4 : Error Correction Enable for channel 4
bits : 4 - 4 (1 bit)
ECORR5 : Error Correction Enable for channel 5
bits : 5 - 5 (1 bit)
ECORR6 : Error Correction Enable for channel 6
bits : 6 - 6 (1 bit)
ECORR7 : Error Correction Enable for channel 7
bits : 7 - 7 (1 bit)
ECORR8 : Error Correction Enable for channel 8
bits : 8 - 8 (1 bit)
ECORR9 : Error Correction Enable for channel 9
bits : 9 - 9 (1 bit)
ECORR10 : Error Correction Enable for channel 10
bits : 10 - 10 (1 bit)
ECORR11 : Error Correction Enable for channel 11
bits : 11 - 11 (1 bit)
AFEC Channel Error Correction Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ECORR0 : Error Correction Enable for channel 0
bits : 0 - 0 (1 bit)
access : read-write
ECORR1 : Error Correction Enable for channel 1
bits : 1 - 1 (1 bit)
access : read-write
ECORR2 : Error Correction Enable for channel 2
bits : 2 - 2 (1 bit)
access : read-write
ECORR3 : Error Correction Enable for channel 3
bits : 3 - 3 (1 bit)
access : read-write
ECORR4 : Error Correction Enable for channel 4
bits : 4 - 4 (1 bit)
access : read-write
ECORR5 : Error Correction Enable for channel 5
bits : 5 - 5 (1 bit)
access : read-write
ECORR6 : Error Correction Enable for channel 6
bits : 6 - 6 (1 bit)
access : read-write
ECORR7 : Error Correction Enable for channel 7
bits : 7 - 7 (1 bit)
access : read-write
ECORR8 : Error Correction Enable for channel 8
bits : 8 - 8 (1 bit)
access : read-write
ECORR9 : Error Correction Enable for channel 9
bits : 9 - 9 (1 bit)
access : read-write
ECORR10 : Error Correction Enable for channel 10
bits : 10 - 10 (1 bit)
access : read-write
ECORR11 : Error Correction Enable for channel 11
bits : 11 - 11 (1 bit)
access : read-write
AFEC Write Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
WPKEY : Write Protect KEY
bits : 8 - 31 (24 bit)
Enumeration: WPKEYSelect
0x414443 : PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
End of enumeration elements list.
AFEC Write Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
access : read-write
WPKEY : Write Protect KEY
bits : 8 - 31 (24 bit)
access : read-write
Enumeration:
0x414443 : PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
End of enumeration elements list.
AFEC Write Protection Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WPVS : Write Protect Violation Status
bits : 0 - 0 (1 bit)
WPVSRC : Write Protect Violation Source
bits : 8 - 23 (16 bit)
AFEC Write Protection Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
WPVS : Write Protect Violation Status
bits : 0 - 0 (1 bit)
access : read-only
WPVSRC : Write Protect Violation Source
bits : 8 - 23 (16 bit)
access : read-only
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