Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xB58 byte (0x0)
mem_usage : registers
protection :
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
MCIEN : Multi-Media Interface Enable
bits : 0 - 0 (1 bit)
MCIDIS : Multi-Media Interface Disable
bits : 1 - 1 (1 bit)
PWSEN : Power Save Mode Enable
bits : 2 - 2 (1 bit)
PWSDIS : Power Save Mode Disable
bits : 3 - 3 (1 bit)
SWRST : Software Reset
bits : 7 - 7 (1 bit)
Argument Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARG : Command Argument
bits : 0 - 31 (32 bit)
Command Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CMDNB : Command Number
bits : 0 - 5 (6 bit)
RSPTYP : Response Type
bits : 6 - 7 (2 bit)
Enumeration: RSPTYPSelect
0x0 : NORESP
No response
0x1 : _48_BIT
48-bit response
0x2 : _136_BIT
136-bit response
0x3 : R1B
R1b response type
End of enumeration elements list.
SPCMD : Special Command
bits : 8 - 10 (3 bit)
Enumeration: SPCMDSelect
0x0 : STD
Not a special CMD.
0x1 : INIT
Initialization CMD: 74 clock cycles for initialization sequence.
0x2 : SYNC
Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command.
0x3 : CE_ATA
CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line.
0x4 : IT_CMD
Interrupt command: Corresponds to the Interrupt Mode (CMD40).
0x5 : IT_RESP
Interrupt response: Corresponds to the Interrupt Mode (CMD40).
0x6 : BOR
Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly.
0x7 : EBO
End Boot Operation. This command allows the host processor to terminate the boot operation mode.
End of enumeration elements list.
OPDCMD : Open Drain Command
bits : 11 - 11 (1 bit)
Enumeration: OPDCMDSelect
0 : PUSHPULL
Push pull command.
1 : OPENDRAIN
Open drain command.
End of enumeration elements list.
MAXLAT : Max Latency for Command to Response
bits : 12 - 12 (1 bit)
Enumeration: MAXLATSelect
0 : _5
5-cycle max latency.
1 : _64
64-cycle max latency.
End of enumeration elements list.
TRCMD : Transfer Command
bits : 16 - 17 (2 bit)
Enumeration: TRCMDSelect
0x0 : NO_DATA
No data transfer
0x1 : START_DATA
Start data transfer
0x2 : STOP_DATA
Stop data transfer
End of enumeration elements list.
TRDIR : Transfer Direction
bits : 18 - 18 (1 bit)
Enumeration: TRDIRSelect
0 : WRITE
Write.
1 : READ
Read.
End of enumeration elements list.
TRTYP : Transfer Type
bits : 19 - 21 (3 bit)
Enumeration: TRTYPSelect
0x0 : SINGLE
MMC/SD Card Single Block
0x1 : MULTIPLE
MMC/SD Card Multiple Block
0x2 : STREAM
MMC Stream
0x4 : BYTE
SDIO Byte
0x5 : BLOCK
SDIO Block
End of enumeration elements list.
IOSPCMD : SDIO Special Command
bits : 24 - 25 (2 bit)
Enumeration: IOSPCMDSelect
0x0 : STD
Not an SDIO Special Command
0x1 : SUSPEND
SDIO Suspend Command
0x2 : RESUME
SDIO Resume Command
End of enumeration elements list.
ATACS : ATA with Command Completion Signal
bits : 26 - 26 (1 bit)
Enumeration: ATACSSelect
0 : NORMAL
Normal operation mode.
1 : COMPLETION
This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR).
End of enumeration elements list.
BOOT_ACK : Boot Operation Acknowledge
bits : 27 - 27 (1 bit)
Block Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BCNT : MMC/SDIO Block Count - SDIO Byte Count
bits : 0 - 15 (16 bit)
BLKLEN : Data Block Length
bits : 16 - 31 (16 bit)
Completion Signal Timeout Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSTOCYC : Completion Signal Timeout Cycle Number
bits : 0 - 3 (4 bit)
CSTOMUL : Completion Signal Timeout Multiplier
bits : 4 - 6 (3 bit)
Enumeration: CSTOMULSelect
0x0 : _1
CSTOCYC x 1
0x1 : _16
CSTOCYC x 16
0x2 : _128
CSTOCYC x 128
0x3 : _256
CSTOCYC x 256
0x4 : _1024
CSTOCYC x 1024
0x5 : _4096
CSTOCYC x 4096
0x6 : _65536
CSTOCYC x 65536
0x7 : _1048576
CSTOCYC x 1048576
End of enumeration elements list.
Response Register 0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RSP : Response
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x23C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
Response Register 0
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RSP : Response
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x27C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
Response Register 0
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RSP : Response
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x2B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x2BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
Response Register 0
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RSP : Response
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x2C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x2CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x2D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x2DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x2E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x2E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x2EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x2F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x2F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x2F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x2FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
Receive Data Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x32C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x33C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
Transmit Data Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x344 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x34C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x350 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x354 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x358 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x35C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x368 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x36C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x378 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x37C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x38C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x398 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x39C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x3A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x3A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x3A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x3AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x3B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x3B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x3B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x3BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x3C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x3C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x3C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x3CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x3D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x3D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x3D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x3DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x3E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x3E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x3E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x3EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKDIV : Clock Divider
bits : 0 - 7 (8 bit)
PWSDIV : Power Saving Divider
bits : 8 - 10 (3 bit)
RDPROOF : Read Proof Enable
bits : 11 - 11 (1 bit)
WRPROOF : Write Proof Enable
bits : 12 - 12 (1 bit)
FBYTE : Force Byte Transfer
bits : 13 - 13 (1 bit)
PADV : Padding Value
bits : 14 - 14 (1 bit)
CLKODD : Clock divider is odd
bits : 16 - 16 (1 bit)
Status Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMDRDY : Command Ready (cleared by writing in HSMCI_CMDR)
bits : 0 - 0 (1 bit)
RXRDY : Receiver Ready (cleared by reading HSMCI_RDR)
bits : 1 - 1 (1 bit)
TXRDY : Transmit Ready (cleared by writing in HSMCI_TDR)
bits : 2 - 2 (1 bit)
BLKE : Data Block Ended (cleared on read)
bits : 3 - 3 (1 bit)
DTIP : Data Transfer in Progress (cleared at the end of CRC16 calculation)
bits : 4 - 4 (1 bit)
NOTBUSY : HSMCI Not Busy
bits : 5 - 5 (1 bit)
SDIOIRQA : SDIO Interrupt for Slot A (cleared on read)
bits : 8 - 8 (1 bit)
SDIOWAIT : SDIO Read Wait Operation Status
bits : 12 - 12 (1 bit)
CSRCV : CE-ATA Completion Signal Received (cleared on read)
bits : 13 - 13 (1 bit)
RINDE : Response Index Error (cleared by writing in HSMCI_CMDR)
bits : 16 - 16 (1 bit)
RDIRE : Response Direction Error (cleared by writing in HSMCI_CMDR)
bits : 17 - 17 (1 bit)
RCRCE : Response CRC Error (cleared by writing in HSMCI_CMDR)
bits : 18 - 18 (1 bit)
RENDE : Response End Bit Error (cleared by writing in HSMCI_CMDR)
bits : 19 - 19 (1 bit)
RTOE : Response Time-out Error (cleared by writing in HSMCI_CMDR)
bits : 20 - 20 (1 bit)
DCRCE : Data CRC Error (cleared on read)
bits : 21 - 21 (1 bit)
DTOE : Data Time-out Error (cleared on read)
bits : 22 - 22 (1 bit)
CSTOE : Completion Signal Time-out Error (cleared on read)
bits : 23 - 23 (1 bit)
BLKOVRE : DMA Block Overrun Error (cleared on read)
bits : 24 - 24 (1 bit)
FIFOEMPTY : FIFO empty flag
bits : 26 - 26 (1 bit)
XFRDONE : Transfer Done flag
bits : 27 - 27 (1 bit)
ACKRCV : Boot Operation Acknowledge Received (cleared on read)
bits : 28 - 28 (1 bit)
ACKRCVE : Boot Operation Acknowledge Error (cleared on read)
bits : 29 - 29 (1 bit)
OVRE : Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0)
bits : 30 - 30 (1 bit)
UNRE : Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0)
bits : 31 - 31 (1 bit)
FIFO Memory Aperture0 0
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x43C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
Interrupt Enable Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CMDRDY : Command Ready Interrupt Enable
bits : 0 - 0 (1 bit)
RXRDY : Receiver Ready Interrupt Enable
bits : 1 - 1 (1 bit)
TXRDY : Transmit Ready Interrupt Enable
bits : 2 - 2 (1 bit)
BLKE : Data Block Ended Interrupt Enable
bits : 3 - 3 (1 bit)
DTIP : Data Transfer in Progress Interrupt Enable
bits : 4 - 4 (1 bit)
NOTBUSY : Data Not Busy Interrupt Enable
bits : 5 - 5 (1 bit)
SDIOIRQA : SDIO Interrupt for Slot A Interrupt Enable
bits : 8 - 8 (1 bit)
SDIOWAIT : SDIO Read Wait Operation Status Interrupt Enable
bits : 12 - 12 (1 bit)
CSRCV : Completion Signal Received Interrupt Enable
bits : 13 - 13 (1 bit)
RINDE : Response Index Error Interrupt Enable
bits : 16 - 16 (1 bit)
RDIRE : Response Direction Error Interrupt Enable
bits : 17 - 17 (1 bit)
RCRCE : Response CRC Error Interrupt Enable
bits : 18 - 18 (1 bit)
RENDE : Response End Bit Error Interrupt Enable
bits : 19 - 19 (1 bit)
RTOE : Response Time-out Error Interrupt Enable
bits : 20 - 20 (1 bit)
DCRCE : Data CRC Error Interrupt Enable
bits : 21 - 21 (1 bit)
DTOE : Data Time-out Error Interrupt Enable
bits : 22 - 22 (1 bit)
CSTOE : Completion Signal Timeout Error Interrupt Enable
bits : 23 - 23 (1 bit)
BLKOVRE : DMA Block Overrun Error Interrupt Enable
bits : 24 - 24 (1 bit)
FIFOEMPTY : FIFO empty Interrupt enable
bits : 26 - 26 (1 bit)
XFRDONE : Transfer Done Interrupt enable
bits : 27 - 27 (1 bit)
ACKRCV : Boot Acknowledge Interrupt Enable
bits : 28 - 28 (1 bit)
ACKRCVE : Boot Acknowledge Error Interrupt Enable
bits : 29 - 29 (1 bit)
OVRE : Overrun Interrupt Enable
bits : 30 - 30 (1 bit)
UNRE : Underrun Interrupt Enable
bits : 31 - 31 (1 bit)
FIFO Memory Aperture0 0
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x444 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x44C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x458 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x45C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x464 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x468 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x46C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x474 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x478 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x47C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
Interrupt Disable Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CMDRDY : Command Ready Interrupt Disable
bits : 0 - 0 (1 bit)
RXRDY : Receiver Ready Interrupt Disable
bits : 1 - 1 (1 bit)
TXRDY : Transmit Ready Interrupt Disable
bits : 2 - 2 (1 bit)
BLKE : Data Block Ended Interrupt Disable
bits : 3 - 3 (1 bit)
DTIP : Data Transfer in Progress Interrupt Disable
bits : 4 - 4 (1 bit)
NOTBUSY : Data Not Busy Interrupt Disable
bits : 5 - 5 (1 bit)
SDIOIRQA : SDIO Interrupt for Slot A Interrupt Disable
bits : 8 - 8 (1 bit)
SDIOWAIT : SDIO Read Wait Operation Status Interrupt Disable
bits : 12 - 12 (1 bit)
CSRCV : Completion Signal received interrupt Disable
bits : 13 - 13 (1 bit)
RINDE : Response Index Error Interrupt Disable
bits : 16 - 16 (1 bit)
RDIRE : Response Direction Error Interrupt Disable
bits : 17 - 17 (1 bit)
RCRCE : Response CRC Error Interrupt Disable
bits : 18 - 18 (1 bit)
RENDE : Response End Bit Error Interrupt Disable
bits : 19 - 19 (1 bit)
RTOE : Response Time-out Error Interrupt Disable
bits : 20 - 20 (1 bit)
DCRCE : Data CRC Error Interrupt Disable
bits : 21 - 21 (1 bit)
DTOE : Data Time-out Error Interrupt Disable
bits : 22 - 22 (1 bit)
CSTOE : Completion Signal Time out Error Interrupt Disable
bits : 23 - 23 (1 bit)
BLKOVRE : DMA Block Overrun Error Interrupt Disable
bits : 24 - 24 (1 bit)
FIFOEMPTY : FIFO empty Interrupt Disable
bits : 26 - 26 (1 bit)
XFRDONE : Transfer Done Interrupt Disable
bits : 27 - 27 (1 bit)
ACKRCV : Boot Acknowledge Interrupt Disable
bits : 28 - 28 (1 bit)
ACKRCVE : Boot Acknowledge Error Interrupt Disable
bits : 29 - 29 (1 bit)
OVRE : Overrun Interrupt Disable
bits : 30 - 30 (1 bit)
UNRE : Underrun Interrupt Disable
bits : 31 - 31 (1 bit)
FIFO Memory Aperture0 0
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x484 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x48C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x494 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x498 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x49C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x4A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x4A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x4A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x4AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x4B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x4B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x4B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x4BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
Interrupt Mask Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMDRDY : Command Ready Interrupt Mask
bits : 0 - 0 (1 bit)
RXRDY : Receiver Ready Interrupt Mask
bits : 1 - 1 (1 bit)
TXRDY : Transmit Ready Interrupt Mask
bits : 2 - 2 (1 bit)
BLKE : Data Block Ended Interrupt Mask
bits : 3 - 3 (1 bit)
DTIP : Data Transfer in Progress Interrupt Mask
bits : 4 - 4 (1 bit)
NOTBUSY : Data Not Busy Interrupt Mask
bits : 5 - 5 (1 bit)
SDIOIRQA : SDIO Interrupt for Slot A Interrupt Mask
bits : 8 - 8 (1 bit)
SDIOWAIT : SDIO Read Wait Operation Status Interrupt Mask
bits : 12 - 12 (1 bit)
CSRCV : Completion Signal Received Interrupt Mask
bits : 13 - 13 (1 bit)
RINDE : Response Index Error Interrupt Mask
bits : 16 - 16 (1 bit)
RDIRE : Response Direction Error Interrupt Mask
bits : 17 - 17 (1 bit)
RCRCE : Response CRC Error Interrupt Mask
bits : 18 - 18 (1 bit)
RENDE : Response End Bit Error Interrupt Mask
bits : 19 - 19 (1 bit)
RTOE : Response Time-out Error Interrupt Mask
bits : 20 - 20 (1 bit)
DCRCE : Data CRC Error Interrupt Mask
bits : 21 - 21 (1 bit)
DTOE : Data Time-out Error Interrupt Mask
bits : 22 - 22 (1 bit)
CSTOE : Completion Signal Time-out Error Interrupt Mask
bits : 23 - 23 (1 bit)
BLKOVRE : DMA Block Overrun Error Interrupt Mask
bits : 24 - 24 (1 bit)
FIFOEMPTY : FIFO Empty Interrupt Mask
bits : 26 - 26 (1 bit)
XFRDONE : Transfer Done Interrupt Mask
bits : 27 - 27 (1 bit)
ACKRCV : Boot Operation Acknowledge Received Interrupt Mask
bits : 28 - 28 (1 bit)
ACKRCVE : Boot Operation Acknowledge Error Interrupt Mask
bits : 29 - 29 (1 bit)
OVRE : Overrun Interrupt Mask
bits : 30 - 30 (1 bit)
UNRE : Underrun Interrupt Mask
bits : 31 - 31 (1 bit)
FIFO Memory Aperture0 0
address_offset : 0x4C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x4C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x4C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x4CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x4D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x4D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x4D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x4DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x4E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x4E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x4E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x4EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x4F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x4F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x4F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x4FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
DMA Configuration Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHKSIZE : DMA Channel Read and Write Chunk Size
bits : 4 - 6 (3 bit)
Enumeration: CHKSIZESelect
0x0 : _1
1 data available
0x1 : _2
2 data available
0x2 : _4
4 data available
0x3 : _8
8 data available
0x4 : _16
16 data available
End of enumeration elements list.
DMAEN : DMA Hardware Handshaking Enable
bits : 8 - 8 (1 bit)
FIFO Memory Aperture0 0
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x504 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x514 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x51C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x524 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x528 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x52C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x530 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x534 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x538 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x53C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
Configuration Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFOMODE : HSMCI Internal FIFO control mode
bits : 0 - 0 (1 bit)
FERRCTRL : Flow Error flag reset control mode
bits : 4 - 4 (1 bit)
HSMODE : High Speed Mode
bits : 8 - 8 (1 bit)
LSYNC : Synchronize on the last block
bits : 12 - 12 (1 bit)
FIFO Memory Aperture0 0
address_offset : 0x540 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x544 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x548 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x54C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x550 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x554 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x558 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x55C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x560 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x564 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x568 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x56C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x570 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x574 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x578 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x57C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x584 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x588 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x58C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x594 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x598 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x59C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x5A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x5A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x5A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x5AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x5B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x5B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x5B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x5BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x5C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x5C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x5C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x5CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x5D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x5D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x5D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x5DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x5E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x5E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x5E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x5EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x5F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x5F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x5F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
FIFO Memory Aperture0 0
address_offset : 0x5FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
Data Timeout Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTOCYC : Data Timeout Cycle Number
bits : 0 - 3 (4 bit)
DTOMUL : Data Timeout Multiplier
bits : 4 - 6 (3 bit)
Enumeration: DTOMULSelect
0x0 : _1
DTOCYC
0x1 : _16
DTOCYC x 16
0x2 : _128
DTOCYC x 128
0x3 : _256
DTOCYC x 256
0x4 : _1024
DTOCYC x 1024
0x5 : _4096
DTOCYC x 4096
0x6 : _65536
DTOCYC x 65536
0x7 : _1048576
DTOCYC x 1048576
End of enumeration elements list.
SD/SDIO Card Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDCSEL : SDCard/SDIO Slot
bits : 0 - 1 (2 bit)
Enumeration: SDCSELSelect
0 : SLOTA
Slot A is selected.
End of enumeration elements list.
SDCBUS : SDCard/SDIO Bus Width
bits : 6 - 7 (2 bit)
Enumeration: SDCBUSSelect
0x0 : _1
1 bit
0x2 : _4
4 bits
0x3 : _8
8 bits
End of enumeration elements list.
Write Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WPEN : Write Protect Enable
bits : 0 - 0 (1 bit)
WPKEY : Write Protect Key
bits : 8 - 31 (24 bit)
Enumeration: WPKEYSelect
0x4D4349 : PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
End of enumeration elements list.
Write Protection Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WPVS : Write Protection Violation Status
bits : 0 - 0 (1 bit)
WPVSRC : Write Protection Violation Source
bits : 8 - 23 (16 bit)
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