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XDMAC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xE60 byte (0x0)
mem_usage : registers
protection :

Registers

GTYPE

CIE

GID

CSA

GIM

CDA

GIS

CNDA

GE

CNDC

GD

CUBC

GS

CBC

GRS

CC

GWS

CDS_MSP

GRWS

CSUS

GRWR

CDUS

GSWR

GSWS

GCFG

CID

GSWF

GWAC

CIM

GIE

CIS


GTYPE

Global Type Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GTYPE GTYPE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NB_CH FIFO_SZ NB_REQ

NB_CH : Number of Channels Minus One
bits : 0 - 4 (5 bit)

FIFO_SZ : Number of Bytes
bits : 5 - 15 (11 bit)

NB_REQ : Number of Peripheral Requests Minus One
bits : 16 - 22 (7 bit)


CIE

Channel Interrupt Enable Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CIE CIE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)


GID

Global Interrupt Disable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GID GID write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ID8 ID9 ID10 ID11 ID12 ID13 ID14 ID15 ID16 ID17 ID18 ID19 ID20 ID21 ID22 ID23

ID0 : XDMAC Channel 0 Interrupt Disable Bit
bits : 0 - 0 (1 bit)

ID1 : XDMAC Channel 1 Interrupt Disable Bit
bits : 1 - 1 (1 bit)

ID2 : XDMAC Channel 2 Interrupt Disable Bit
bits : 2 - 2 (1 bit)

ID3 : XDMAC Channel 3 Interrupt Disable Bit
bits : 3 - 3 (1 bit)

ID4 : XDMAC Channel 4 Interrupt Disable Bit
bits : 4 - 4 (1 bit)

ID5 : XDMAC Channel 5 Interrupt Disable Bit
bits : 5 - 5 (1 bit)

ID6 : XDMAC Channel 6 Interrupt Disable Bit
bits : 6 - 6 (1 bit)

ID7 : XDMAC Channel 7 Interrupt Disable Bit
bits : 7 - 7 (1 bit)

ID8 : XDMAC Channel 8 Interrupt Disable Bit
bits : 8 - 8 (1 bit)

ID9 : XDMAC Channel 9 Interrupt Disable Bit
bits : 9 - 9 (1 bit)

ID10 : XDMAC Channel 10 Interrupt Disable Bit
bits : 10 - 10 (1 bit)

ID11 : XDMAC Channel 11 Interrupt Disable Bit
bits : 11 - 11 (1 bit)

ID12 : XDMAC Channel 12 Interrupt Disable Bit
bits : 12 - 12 (1 bit)

ID13 : XDMAC Channel 13 Interrupt Disable Bit
bits : 13 - 13 (1 bit)

ID14 : XDMAC Channel 14 Interrupt Disable Bit
bits : 14 - 14 (1 bit)

ID15 : XDMAC Channel 15 Interrupt Disable Bit
bits : 15 - 15 (1 bit)

ID16 : XDMAC Channel 16 Interrupt Disable Bit
bits : 16 - 16 (1 bit)

ID17 : XDMAC Channel 17 Interrupt Disable Bit
bits : 17 - 17 (1 bit)

ID18 : XDMAC Channel 18 Interrupt Disable Bit
bits : 18 - 18 (1 bit)

ID19 : XDMAC Channel 19 Interrupt Disable Bit
bits : 19 - 19 (1 bit)

ID20 : XDMAC Channel 20 Interrupt Disable Bit
bits : 20 - 20 (1 bit)

ID21 : XDMAC Channel 21 Interrupt Disable Bit
bits : 21 - 21 (1 bit)

ID22 : XDMAC Channel 22 Interrupt Disable Bit
bits : 22 - 22 (1 bit)

ID23 : XDMAC Channel 23 Interrupt Disable Bit
bits : 23 - 23 (1 bit)


CSA

Channel Source Address Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSA CSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)


GIM

Global Interrupt Mask Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GIM GIM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IM0 IM1 IM2 IM3 IM4 IM5 IM6 IM7 IM8 IM9 IM10 IM11 IM12 IM13 IM14 IM15 IM16 IM17 IM18 IM19 IM20 IM21 IM22 IM23

IM0 : XDMAC Channel 0 Interrupt Mask Bit
bits : 0 - 0 (1 bit)

IM1 : XDMAC Channel 1 Interrupt Mask Bit
bits : 1 - 1 (1 bit)

IM2 : XDMAC Channel 2 Interrupt Mask Bit
bits : 2 - 2 (1 bit)

IM3 : XDMAC Channel 3 Interrupt Mask Bit
bits : 3 - 3 (1 bit)

IM4 : XDMAC Channel 4 Interrupt Mask Bit
bits : 4 - 4 (1 bit)

IM5 : XDMAC Channel 5 Interrupt Mask Bit
bits : 5 - 5 (1 bit)

IM6 : XDMAC Channel 6 Interrupt Mask Bit
bits : 6 - 6 (1 bit)

IM7 : XDMAC Channel 7 Interrupt Mask Bit
bits : 7 - 7 (1 bit)

IM8 : XDMAC Channel 8 Interrupt Mask Bit
bits : 8 - 8 (1 bit)

IM9 : XDMAC Channel 9 Interrupt Mask Bit
bits : 9 - 9 (1 bit)

IM10 : XDMAC Channel 10 Interrupt Mask Bit
bits : 10 - 10 (1 bit)

IM11 : XDMAC Channel 11 Interrupt Mask Bit
bits : 11 - 11 (1 bit)

IM12 : XDMAC Channel 12 Interrupt Mask Bit
bits : 12 - 12 (1 bit)

IM13 : XDMAC Channel 13 Interrupt Mask Bit
bits : 13 - 13 (1 bit)

IM14 : XDMAC Channel 14 Interrupt Mask Bit
bits : 14 - 14 (1 bit)

IM15 : XDMAC Channel 15 Interrupt Mask Bit
bits : 15 - 15 (1 bit)

IM16 : XDMAC Channel 16 Interrupt Mask Bit
bits : 16 - 16 (1 bit)

IM17 : XDMAC Channel 17 Interrupt Mask Bit
bits : 17 - 17 (1 bit)

IM18 : XDMAC Channel 18 Interrupt Mask Bit
bits : 18 - 18 (1 bit)

IM19 : XDMAC Channel 19 Interrupt Mask Bit
bits : 19 - 19 (1 bit)

IM20 : XDMAC Channel 20 Interrupt Mask Bit
bits : 20 - 20 (1 bit)

IM21 : XDMAC Channel 21 Interrupt Mask Bit
bits : 21 - 21 (1 bit)

IM22 : XDMAC Channel 22 Interrupt Mask Bit
bits : 22 - 22 (1 bit)

IM23 : XDMAC Channel 23 Interrupt Mask Bit
bits : 23 - 23 (1 bit)


CDA

Channel Destination Address Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDA CDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)


GIS

Global Interrupt Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GIS GIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IS0 IS1 IS2 IS3 IS4 IS5 IS6 IS7 IS8 IS9 IS10 IS11 IS12 IS13 IS14 IS15 IS16 IS17 IS18 IS19 IS20 IS21 IS22 IS23

IS0 : XDMAC Channel 0 Interrupt Status Bit
bits : 0 - 0 (1 bit)

IS1 : XDMAC Channel 1 Interrupt Status Bit
bits : 1 - 1 (1 bit)

IS2 : XDMAC Channel 2 Interrupt Status Bit
bits : 2 - 2 (1 bit)

IS3 : XDMAC Channel 3 Interrupt Status Bit
bits : 3 - 3 (1 bit)

IS4 : XDMAC Channel 4 Interrupt Status Bit
bits : 4 - 4 (1 bit)

IS5 : XDMAC Channel 5 Interrupt Status Bit
bits : 5 - 5 (1 bit)

IS6 : XDMAC Channel 6 Interrupt Status Bit
bits : 6 - 6 (1 bit)

IS7 : XDMAC Channel 7 Interrupt Status Bit
bits : 7 - 7 (1 bit)

IS8 : XDMAC Channel 8 Interrupt Status Bit
bits : 8 - 8 (1 bit)

IS9 : XDMAC Channel 9 Interrupt Status Bit
bits : 9 - 9 (1 bit)

IS10 : XDMAC Channel 10 Interrupt Status Bit
bits : 10 - 10 (1 bit)

IS11 : XDMAC Channel 11 Interrupt Status Bit
bits : 11 - 11 (1 bit)

IS12 : XDMAC Channel 12 Interrupt Status Bit
bits : 12 - 12 (1 bit)

IS13 : XDMAC Channel 13 Interrupt Status Bit
bits : 13 - 13 (1 bit)

IS14 : XDMAC Channel 14 Interrupt Status Bit
bits : 14 - 14 (1 bit)

IS15 : XDMAC Channel 15 Interrupt Status Bit
bits : 15 - 15 (1 bit)

IS16 : XDMAC Channel 16 Interrupt Status Bit
bits : 16 - 16 (1 bit)

IS17 : XDMAC Channel 17 Interrupt Status Bit
bits : 17 - 17 (1 bit)

IS18 : XDMAC Channel 18 Interrupt Status Bit
bits : 18 - 18 (1 bit)

IS19 : XDMAC Channel 19 Interrupt Status Bit
bits : 19 - 19 (1 bit)

IS20 : XDMAC Channel 20 Interrupt Status Bit
bits : 20 - 20 (1 bit)

IS21 : XDMAC Channel 21 Interrupt Status Bit
bits : 21 - 21 (1 bit)

IS22 : XDMAC Channel 22 Interrupt Status Bit
bits : 22 - 22 (1 bit)

IS23 : XDMAC Channel 23 Interrupt Status Bit
bits : 23 - 23 (1 bit)


CNDA

Channel Next Descriptor Address Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDA CNDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)


GE

Global Channel Enable Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GE GE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN0 EN1 EN2 EN3 EN4 EN5 EN6 EN7 EN8 EN9 EN10 EN11 EN12 EN13 EN14 EN15 EN16 EN17 EN18 EN19 EN20 EN21 EN22 EN23

EN0 : XDMAC Channel 0 Enable Bit
bits : 0 - 0 (1 bit)

EN1 : XDMAC Channel 1 Enable Bit
bits : 1 - 1 (1 bit)

EN2 : XDMAC Channel 2 Enable Bit
bits : 2 - 2 (1 bit)

EN3 : XDMAC Channel 3 Enable Bit
bits : 3 - 3 (1 bit)

EN4 : XDMAC Channel 4 Enable Bit
bits : 4 - 4 (1 bit)

EN5 : XDMAC Channel 5 Enable Bit
bits : 5 - 5 (1 bit)

EN6 : XDMAC Channel 6 Enable Bit
bits : 6 - 6 (1 bit)

EN7 : XDMAC Channel 7 Enable Bit
bits : 7 - 7 (1 bit)

EN8 : XDMAC Channel 8 Enable Bit
bits : 8 - 8 (1 bit)

EN9 : XDMAC Channel 9 Enable Bit
bits : 9 - 9 (1 bit)

EN10 : XDMAC Channel 10 Enable Bit
bits : 10 - 10 (1 bit)

EN11 : XDMAC Channel 11 Enable Bit
bits : 11 - 11 (1 bit)

EN12 : XDMAC Channel 12 Enable Bit
bits : 12 - 12 (1 bit)

EN13 : XDMAC Channel 13 Enable Bit
bits : 13 - 13 (1 bit)

EN14 : XDMAC Channel 14 Enable Bit
bits : 14 - 14 (1 bit)

EN15 : XDMAC Channel 15 Enable Bit
bits : 15 - 15 (1 bit)

EN16 : XDMAC Channel 16 Enable Bit
bits : 16 - 16 (1 bit)

EN17 : XDMAC Channel 17 Enable Bit
bits : 17 - 17 (1 bit)

EN18 : XDMAC Channel 18 Enable Bit
bits : 18 - 18 (1 bit)

EN19 : XDMAC Channel 19 Enable Bit
bits : 19 - 19 (1 bit)

EN20 : XDMAC Channel 20 Enable Bit
bits : 20 - 20 (1 bit)

EN21 : XDMAC Channel 21 Enable Bit
bits : 21 - 21 (1 bit)

EN22 : XDMAC Channel 22 Enable Bit
bits : 22 - 22 (1 bit)

EN23 : XDMAC Channel 23 Enable Bit
bits : 23 - 23 (1 bit)


CNDC

Channel Next Descriptor Control Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDC CNDC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)

Enumeration: NDESelect

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)

Enumeration: NDSUPSelect

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)

Enumeration: NDDUPSelect

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)

Enumeration: NDVIEWSelect

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


GD

Global Channel Disable Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GD GD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DI9 DI10 DI11 DI12 DI13 DI14 DI15 DI16 DI17 DI18 DI19 DI20 DI21 DI22 DI23

DI0 : XDMAC Channel 0 Disable Bit
bits : 0 - 0 (1 bit)

DI1 : XDMAC Channel 1 Disable Bit
bits : 1 - 1 (1 bit)

DI2 : XDMAC Channel 2 Disable Bit
bits : 2 - 2 (1 bit)

DI3 : XDMAC Channel 3 Disable Bit
bits : 3 - 3 (1 bit)

DI4 : XDMAC Channel 4 Disable Bit
bits : 4 - 4 (1 bit)

DI5 : XDMAC Channel 5 Disable Bit
bits : 5 - 5 (1 bit)

DI6 : XDMAC Channel 6 Disable Bit
bits : 6 - 6 (1 bit)

DI7 : XDMAC Channel 7 Disable Bit
bits : 7 - 7 (1 bit)

DI8 : XDMAC Channel 8 Disable Bit
bits : 8 - 8 (1 bit)

DI9 : XDMAC Channel 9 Disable Bit
bits : 9 - 9 (1 bit)

DI10 : XDMAC Channel 10 Disable Bit
bits : 10 - 10 (1 bit)

DI11 : XDMAC Channel 11 Disable Bit
bits : 11 - 11 (1 bit)

DI12 : XDMAC Channel 12 Disable Bit
bits : 12 - 12 (1 bit)

DI13 : XDMAC Channel 13 Disable Bit
bits : 13 - 13 (1 bit)

DI14 : XDMAC Channel 14 Disable Bit
bits : 14 - 14 (1 bit)

DI15 : XDMAC Channel 15 Disable Bit
bits : 15 - 15 (1 bit)

DI16 : XDMAC Channel 16 Disable Bit
bits : 16 - 16 (1 bit)

DI17 : XDMAC Channel 17 Disable Bit
bits : 17 - 17 (1 bit)

DI18 : XDMAC Channel 18 Disable Bit
bits : 18 - 18 (1 bit)

DI19 : XDMAC Channel 19 Disable Bit
bits : 19 - 19 (1 bit)

DI20 : XDMAC Channel 20 Disable Bit
bits : 20 - 20 (1 bit)

DI21 : XDMAC Channel 21 Disable Bit
bits : 21 - 21 (1 bit)

DI22 : XDMAC Channel 22 Disable Bit
bits : 22 - 22 (1 bit)

DI23 : XDMAC Channel 23 Disable Bit
bits : 23 - 23 (1 bit)


CUBC

Channel Microblock Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CUBC CUBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)


GS

Global Channel Status Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GS GS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ST0 ST1 ST2 ST3 ST4 ST5 ST6 ST7 ST8 ST9 ST10 ST11 ST12 ST13 ST14 ST15 ST16 ST17 ST18 ST19 ST20 ST21 ST22 ST23

ST0 : XDMAC Channel 0 Status Bit
bits : 0 - 0 (1 bit)

ST1 : XDMAC Channel 1 Status Bit
bits : 1 - 1 (1 bit)

ST2 : XDMAC Channel 2 Status Bit
bits : 2 - 2 (1 bit)

ST3 : XDMAC Channel 3 Status Bit
bits : 3 - 3 (1 bit)

ST4 : XDMAC Channel 4 Status Bit
bits : 4 - 4 (1 bit)

ST5 : XDMAC Channel 5 Status Bit
bits : 5 - 5 (1 bit)

ST6 : XDMAC Channel 6 Status Bit
bits : 6 - 6 (1 bit)

ST7 : XDMAC Channel 7 Status Bit
bits : 7 - 7 (1 bit)

ST8 : XDMAC Channel 8 Status Bit
bits : 8 - 8 (1 bit)

ST9 : XDMAC Channel 9 Status Bit
bits : 9 - 9 (1 bit)

ST10 : XDMAC Channel 10 Status Bit
bits : 10 - 10 (1 bit)

ST11 : XDMAC Channel 11 Status Bit
bits : 11 - 11 (1 bit)

ST12 : XDMAC Channel 12 Status Bit
bits : 12 - 12 (1 bit)

ST13 : XDMAC Channel 13 Status Bit
bits : 13 - 13 (1 bit)

ST14 : XDMAC Channel 14 Status Bit
bits : 14 - 14 (1 bit)

ST15 : XDMAC Channel 15 Status Bit
bits : 15 - 15 (1 bit)

ST16 : XDMAC Channel 16 Status Bit
bits : 16 - 16 (1 bit)

ST17 : XDMAC Channel 17 Status Bit
bits : 17 - 17 (1 bit)

ST18 : XDMAC Channel 18 Status Bit
bits : 18 - 18 (1 bit)

ST19 : XDMAC Channel 19 Status Bit
bits : 19 - 19 (1 bit)

ST20 : XDMAC Channel 20 Status Bit
bits : 20 - 20 (1 bit)

ST21 : XDMAC Channel 21 Status Bit
bits : 21 - 21 (1 bit)

ST22 : XDMAC Channel 22 Status Bit
bits : 22 - 22 (1 bit)

ST23 : XDMAC Channel 23 Status Bit
bits : 23 - 23 (1 bit)


CBC

Channel Block Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CBC CBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)


GRS

Global Channel Read Suspend Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GRS GRS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RS0 RS1 RS2 RS3 RS4 RS5 RS6 RS7 RS8 RS9 RS10 RS11 RS12 RS13 RS14 RS15 RS16 RS17 RS18 RS19 RS20 RS21 RS22 RS23

RS0 : XDMAC Channel 0 Read Suspend Bit
bits : 0 - 0 (1 bit)

RS1 : XDMAC Channel 1 Read Suspend Bit
bits : 1 - 1 (1 bit)

RS2 : XDMAC Channel 2 Read Suspend Bit
bits : 2 - 2 (1 bit)

RS3 : XDMAC Channel 3 Read Suspend Bit
bits : 3 - 3 (1 bit)

RS4 : XDMAC Channel 4 Read Suspend Bit
bits : 4 - 4 (1 bit)

RS5 : XDMAC Channel 5 Read Suspend Bit
bits : 5 - 5 (1 bit)

RS6 : XDMAC Channel 6 Read Suspend Bit
bits : 6 - 6 (1 bit)

RS7 : XDMAC Channel 7 Read Suspend Bit
bits : 7 - 7 (1 bit)

RS8 : XDMAC Channel 8 Read Suspend Bit
bits : 8 - 8 (1 bit)

RS9 : XDMAC Channel 9 Read Suspend Bit
bits : 9 - 9 (1 bit)

RS10 : XDMAC Channel 10 Read Suspend Bit
bits : 10 - 10 (1 bit)

RS11 : XDMAC Channel 11 Read Suspend Bit
bits : 11 - 11 (1 bit)

RS12 : XDMAC Channel 12 Read Suspend Bit
bits : 12 - 12 (1 bit)

RS13 : XDMAC Channel 13 Read Suspend Bit
bits : 13 - 13 (1 bit)

RS14 : XDMAC Channel 14 Read Suspend Bit
bits : 14 - 14 (1 bit)

RS15 : XDMAC Channel 15 Read Suspend Bit
bits : 15 - 15 (1 bit)

RS16 : XDMAC Channel 16 Read Suspend Bit
bits : 16 - 16 (1 bit)

RS17 : XDMAC Channel 17 Read Suspend Bit
bits : 17 - 17 (1 bit)

RS18 : XDMAC Channel 18 Read Suspend Bit
bits : 18 - 18 (1 bit)

RS19 : XDMAC Channel 19 Read Suspend Bit
bits : 19 - 19 (1 bit)

RS20 : XDMAC Channel 20 Read Suspend Bit
bits : 20 - 20 (1 bit)

RS21 : XDMAC Channel 21 Read Suspend Bit
bits : 21 - 21 (1 bit)

RS22 : XDMAC Channel 22 Read Suspend Bit
bits : 22 - 22 (1 bit)

RS23 : XDMAC Channel 23 Read Suspend Bit
bits : 23 - 23 (1 bit)


CC

Channel Configuration Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)

Enumeration: TYPESelect

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)

Enumeration: MBSIZESelect

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)

Enumeration: DSYNCSelect

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)

Enumeration: SWREQSelect

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)

Enumeration: MEMSETSelect

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)

Enumeration: CSIZESelect

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)

Enumeration: DWIDTHSelect

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)

Enumeration: SIFSelect

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)

Enumeration: DIFSelect

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)

Enumeration: SAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)

Enumeration: DAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)

Enumeration: INITDSelect

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)

Enumeration: RDIPSelect

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)

Enumeration: WRIPSelect

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)

Enumeration: PERIDSelect

0 : HSMCI

HSMCI

1 : SPI0_TX

SPI0_TX

2 : SPI0_RX

SPI0_RX

5 : QSPI_TX

QSPI_TX

6 : QSPI_RX

QSPI_RX

7 : USART0_TX

USART0_TX

8 : USART0_RX

USART0_RX

9 : USART1_TX

USART1_TX

10 : USART1_RX

USART1_RX

11 : USART2_TX

USART2_TX

12 : USART2_RX

USART2_RX

13 : PWM0

PWM0

14 : TWIHS0_TX

TWIHS0_TX

15 : TWIHS0_RX

TWIHS0_RX

16 : TWIHS1_TX

TWIHS1_TX

17 : TWIHS1_RX

TWIHS1_RX

18 : TWIHS2_TX

TWIHS2_TX

19 : TWIHS2_RX

TWIHS2_RX

20 : UART0_TX

UART0_TX

21 : UART0_RX

UART0_RX

22 : UART1_TX

UART1_TX

23 : UART1_RX

UART1_RX

24 : UART2_TX

UART2_TX

25 : UART2_RX

UART2_RX

26 : UART3_TX

UART3_TX

27 : UART3_RX

UART3_RX

28 : UART4_TX

UART4_TX

29 : UART4_RX

UART4_RX

30 : DACC0

DACC0

31 : DACC1

DACC1

32 : SSC_TX

SSC_TX

33 : SSC_RX

SSC_RX

34 : PIOA

PIOA

35 : AFEC0

AFEC0

36 : AFEC1

AFEC1

37 : AES_TX

AES_TX

38 : AES_RX

AES_RX

39 : PWM1

PWM1

40 : TC0

TC0

41 : TC3

TC3

42 : TC6

TC6

43 : TC9

TC9

44 : I2SC0_TX_LEFT

I2SC0_TX_LEFT

45 : I2SC0_RX_LEFT

I2SC0_RX_LEFT

48 : I2SC0_TX_RIGHT

I2SC0_TX_RIGHT

49 : I2SC0_RX_RIGHT

I2SC0_RX_RIGHT

End of enumeration elements list.


GWS

Global Channel Write Suspend Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GWS GWS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WS0 WS1 WS2 WS3 WS4 WS5 WS6 WS7 WS8 WS9 WS10 WS11 WS12 WS13 WS14 WS15 WS16 WS17 WS18 WS19 WS20 WS21 WS22 WS23

WS0 : XDMAC Channel 0 Write Suspend Bit
bits : 0 - 0 (1 bit)

WS1 : XDMAC Channel 1 Write Suspend Bit
bits : 1 - 1 (1 bit)

WS2 : XDMAC Channel 2 Write Suspend Bit
bits : 2 - 2 (1 bit)

WS3 : XDMAC Channel 3 Write Suspend Bit
bits : 3 - 3 (1 bit)

WS4 : XDMAC Channel 4 Write Suspend Bit
bits : 4 - 4 (1 bit)

WS5 : XDMAC Channel 5 Write Suspend Bit
bits : 5 - 5 (1 bit)

WS6 : XDMAC Channel 6 Write Suspend Bit
bits : 6 - 6 (1 bit)

WS7 : XDMAC Channel 7 Write Suspend Bit
bits : 7 - 7 (1 bit)

WS8 : XDMAC Channel 8 Write Suspend Bit
bits : 8 - 8 (1 bit)

WS9 : XDMAC Channel 9 Write Suspend Bit
bits : 9 - 9 (1 bit)

WS10 : XDMAC Channel 10 Write Suspend Bit
bits : 10 - 10 (1 bit)

WS11 : XDMAC Channel 11 Write Suspend Bit
bits : 11 - 11 (1 bit)

WS12 : XDMAC Channel 12 Write Suspend Bit
bits : 12 - 12 (1 bit)

WS13 : XDMAC Channel 13 Write Suspend Bit
bits : 13 - 13 (1 bit)

WS14 : XDMAC Channel 14 Write Suspend Bit
bits : 14 - 14 (1 bit)

WS15 : XDMAC Channel 15 Write Suspend Bit
bits : 15 - 15 (1 bit)

WS16 : XDMAC Channel 16 Write Suspend Bit
bits : 16 - 16 (1 bit)

WS17 : XDMAC Channel 17 Write Suspend Bit
bits : 17 - 17 (1 bit)

WS18 : XDMAC Channel 18 Write Suspend Bit
bits : 18 - 18 (1 bit)

WS19 : XDMAC Channel 19 Write Suspend Bit
bits : 19 - 19 (1 bit)

WS20 : XDMAC Channel 20 Write Suspend Bit
bits : 20 - 20 (1 bit)

WS21 : XDMAC Channel 21 Write Suspend Bit
bits : 21 - 21 (1 bit)

WS22 : XDMAC Channel 22 Write Suspend Bit
bits : 22 - 22 (1 bit)

WS23 : XDMAC Channel 23 Write Suspend Bit
bits : 23 - 23 (1 bit)


CDS_MSP

Channel Data Stride Memory Set Pattern
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDS_MSP CDS_MSP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)


GRWS

Global Channel Read Write Suspend Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GRWS GRWS write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RWS0 RWS1 RWS2 RWS3 RWS4 RWS5 RWS6 RWS7 RWS8 RWS9 RWS10 RWS11 RWS12 RWS13 RWS14 RWS15 RWS16 RWS17 RWS18 RWS19 RWS20 RWS21 RWS22 RWS23

RWS0 : XDMAC Channel 0 Read Write Suspend Bit
bits : 0 - 0 (1 bit)

RWS1 : XDMAC Channel 1 Read Write Suspend Bit
bits : 1 - 1 (1 bit)

RWS2 : XDMAC Channel 2 Read Write Suspend Bit
bits : 2 - 2 (1 bit)

RWS3 : XDMAC Channel 3 Read Write Suspend Bit
bits : 3 - 3 (1 bit)

RWS4 : XDMAC Channel 4 Read Write Suspend Bit
bits : 4 - 4 (1 bit)

RWS5 : XDMAC Channel 5 Read Write Suspend Bit
bits : 5 - 5 (1 bit)

RWS6 : XDMAC Channel 6 Read Write Suspend Bit
bits : 6 - 6 (1 bit)

RWS7 : XDMAC Channel 7 Read Write Suspend Bit
bits : 7 - 7 (1 bit)

RWS8 : XDMAC Channel 8 Read Write Suspend Bit
bits : 8 - 8 (1 bit)

RWS9 : XDMAC Channel 9 Read Write Suspend Bit
bits : 9 - 9 (1 bit)

RWS10 : XDMAC Channel 10 Read Write Suspend Bit
bits : 10 - 10 (1 bit)

RWS11 : XDMAC Channel 11 Read Write Suspend Bit
bits : 11 - 11 (1 bit)

RWS12 : XDMAC Channel 12 Read Write Suspend Bit
bits : 12 - 12 (1 bit)

RWS13 : XDMAC Channel 13 Read Write Suspend Bit
bits : 13 - 13 (1 bit)

RWS14 : XDMAC Channel 14 Read Write Suspend Bit
bits : 14 - 14 (1 bit)

RWS15 : XDMAC Channel 15 Read Write Suspend Bit
bits : 15 - 15 (1 bit)

RWS16 : XDMAC Channel 16 Read Write Suspend Bit
bits : 16 - 16 (1 bit)

RWS17 : XDMAC Channel 17 Read Write Suspend Bit
bits : 17 - 17 (1 bit)

RWS18 : XDMAC Channel 18 Read Write Suspend Bit
bits : 18 - 18 (1 bit)

RWS19 : XDMAC Channel 19 Read Write Suspend Bit
bits : 19 - 19 (1 bit)

RWS20 : XDMAC Channel 20 Read Write Suspend Bit
bits : 20 - 20 (1 bit)

RWS21 : XDMAC Channel 21 Read Write Suspend Bit
bits : 21 - 21 (1 bit)

RWS22 : XDMAC Channel 22 Read Write Suspend Bit
bits : 22 - 22 (1 bit)

RWS23 : XDMAC Channel 23 Read Write Suspend Bit
bits : 23 - 23 (1 bit)


CSUS

Channel Source Microblock Stride
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSUS CSUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)


GRWR

Global Channel Read Write Resume Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GRWR GRWR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RWR0 RWR1 RWR2 RWR3 RWR4 RWR5 RWR6 RWR7 RWR8 RWR9 RWR10 RWR11 RWR12 RWR13 RWR14 RWR15 RWR16 RWR17 RWR18 RWR19 RWR20 RWR21 RWR22 RWR23

RWR0 : XDMAC Channel 0 Read Write Resume Bit
bits : 0 - 0 (1 bit)

RWR1 : XDMAC Channel 1 Read Write Resume Bit
bits : 1 - 1 (1 bit)

RWR2 : XDMAC Channel 2 Read Write Resume Bit
bits : 2 - 2 (1 bit)

RWR3 : XDMAC Channel 3 Read Write Resume Bit
bits : 3 - 3 (1 bit)

RWR4 : XDMAC Channel 4 Read Write Resume Bit
bits : 4 - 4 (1 bit)

RWR5 : XDMAC Channel 5 Read Write Resume Bit
bits : 5 - 5 (1 bit)

RWR6 : XDMAC Channel 6 Read Write Resume Bit
bits : 6 - 6 (1 bit)

RWR7 : XDMAC Channel 7 Read Write Resume Bit
bits : 7 - 7 (1 bit)

RWR8 : XDMAC Channel 8 Read Write Resume Bit
bits : 8 - 8 (1 bit)

RWR9 : XDMAC Channel 9 Read Write Resume Bit
bits : 9 - 9 (1 bit)

RWR10 : XDMAC Channel 10 Read Write Resume Bit
bits : 10 - 10 (1 bit)

RWR11 : XDMAC Channel 11 Read Write Resume Bit
bits : 11 - 11 (1 bit)

RWR12 : XDMAC Channel 12 Read Write Resume Bit
bits : 12 - 12 (1 bit)

RWR13 : XDMAC Channel 13 Read Write Resume Bit
bits : 13 - 13 (1 bit)

RWR14 : XDMAC Channel 14 Read Write Resume Bit
bits : 14 - 14 (1 bit)

RWR15 : XDMAC Channel 15 Read Write Resume Bit
bits : 15 - 15 (1 bit)

RWR16 : XDMAC Channel 16 Read Write Resume Bit
bits : 16 - 16 (1 bit)

RWR17 : XDMAC Channel 17 Read Write Resume Bit
bits : 17 - 17 (1 bit)

RWR18 : XDMAC Channel 18 Read Write Resume Bit
bits : 18 - 18 (1 bit)

RWR19 : XDMAC Channel 19 Read Write Resume Bit
bits : 19 - 19 (1 bit)

RWR20 : XDMAC Channel 20 Read Write Resume Bit
bits : 20 - 20 (1 bit)

RWR21 : XDMAC Channel 21 Read Write Resume Bit
bits : 21 - 21 (1 bit)

RWR22 : XDMAC Channel 22 Read Write Resume Bit
bits : 22 - 22 (1 bit)

RWR23 : XDMAC Channel 23 Read Write Resume Bit
bits : 23 - 23 (1 bit)


CDUS

Channel Destination Microblock Stride
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDUS CDUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)


GSWR

Global Channel Software Request Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GSWR GSWR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWREQ0 SWREQ1 SWREQ2 SWREQ3 SWREQ4 SWREQ5 SWREQ6 SWREQ7 SWREQ8 SWREQ9 SWREQ10 SWREQ11 SWREQ12 SWREQ13 SWREQ14 SWREQ15 SWREQ16 SWREQ17 SWREQ18 SWREQ19 SWREQ20 SWREQ21 SWREQ22 SWREQ23

SWREQ0 : XDMAC Channel 0 Software Request Bit
bits : 0 - 0 (1 bit)

SWREQ1 : XDMAC Channel 1 Software Request Bit
bits : 1 - 1 (1 bit)

SWREQ2 : XDMAC Channel 2 Software Request Bit
bits : 2 - 2 (1 bit)

SWREQ3 : XDMAC Channel 3 Software Request Bit
bits : 3 - 3 (1 bit)

SWREQ4 : XDMAC Channel 4 Software Request Bit
bits : 4 - 4 (1 bit)

SWREQ5 : XDMAC Channel 5 Software Request Bit
bits : 5 - 5 (1 bit)

SWREQ6 : XDMAC Channel 6 Software Request Bit
bits : 6 - 6 (1 bit)

SWREQ7 : XDMAC Channel 7 Software Request Bit
bits : 7 - 7 (1 bit)

SWREQ8 : XDMAC Channel 8 Software Request Bit
bits : 8 - 8 (1 bit)

SWREQ9 : XDMAC Channel 9 Software Request Bit
bits : 9 - 9 (1 bit)

SWREQ10 : XDMAC Channel 10 Software Request Bit
bits : 10 - 10 (1 bit)

SWREQ11 : XDMAC Channel 11 Software Request Bit
bits : 11 - 11 (1 bit)

SWREQ12 : XDMAC Channel 12 Software Request Bit
bits : 12 - 12 (1 bit)

SWREQ13 : XDMAC Channel 13 Software Request Bit
bits : 13 - 13 (1 bit)

SWREQ14 : XDMAC Channel 14 Software Request Bit
bits : 14 - 14 (1 bit)

SWREQ15 : XDMAC Channel 15 Software Request Bit
bits : 15 - 15 (1 bit)

SWREQ16 : XDMAC Channel 16 Software Request Bit
bits : 16 - 16 (1 bit)

SWREQ17 : XDMAC Channel 17 Software Request Bit
bits : 17 - 17 (1 bit)

SWREQ18 : XDMAC Channel 18 Software Request Bit
bits : 18 - 18 (1 bit)

SWREQ19 : XDMAC Channel 19 Software Request Bit
bits : 19 - 19 (1 bit)

SWREQ20 : XDMAC Channel 20 Software Request Bit
bits : 20 - 20 (1 bit)

SWREQ21 : XDMAC Channel 21 Software Request Bit
bits : 21 - 21 (1 bit)

SWREQ22 : XDMAC Channel 22 Software Request Bit
bits : 22 - 22 (1 bit)

SWREQ23 : XDMAC Channel 23 Software Request Bit
bits : 23 - 23 (1 bit)


GSWS

Global Channel Software Request Status Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GSWS GSWS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRS0 SWRS1 SWRS2 SWRS3 SWRS4 SWRS5 SWRS6 SWRS7 SWRS8 SWRS9 SWRS10 SWRS11 SWRS12 SWRS13 SWRS14 SWRS15 SWRS16 SWRS17 SWRS18 SWRS19 SWRS20 SWRS21 SWRS22 SWRS23

SWRS0 : XDMAC Channel 0 Software Request Status Bit
bits : 0 - 0 (1 bit)

SWRS1 : XDMAC Channel 1 Software Request Status Bit
bits : 1 - 1 (1 bit)

SWRS2 : XDMAC Channel 2 Software Request Status Bit
bits : 2 - 2 (1 bit)

SWRS3 : XDMAC Channel 3 Software Request Status Bit
bits : 3 - 3 (1 bit)

SWRS4 : XDMAC Channel 4 Software Request Status Bit
bits : 4 - 4 (1 bit)

SWRS5 : XDMAC Channel 5 Software Request Status Bit
bits : 5 - 5 (1 bit)

SWRS6 : XDMAC Channel 6 Software Request Status Bit
bits : 6 - 6 (1 bit)

SWRS7 : XDMAC Channel 7 Software Request Status Bit
bits : 7 - 7 (1 bit)

SWRS8 : XDMAC Channel 8 Software Request Status Bit
bits : 8 - 8 (1 bit)

SWRS9 : XDMAC Channel 9 Software Request Status Bit
bits : 9 - 9 (1 bit)

SWRS10 : XDMAC Channel 10 Software Request Status Bit
bits : 10 - 10 (1 bit)

SWRS11 : XDMAC Channel 11 Software Request Status Bit
bits : 11 - 11 (1 bit)

SWRS12 : XDMAC Channel 12 Software Request Status Bit
bits : 12 - 12 (1 bit)

SWRS13 : XDMAC Channel 13 Software Request Status Bit
bits : 13 - 13 (1 bit)

SWRS14 : XDMAC Channel 14 Software Request Status Bit
bits : 14 - 14 (1 bit)

SWRS15 : XDMAC Channel 15 Software Request Status Bit
bits : 15 - 15 (1 bit)

SWRS16 : XDMAC Channel 16 Software Request Status Bit
bits : 16 - 16 (1 bit)

SWRS17 : XDMAC Channel 17 Software Request Status Bit
bits : 17 - 17 (1 bit)

SWRS18 : XDMAC Channel 18 Software Request Status Bit
bits : 18 - 18 (1 bit)

SWRS19 : XDMAC Channel 19 Software Request Status Bit
bits : 19 - 19 (1 bit)

SWRS20 : XDMAC Channel 20 Software Request Status Bit
bits : 20 - 20 (1 bit)

SWRS21 : XDMAC Channel 21 Software Request Status Bit
bits : 21 - 21 (1 bit)

SWRS22 : XDMAC Channel 22 Software Request Status Bit
bits : 22 - 22 (1 bit)

SWRS23 : XDMAC Channel 23 Software Request Status Bit
bits : 23 - 23 (1 bit)


GCFG

Global Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GCFG GCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CGDISREG CGDISPIPE CGDISFIFO CGDISIF BXKBEN

CGDISREG : Configuration Registers Clock Gating Disable
bits : 0 - 0 (1 bit)

CGDISPIPE : Pipeline Clock Gating Disable
bits : 1 - 1 (1 bit)

CGDISFIFO : FIFO Clock Gating Disable
bits : 2 - 2 (1 bit)

CGDISIF : Bus Interface Clock Gating Disable
bits : 3 - 3 (1 bit)

BXKBEN : Boundary X Kilobyte Enable
bits : 8 - 8 (1 bit)


CID

Channel Interrupt Disable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CID CID write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)


GSWF

Global Channel Software Flush Request Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GSWF GSWF write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWF0 SWF1 SWF2 SWF3 SWF4 SWF5 SWF6 SWF7 SWF8 SWF9 SWF10 SWF11 SWF12 SWF13 SWF14 SWF15 SWF16 SWF17 SWF18 SWF19 SWF20 SWF21 SWF22 SWF23

SWF0 : XDMAC Channel 0 Software Flush Request Bit
bits : 0 - 0 (1 bit)

SWF1 : XDMAC Channel 1 Software Flush Request Bit
bits : 1 - 1 (1 bit)

SWF2 : XDMAC Channel 2 Software Flush Request Bit
bits : 2 - 2 (1 bit)

SWF3 : XDMAC Channel 3 Software Flush Request Bit
bits : 3 - 3 (1 bit)

SWF4 : XDMAC Channel 4 Software Flush Request Bit
bits : 4 - 4 (1 bit)

SWF5 : XDMAC Channel 5 Software Flush Request Bit
bits : 5 - 5 (1 bit)

SWF6 : XDMAC Channel 6 Software Flush Request Bit
bits : 6 - 6 (1 bit)

SWF7 : XDMAC Channel 7 Software Flush Request Bit
bits : 7 - 7 (1 bit)

SWF8 : XDMAC Channel 8 Software Flush Request Bit
bits : 8 - 8 (1 bit)

SWF9 : XDMAC Channel 9 Software Flush Request Bit
bits : 9 - 9 (1 bit)

SWF10 : XDMAC Channel 10 Software Flush Request Bit
bits : 10 - 10 (1 bit)

SWF11 : XDMAC Channel 11 Software Flush Request Bit
bits : 11 - 11 (1 bit)

SWF12 : XDMAC Channel 12 Software Flush Request Bit
bits : 12 - 12 (1 bit)

SWF13 : XDMAC Channel 13 Software Flush Request Bit
bits : 13 - 13 (1 bit)

SWF14 : XDMAC Channel 14 Software Flush Request Bit
bits : 14 - 14 (1 bit)

SWF15 : XDMAC Channel 15 Software Flush Request Bit
bits : 15 - 15 (1 bit)

SWF16 : XDMAC Channel 16 Software Flush Request Bit
bits : 16 - 16 (1 bit)

SWF17 : XDMAC Channel 17 Software Flush Request Bit
bits : 17 - 17 (1 bit)

SWF18 : XDMAC Channel 18 Software Flush Request Bit
bits : 18 - 18 (1 bit)

SWF19 : XDMAC Channel 19 Software Flush Request Bit
bits : 19 - 19 (1 bit)

SWF20 : XDMAC Channel 20 Software Flush Request Bit
bits : 20 - 20 (1 bit)

SWF21 : XDMAC Channel 21 Software Flush Request Bit
bits : 21 - 21 (1 bit)

SWF22 : XDMAC Channel 22 Software Flush Request Bit
bits : 22 - 22 (1 bit)

SWF23 : XDMAC Channel 23 Software Flush Request Bit
bits : 23 - 23 (1 bit)


GWAC

Global Weighted Arbiter Configuration Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GWAC GWAC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PW0 PW1 PW2 PW3

PW0 : Pool Weight 0
bits : 0 - 3 (4 bit)

PW1 : Pool Weight 1
bits : 4 - 7 (4 bit)

PW2 : Pool Weight 2
bits : 8 - 11 (4 bit)

PW3 : Pool Weight 3
bits : 12 - 15 (4 bit)


CIM

Channel Interrupt Mask Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIM CIM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)


GIE

Global Interrupt Enable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GIE GIE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IE0 IE1 IE2 IE3 IE4 IE5 IE6 IE7 IE8 IE9 IE10 IE11 IE12 IE13 IE14 IE15 IE16 IE17 IE18 IE19 IE20 IE21 IE22 IE23

IE0 : XDMAC Channel 0 Interrupt Enable Bit
bits : 0 - 0 (1 bit)

IE1 : XDMAC Channel 1 Interrupt Enable Bit
bits : 1 - 1 (1 bit)

IE2 : XDMAC Channel 2 Interrupt Enable Bit
bits : 2 - 2 (1 bit)

IE3 : XDMAC Channel 3 Interrupt Enable Bit
bits : 3 - 3 (1 bit)

IE4 : XDMAC Channel 4 Interrupt Enable Bit
bits : 4 - 4 (1 bit)

IE5 : XDMAC Channel 5 Interrupt Enable Bit
bits : 5 - 5 (1 bit)

IE6 : XDMAC Channel 6 Interrupt Enable Bit
bits : 6 - 6 (1 bit)

IE7 : XDMAC Channel 7 Interrupt Enable Bit
bits : 7 - 7 (1 bit)

IE8 : XDMAC Channel 8 Interrupt Enable Bit
bits : 8 - 8 (1 bit)

IE9 : XDMAC Channel 9 Interrupt Enable Bit
bits : 9 - 9 (1 bit)

IE10 : XDMAC Channel 10 Interrupt Enable Bit
bits : 10 - 10 (1 bit)

IE11 : XDMAC Channel 11 Interrupt Enable Bit
bits : 11 - 11 (1 bit)

IE12 : XDMAC Channel 12 Interrupt Enable Bit
bits : 12 - 12 (1 bit)

IE13 : XDMAC Channel 13 Interrupt Enable Bit
bits : 13 - 13 (1 bit)

IE14 : XDMAC Channel 14 Interrupt Enable Bit
bits : 14 - 14 (1 bit)

IE15 : XDMAC Channel 15 Interrupt Enable Bit
bits : 15 - 15 (1 bit)

IE16 : XDMAC Channel 16 Interrupt Enable Bit
bits : 16 - 16 (1 bit)

IE17 : XDMAC Channel 17 Interrupt Enable Bit
bits : 17 - 17 (1 bit)

IE18 : XDMAC Channel 18 Interrupt Enable Bit
bits : 18 - 18 (1 bit)

IE19 : XDMAC Channel 19 Interrupt Enable Bit
bits : 19 - 19 (1 bit)

IE20 : XDMAC Channel 20 Interrupt Enable Bit
bits : 20 - 20 (1 bit)

IE21 : XDMAC Channel 21 Interrupt Enable Bit
bits : 21 - 21 (1 bit)

IE22 : XDMAC Channel 22 Interrupt Enable Bit
bits : 22 - 22 (1 bit)

IE23 : XDMAC Channel 23 Interrupt Enable Bit
bits : 23 - 23 (1 bit)


CIS

Channel Interrupt Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIS CIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)



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