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USART

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xEC byte (0x0)
mem_usage : registers
protection :

Registers

US_CR_USART_MODE

US_CR_SPI_MODE

US_CR_LIN_MODE

US_IMR_USART_MODE

US_IMR_USART_LIN_MODE

US_IMR_SPI_MODE

US_IMR_LIN_MODE

US_IMR_LON_MODE

US_IMR_LON_SPI_MODE

US_CSR_USART_MODE

US_CSR_USART_LIN_MODE

US_CSR_SPI_MODE

US_CSR_LIN_MODE

US_CSR_LON_MODE

US_CSR_LON_SPI_MODE

US_RHR

US_THR

US_BRGR

US_RTOR

US_TTGR_USART_MODE

US_TTGR_LON_MODE

US_MR_USART_MODE

US_MR_SPI_MODE

US_FIDI_USART_MODE

US_FIDI_LON_MODE

US_NER

US_IF

US_MAN

US_LINMR

US_LINIR

US_LINBRR

US_LONMR

US_LONPR

US_LONDL

US_LONL2HDR

US_LONBL

US_LONB1TX

US_LONB1RX

US_LONPRIO

US_IER_USART_MODE

US_IER_USART_LIN_MODE

US_IER_SPI_MODE

US_IER_LIN_MODE

US_IER_LON_MODE

US_IER_LON_SPI_MODE

US_IDTTX

US_IDTRX

US_ICDIFF

US_IDR_USART_MODE

US_IDR_USART_LIN_MODE

US_IDR_SPI_MODE

US_IDR_LIN_MODE

US_IDR_LON_MODE

US_IDR_LON_SPI_MODE

US_WPMR

US_WPSR


US_CR_USART_MODE

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

US_CR_USART_MODE US_CR_USART_MODE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSTRX RSTTX RXEN RXDIS TXEN TXDIS RSTSTA STTBRK STPBRK STTTO SENDA RSTIT RSTNACK RETTO DTREN DTRDIS RTSEN RTSDIS

RSTRX : Reset Receiver
bits : 2 - 2 (1 bit)

RSTTX : Reset Transmitter
bits : 3 - 3 (1 bit)

RXEN : Receiver Enable
bits : 4 - 4 (1 bit)

RXDIS : Receiver Disable
bits : 5 - 5 (1 bit)

TXEN : Transmitter Enable
bits : 6 - 6 (1 bit)

TXDIS : Transmitter Disable
bits : 7 - 7 (1 bit)

RSTSTA : Reset Status Bits
bits : 8 - 8 (1 bit)

STTBRK : Start Break
bits : 9 - 9 (1 bit)

STPBRK : Stop Break
bits : 10 - 10 (1 bit)

STTTO : Clear TIMEOUT Flag and Start Timeout After Next Character Received
bits : 11 - 11 (1 bit)

SENDA : Send Address
bits : 12 - 12 (1 bit)

RSTIT : Reset Iterations
bits : 13 - 13 (1 bit)

RSTNACK : Reset Non Acknowledge
bits : 14 - 14 (1 bit)

RETTO : Start Timeout Immediately
bits : 15 - 15 (1 bit)

DTREN : Data Terminal Ready Enable
bits : 16 - 16 (1 bit)

DTRDIS : Data Terminal Ready Disable
bits : 17 - 17 (1 bit)

RTSEN : Request to Send Enable
bits : 18 - 18 (1 bit)

RTSDIS : Request to Send Disable
bits : 19 - 19 (1 bit)


US_CR_SPI_MODE

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : US_CR_USART_MODE
reset_Mask : 0x0

US_CR_SPI_MODE US_CR_SPI_MODE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSTRX RSTTX RXEN RXDIS TXEN TXDIS RSTSTA FCS RCS

RSTRX : Reset Receiver
bits : 2 - 2 (1 bit)

RSTTX : Reset Transmitter
bits : 3 - 3 (1 bit)

RXEN : Receiver Enable
bits : 4 - 4 (1 bit)

RXDIS : Receiver Disable
bits : 5 - 5 (1 bit)

TXEN : Transmitter Enable
bits : 6 - 6 (1 bit)

TXDIS : Transmitter Disable
bits : 7 - 7 (1 bit)

RSTSTA : Reset Status Bits
bits : 8 - 8 (1 bit)

FCS : Force SPI Chip Select
bits : 18 - 18 (1 bit)

RCS : Release SPI Chip Select
bits : 19 - 19 (1 bit)


US_CR_LIN_MODE

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : US_CR_USART_MODE
reset_Mask : 0x0

US_CR_LIN_MODE US_CR_LIN_MODE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSTRX RSTTX RXEN RXDIS TXEN TXDIS RSTSTA LINABT LINWKUP

RSTRX : Reset Receiver
bits : 2 - 2 (1 bit)

RSTTX : Reset Transmitter
bits : 3 - 3 (1 bit)

RXEN : Receiver Enable
bits : 4 - 4 (1 bit)

RXDIS : Receiver Disable
bits : 5 - 5 (1 bit)

TXEN : Transmitter Enable
bits : 6 - 6 (1 bit)

TXDIS : Transmitter Disable
bits : 7 - 7 (1 bit)

RSTSTA : Reset Status Bits
bits : 8 - 8 (1 bit)

LINABT : Abort LIN Transmission
bits : 20 - 20 (1 bit)

LINWKUP : Send LIN Wakeup Signal
bits : 21 - 21 (1 bit)


US_IMR_USART_MODE

Interrupt Mask Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

US_IMR_USART_MODE US_IMR_USART_MODE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY RXBRK OVRE FRAME PARE TIMEOUT TXEMPTY ITER NACK RIIC DSRIC DCDIC CTSIC MANE

RXRDY : RXRDY Interrupt Mask
bits : 0 - 0 (1 bit)

TXRDY : TXRDY Interrupt Mask
bits : 1 - 1 (1 bit)

RXBRK : Receiver Break Interrupt Mask
bits : 2 - 2 (1 bit)

OVRE : Overrun Error Interrupt Mask
bits : 5 - 5 (1 bit)

FRAME : Framing Error Interrupt Mask
bits : 6 - 6 (1 bit)

PARE : Parity Error Interrupt Mask
bits : 7 - 7 (1 bit)

TIMEOUT : Timeout Interrupt Mask
bits : 8 - 8 (1 bit)

TXEMPTY : TXEMPTY Interrupt Mask
bits : 9 - 9 (1 bit)

ITER : Max Number of Repetitions Reached Interrupt Mask
bits : 10 - 10 (1 bit)

NACK : Non Acknowledge Interrupt Mask
bits : 13 - 13 (1 bit)

RIIC : Ring Indicator Input Change Mask
bits : 16 - 16 (1 bit)

DSRIC : Data Set Ready Input Change Mask
bits : 17 - 17 (1 bit)

DCDIC : Data Carrier Detect Input Change Interrupt Mask
bits : 18 - 18 (1 bit)

CTSIC : Clear to Send Input Change Interrupt Mask
bits : 19 - 19 (1 bit)

MANE : Manchester Error Interrupt Mask
bits : 24 - 24 (1 bit)


US_IMR_USART_LIN_MODE

Interrupt Mask Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : US_IMR_USART_MODE
reset_Mask : 0x0

US_IMR_USART_LIN_MODE US_IMR_USART_LIN_MODE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY OVRE FRAME PARE TIMEOUT TXEMPTY RIIC DSRIC DCDIC

RXRDY : RXRDY Interrupt Mask
bits : 0 - 0 (1 bit)

TXRDY : TXRDY Interrupt Mask
bits : 1 - 1 (1 bit)

OVRE : Overrun Error Interrupt Mask
bits : 5 - 5 (1 bit)

FRAME : Framing Error Interrupt Mask
bits : 6 - 6 (1 bit)

PARE : Parity Error Interrupt Mask
bits : 7 - 7 (1 bit)

TIMEOUT : Timeout Interrupt Mask
bits : 8 - 8 (1 bit)

TXEMPTY : TXEMPTY Interrupt Mask
bits : 9 - 9 (1 bit)

RIIC : Ring Indicator Input Change Mask
bits : 16 - 16 (1 bit)

DSRIC : Data Set Ready Input Change Mask
bits : 17 - 17 (1 bit)

DCDIC : Data Carrier Detect Input Change Interrupt Mask
bits : 18 - 18 (1 bit)


US_IMR_SPI_MODE

Interrupt Mask Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : US_IMR_USART_MODE
reset_Mask : 0x0

US_IMR_SPI_MODE US_IMR_SPI_MODE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY OVRE TXEMPTY UNRE RIIC DSRIC DCDIC NSSE

RXRDY : RXRDY Interrupt Mask
bits : 0 - 0 (1 bit)

TXRDY : TXRDY Interrupt Mask
bits : 1 - 1 (1 bit)

OVRE : Overrun Error Interrupt Mask
bits : 5 - 5 (1 bit)

TXEMPTY : TXEMPTY Interrupt Mask
bits : 9 - 9 (1 bit)

UNRE : SPI Underrun Error Interrupt Mask
bits : 10 - 10 (1 bit)

RIIC : Ring Indicator Input Change Mask
bits : 16 - 16 (1 bit)

DSRIC : Data Set Ready Input Change Mask
bits : 17 - 17 (1 bit)

DCDIC : Data Carrier Detect Input Change Interrupt Mask
bits : 18 - 18 (1 bit)

NSSE : NSS Line (Driving CTS Pin) Rising or Falling Edge Event
bits : 19 - 19 (1 bit)


US_IMR_LIN_MODE

Interrupt Mask Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : US_IMR_USART_MODE
reset_Mask : 0x0

US_IMR_LIN_MODE US_IMR_LIN_MODE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY OVRE FRAME PARE TIMEOUT TXEMPTY LINBK LINID LINTC RIIC DSRIC DCDIC LINBE LINISFE LINIPE LINCE LINSNRE LINSTE LINHTE

RXRDY : RXRDY Interrupt Mask
bits : 0 - 0 (1 bit)

TXRDY : TXRDY Interrupt Mask
bits : 1 - 1 (1 bit)

OVRE : Overrun Error Interrupt Mask
bits : 5 - 5 (1 bit)

FRAME : Framing Error Interrupt Mask
bits : 6 - 6 (1 bit)

PARE : Parity Error Interrupt Mask
bits : 7 - 7 (1 bit)

TIMEOUT : Timeout Interrupt Mask
bits : 8 - 8 (1 bit)

TXEMPTY : TXEMPTY Interrupt Mask
bits : 9 - 9 (1 bit)

LINBK : LIN Break Sent or LIN Break Received Interrupt Mask
bits : 13 - 13 (1 bit)

LINID : LIN Identifier Sent or LIN Identifier Received Interrupt Mask
bits : 14 - 14 (1 bit)

LINTC : LIN Transfer Completed Interrupt Mask
bits : 15 - 15 (1 bit)

RIIC : Ring Indicator Input Change Mask
bits : 16 - 16 (1 bit)

DSRIC : Data Set Ready Input Change Mask
bits : 17 - 17 (1 bit)

DCDIC : Data Carrier Detect Input Change Interrupt Mask
bits : 18 - 18 (1 bit)

LINBE : LIN Bus Error Interrupt Mask
bits : 25 - 25 (1 bit)

LINISFE : LIN Inconsistent Synch Field Error Interrupt Mask
bits : 26 - 26 (1 bit)

LINIPE : LIN Identifier Parity Interrupt Mask
bits : 27 - 27 (1 bit)

LINCE : LIN Checksum Error Interrupt Mask
bits : 28 - 28 (1 bit)

LINSNRE : LIN Slave Not Responding Error Interrupt Mask
bits : 29 - 29 (1 bit)

LINSTE : LIN Synch Tolerance Error Interrupt Mask
bits : 30 - 30 (1 bit)

LINHTE : LIN Header Timeout Error Interrupt Mask
bits : 31 - 31 (1 bit)


US_IMR_LON_MODE

Interrupt Mask Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : US_IMR_USART_MODE
reset_Mask : 0x0

US_IMR_LON_MODE US_IMR_LON_MODE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY OVRE LSFE LCRCE TXEMPTY UNRE RIIC DSRIC DCDIC LTXD LCOL LFET LRXD LBLOVFE

RXRDY : RXRDY Interrupt Mask
bits : 0 - 0 (1 bit)

TXRDY : TXRDY Interrupt Mask
bits : 1 - 1 (1 bit)

OVRE : Overrun Error Interrupt Mask
bits : 5 - 5 (1 bit)

LSFE : LON Short Frame Error Interrupt Mask
bits : 6 - 6 (1 bit)

LCRCE : LON CRC Error Interrupt Mask
bits : 7 - 7 (1 bit)

TXEMPTY : TXEMPTY Interrupt Mask
bits : 9 - 9 (1 bit)

UNRE : SPI Underrun Error Interrupt Mask
bits : 10 - 10 (1 bit)

RIIC : Ring Indicator Input Change Mask
bits : 16 - 16 (1 bit)

DSRIC : Data Set Ready Input Change Mask
bits : 17 - 17 (1 bit)

DCDIC : Data Carrier Detect Input Change Interrupt Mask
bits : 18 - 18 (1 bit)

LTXD : LON Transmission Done Interrupt Mask
bits : 24 - 24 (1 bit)

LCOL : LON Collision Interrupt Mask
bits : 25 - 25 (1 bit)

LFET : LON Frame Early Termination Interrupt Mask
bits : 26 - 26 (1 bit)

LRXD : LON Reception Done Interrupt Mask
bits : 27 - 27 (1 bit)

LBLOVFE : LON Backlog Overflow Error Interrupt Mask
bits : 28 - 28 (1 bit)


US_IMR_LON_SPI_MODE

Interrupt Mask Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : US_IMR_USART_MODE
reset_Mask : 0x0

US_IMR_LON_SPI_MODE US_IMR_LON_SPI_MODE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY OVRE TXEMPTY UNRE RIIC DSRIC DCDIC

RXRDY : RXRDY Interrupt Mask
bits : 0 - 0 (1 bit)

TXRDY : TXRDY Interrupt Mask
bits : 1 - 1 (1 bit)

OVRE : Overrun Error Interrupt Mask
bits : 5 - 5 (1 bit)

TXEMPTY : TXEMPTY Interrupt Mask
bits : 9 - 9 (1 bit)

UNRE : SPI Underrun Error Interrupt Mask
bits : 10 - 10 (1 bit)

RIIC : Ring Indicator Input Change Mask
bits : 16 - 16 (1 bit)

DSRIC : Data Set Ready Input Change Mask
bits : 17 - 17 (1 bit)

DCDIC : Data Carrier Detect Input Change Interrupt Mask
bits : 18 - 18 (1 bit)


US_CSR_USART_MODE

Channel Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

US_CSR_USART_MODE US_CSR_USART_MODE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY RXBRK OVRE FRAME PARE TIMEOUT TXEMPTY ITER NACK RIIC DSRIC DCDIC CTSIC RI DSR DCD CTS MANERR

RXRDY : Receiver Ready (cleared by reading US_RHR)
bits : 0 - 0 (1 bit)

TXRDY : Transmitter Ready (cleared by writing US_THR)
bits : 1 - 1 (1 bit)

RXBRK : Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA)
bits : 2 - 2 (1 bit)

OVRE : Overrun Error (cleared by writing a one to bit US_CR.RSTSTA)
bits : 5 - 5 (1 bit)

FRAME : Framing Error (cleared by writing a one to bit US_CR.RSTSTA)
bits : 6 - 6 (1 bit)

PARE : Parity Error (cleared by writing a one to bit US_CR.RSTSTA)
bits : 7 - 7 (1 bit)

TIMEOUT : Receiver Timeout (cleared by writing a one to bit US_CR.STTTO)
bits : 8 - 8 (1 bit)

TXEMPTY : Transmitter Empty (cleared by writing US_THR)
bits : 9 - 9 (1 bit)

ITER : Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT)
bits : 10 - 10 (1 bit)

NACK : Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK)
bits : 13 - 13 (1 bit)

RIIC : Ring Indicator Input Change Flag (cleared on read)
bits : 16 - 16 (1 bit)

DSRIC : Data Set Ready Input Change Flag (cleared on read)
bits : 17 - 17 (1 bit)

DCDIC : Data Carrier Detect Input Change Flag (cleared on read)
bits : 18 - 18 (1 bit)

CTSIC : Clear to Send Input Change Flag (cleared on read)
bits : 19 - 19 (1 bit)

RI : Image of RI Input
bits : 20 - 20 (1 bit)

DSR : Image of DSR Input
bits : 21 - 21 (1 bit)

DCD : Image of DCD Input
bits : 22 - 22 (1 bit)

CTS : Image of CTS Input
bits : 23 - 23 (1 bit)

MANERR : Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA)
bits : 24 - 24 (1 bit)


US_CSR_USART_LIN_MODE

Channel Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : US_CSR_USART_MODE
reset_Mask : 0x0

US_CSR_USART_LIN_MODE US_CSR_USART_LIN_MODE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY OVRE FRAME PARE TIMEOUT TXEMPTY RIIC DSRIC DCDIC

RXRDY : Receiver Ready (cleared by reading US_RHR)
bits : 0 - 0 (1 bit)

TXRDY : Transmitter Ready (cleared by writing US_THR)
bits : 1 - 1 (1 bit)

OVRE : Overrun Error (cleared by writing a one to bit US_CR.RSTSTA)
bits : 5 - 5 (1 bit)

FRAME : Framing Error (cleared by writing a one to bit US_CR.RSTSTA)
bits : 6 - 6 (1 bit)

PARE : Parity Error (cleared by writing a one to bit US_CR.RSTSTA)
bits : 7 - 7 (1 bit)

TIMEOUT : Receiver Timeout (cleared by writing a one to bit US_CR.STTTO)
bits : 8 - 8 (1 bit)

TXEMPTY : Transmitter Empty (cleared by writing US_THR)
bits : 9 - 9 (1 bit)

RIIC : Ring Indicator Input Change Flag (cleared on read)
bits : 16 - 16 (1 bit)

DSRIC : Data Set Ready Input Change Flag (cleared on read)
bits : 17 - 17 (1 bit)

DCDIC : Data Carrier Detect Input Change Flag (cleared on read)
bits : 18 - 18 (1 bit)


US_CSR_SPI_MODE

Channel Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : US_CSR_USART_MODE
reset_Mask : 0x0

US_CSR_SPI_MODE US_CSR_SPI_MODE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY OVRE TXEMPTY UNRE RIIC DSRIC DCDIC NSSE NSS

RXRDY : Receiver Ready (cleared by reading US_RHR)
bits : 0 - 0 (1 bit)

TXRDY : Transmitter Ready (cleared by writing US_THR)
bits : 1 - 1 (1 bit)

OVRE : Overrun Error (cleared by writing a one to bit US_CR.RSTSTA)
bits : 5 - 5 (1 bit)

TXEMPTY : Transmitter Empty (cleared by writing US_THR)
bits : 9 - 9 (1 bit)

UNRE : SPI Underrun Error
bits : 10 - 10 (1 bit)

RIIC : Ring Indicator Input Change Flag (cleared on read)
bits : 16 - 16 (1 bit)

DSRIC : Data Set Ready Input Change Flag (cleared on read)
bits : 17 - 17 (1 bit)

DCDIC : Data Carrier Detect Input Change Flag (cleared on read)
bits : 18 - 18 (1 bit)

NSSE : NSS Line (Driving CTS Pin) Rising or Falling Edge Event
bits : 19 - 19 (1 bit)

NSS : Image of NSS Line
bits : 23 - 23 (1 bit)


US_CSR_LIN_MODE

Channel Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : US_CSR_USART_MODE
reset_Mask : 0x0

US_CSR_LIN_MODE US_CSR_LIN_MODE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY OVRE FRAME PARE TIMEOUT TXEMPTY LINBK LINID LINTC RIIC DSRIC DCDIC LINBLS LINBE LINISFE LINIPE LINCE LINSNRE LINSTE LINHTE

RXRDY : Receiver Ready (cleared by reading US_RHR)
bits : 0 - 0 (1 bit)

TXRDY : Transmitter Ready (cleared by writing US_THR)
bits : 1 - 1 (1 bit)

OVRE : Overrun Error (cleared by writing a one to bit US_CR.RSTSTA)
bits : 5 - 5 (1 bit)

FRAME : Framing Error (cleared by writing a one to bit US_CR.RSTSTA)
bits : 6 - 6 (1 bit)

PARE : Parity Error (cleared by writing a one to bit US_CR.RSTSTA)
bits : 7 - 7 (1 bit)

TIMEOUT : Receiver Timeout (cleared by writing a one to bit US_CR.STTTO)
bits : 8 - 8 (1 bit)

TXEMPTY : Transmitter Empty (cleared by writing US_THR)
bits : 9 - 9 (1 bit)

LINBK : LIN Break Sent or LIN Break Received
bits : 13 - 13 (1 bit)

LINID : LIN Identifier Sent or LIN Identifier Received
bits : 14 - 14 (1 bit)

LINTC : LIN Transfer Completed
bits : 15 - 15 (1 bit)

RIIC : Ring Indicator Input Change Flag (cleared on read)
bits : 16 - 16 (1 bit)

DSRIC : Data Set Ready Input Change Flag (cleared on read)
bits : 17 - 17 (1 bit)

DCDIC : Data Carrier Detect Input Change Flag (cleared on read)
bits : 18 - 18 (1 bit)

LINBLS : LIN Bus Line Status
bits : 23 - 23 (1 bit)

LINBE : LIN Bus Error
bits : 25 - 25 (1 bit)

LINISFE : LIN Inconsistent Synch Field Error
bits : 26 - 26 (1 bit)

LINIPE : LIN Identifier Parity Error
bits : 27 - 27 (1 bit)

LINCE : LIN Checksum Error
bits : 28 - 28 (1 bit)

LINSNRE : LIN Slave Not Responding Error Interrupt Mask
bits : 29 - 29 (1 bit)

LINSTE : LIN Synch Tolerance Error
bits : 30 - 30 (1 bit)

LINHTE : LIN Header Timeout Error
bits : 31 - 31 (1 bit)


US_CSR_LON_MODE

Channel Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : US_CSR_USART_MODE
reset_Mask : 0x0

US_CSR_LON_MODE US_CSR_LON_MODE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY OVRE LSFE LCRCE TXEMPTY UNRE RIIC DSRIC DCDIC LTXD LCOL LFET LRXD LBLOVFE

RXRDY : Receiver Ready (cleared by reading US_RHR)
bits : 0 - 0 (1 bit)

TXRDY : Transmitter Ready (cleared by writing US_THR)
bits : 1 - 1 (1 bit)

OVRE : Overrun Error (cleared by writing a one to bit US_CR.RSTSTA)
bits : 5 - 5 (1 bit)

LSFE : LON Short Frame Error
bits : 6 - 6 (1 bit)

LCRCE : LON CRC Error
bits : 7 - 7 (1 bit)

TXEMPTY : Transmitter Empty (cleared by writing US_THR)
bits : 9 - 9 (1 bit)

UNRE : Underrun Error
bits : 10 - 10 (1 bit)

RIIC : Ring Indicator Input Change Flag (cleared on read)
bits : 16 - 16 (1 bit)

DSRIC : Data Set Ready Input Change Flag (cleared on read)
bits : 17 - 17 (1 bit)

DCDIC : Data Carrier Detect Input Change Flag (cleared on read)
bits : 18 - 18 (1 bit)

LTXD : LON Transmission End Flag
bits : 24 - 24 (1 bit)

LCOL : LON Collision Detected Flag
bits : 25 - 25 (1 bit)

LFET : LON Frame Early Termination
bits : 26 - 26 (1 bit)

LRXD : LON Reception End Flag
bits : 27 - 27 (1 bit)

LBLOVFE : LON Backlog Overflow Error
bits : 28 - 28 (1 bit)


US_CSR_LON_SPI_MODE

Channel Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : US_CSR_USART_MODE
reset_Mask : 0x0

US_CSR_LON_SPI_MODE US_CSR_LON_SPI_MODE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY OVRE TXEMPTY UNRE RIIC DSRIC DCDIC

RXRDY : Receiver Ready (cleared by reading US_RHR)
bits : 0 - 0 (1 bit)

TXRDY : Transmitter Ready (cleared by writing US_THR)
bits : 1 - 1 (1 bit)

OVRE : Overrun Error (cleared by writing a one to bit US_CR.RSTSTA)
bits : 5 - 5 (1 bit)

TXEMPTY : Transmitter Empty (cleared by writing US_THR)
bits : 9 - 9 (1 bit)

UNRE : SPI Underrun Error
bits : 10 - 10 (1 bit)

RIIC : Ring Indicator Input Change Flag (cleared on read)
bits : 16 - 16 (1 bit)

DSRIC : Data Set Ready Input Change Flag (cleared on read)
bits : 17 - 17 (1 bit)

DCDIC : Data Carrier Detect Input Change Flag (cleared on read)
bits : 18 - 18 (1 bit)


US_RHR

Receive Holding Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

US_RHR US_RHR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXCHR RXSYNH

RXCHR : Received Character
bits : 0 - 8 (9 bit)

RXSYNH : Received Sync
bits : 15 - 15 (1 bit)


US_THR

Transmit Holding Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

US_THR US_THR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCHR TXSYNH

TXCHR : Character to be Transmitted
bits : 0 - 8 (9 bit)

TXSYNH : Sync Field to be Transmitted
bits : 15 - 15 (1 bit)


US_BRGR

Baud Rate Generator Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

US_BRGR US_BRGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CD FP

CD : Clock Divider
bits : 0 - 15 (16 bit)

FP : Fractional Part
bits : 16 - 18 (3 bit)


US_RTOR

Receiver Timeout Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

US_RTOR US_RTOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TO

TO : Timeout Value
bits : 0 - 16 (17 bit)


US_TTGR_USART_MODE

Transmitter Timeguard Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

US_TTGR_USART_MODE US_TTGR_USART_MODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TG

TG : Timeguard Value
bits : 0 - 7 (8 bit)


US_TTGR_LON_MODE

Transmitter Timeguard Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : US_TTGR_USART_MODE
reset_Mask : 0x0

US_TTGR_LON_MODE US_TTGR_LON_MODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCYCLE

PCYCLE : LON PCYCLE Length
bits : 0 - 23 (24 bit)


US_MR_USART_MODE

Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

US_MR_USART_MODE US_MR_USART_MODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USART_MODE USCLKS CHRL SYNC PAR NBSTOP CHMODE MSBF MODE9 CLKO OVER INACK DSNACK VAR_SYNC INVDATA MAX_ITERATION FILTER MAN MODSYNC ONEBIT

USART_MODE : USART Mode of Operation
bits : 0 - 3 (4 bit)

Enumeration: USART_MODESelect

0x0 : NORMAL

Normal mode

0x1 : RS485

RS485

0x2 : HW_HANDSHAKING

Hardware handshaking

0x3 : MODEM

Modem

0x4 : IS07816_T_0

IS07816 Protocol: T = 0

0x6 : IS07816_T_1

IS07816 Protocol: T = 1

0x8 : IRDA

IrDA

0x9 : LON

LON

0xA : LIN_MASTER

LIN Master mode

0xB : LIN_SLAVE

LIN Slave mode

0xE : SPI_MASTER

SPI Master mode (CLKO must be written to 1 and USCLKS = 0, 1 or 2)

0xF : SPI_SLAVE

SPI Slave mode

End of enumeration elements list.

USCLKS : Clock Selection
bits : 4 - 5 (2 bit)

Enumeration: USCLKSSelect

0x0 : MCK

Peripheral clock is selected

0x1 : DIV

Peripheral clock divided (DIV = 8) is selected

0x2 : PCK

PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1.

0x3 : SCK

Serial clock (SCK) is selected

End of enumeration elements list.

CHRL : Character Length
bits : 6 - 7 (2 bit)

Enumeration: CHRLSelect

0x0 : _5_BIT

Character length is 5 bits

0x1 : _6_BIT

Character length is 6 bits

0x2 : _7_BIT

Character length is 7 bits

0x3 : _8_BIT

Character length is 8 bits

End of enumeration elements list.

SYNC : Synchronous Mode Select
bits : 8 - 8 (1 bit)

PAR : Parity Type
bits : 9 - 11 (3 bit)

Enumeration: PARSelect

0x0 : EVEN

Even parity

0x1 : ODD

Odd parity

0x2 : SPACE

Parity forced to 0 (Space)

0x3 : MARK

Parity forced to 1 (Mark)

0x4 : NO

No parity

0x6 : MULTIDROP

Multidrop mode

End of enumeration elements list.

NBSTOP : Number of Stop Bits
bits : 12 - 13 (2 bit)

Enumeration: NBSTOPSelect

0x0 : _1_BIT

1 stop bit

0x1 : _1_5_BIT

1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)

0x2 : _2_BIT

2 stop bits

End of enumeration elements list.

CHMODE : Channel Mode
bits : 14 - 15 (2 bit)

Enumeration: CHMODESelect

0x0 : NORMAL

Normal mode

0x1 : AUTOMATIC

Automatic Echo. Receiver input is connected to the TXD pin.

0x2 : LOCAL_LOOPBACK

Local Loopback. Transmitter output is connected to the Receiver Input.

0x3 : REMOTE_LOOPBACK

Remote Loopback. RXD pin is internally connected to the TXD pin.

End of enumeration elements list.

MSBF : Bit Order
bits : 16 - 16 (1 bit)

MODE9 : 9-bit Character Length
bits : 17 - 17 (1 bit)

CLKO : Clock Output Select
bits : 18 - 18 (1 bit)

OVER : Oversampling Mode
bits : 19 - 19 (1 bit)

INACK : Inhibit Non Acknowledge
bits : 20 - 20 (1 bit)

DSNACK : Disable Successive NACK
bits : 21 - 21 (1 bit)

VAR_SYNC : Variable Synchronization of Command/Data Sync Start Frame Delimiter
bits : 22 - 22 (1 bit)

INVDATA : Inverted Data
bits : 23 - 23 (1 bit)

MAX_ITERATION : Maximum Number of Automatic Iteration
bits : 24 - 26 (3 bit)

FILTER : Receive Line Filter
bits : 28 - 28 (1 bit)

MAN : Manchester Encoder/Decoder Enable
bits : 29 - 29 (1 bit)

MODSYNC : Manchester Synchronization Mode
bits : 30 - 30 (1 bit)

ONEBIT : Start Frame Delimiter Selector
bits : 31 - 31 (1 bit)


US_MR_SPI_MODE

Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : US_MR_USART_MODE
reset_Mask : 0x0

US_MR_SPI_MODE US_MR_SPI_MODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USART_MODE USCLKS CHRL CPHA CPOL CLKO WRDBT

USART_MODE : USART Mode of Operation
bits : 0 - 3 (4 bit)

Enumeration: USART_MODESelect

0x0 : NORMAL

Normal mode

0x1 : RS485

RS485

0x2 : HW_HANDSHAKING

Hardware handshaking

0x3 : MODEM

Modem

0x4 : IS07816_T_0

IS07816 Protocol: T = 0

0x6 : IS07816_T_1

IS07816 Protocol: T = 1

0x8 : IRDA

IrDA

0x9 : LON

LON

0xA : LIN_MASTER

LIN Master mode

0xB : LIN_SLAVE

LIN Slave mode

0xE : SPI_MASTER

SPI Master mode (CLKO must be written to 1 and USCLKS = 0, 1 or 2)

0xF : SPI_SLAVE

SPI Slave mode

End of enumeration elements list.

USCLKS : Clock Selection
bits : 4 - 5 (2 bit)

Enumeration: USCLKSSelect

0x0 : MCK

Peripheral clock is selected

0x1 : DIV

Peripheral clock divided (DIV = 8) is selected

0x2 : PCK

PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1.

0x3 : SCK

Serial clock (SCK) is selected

End of enumeration elements list.

CHRL : Character Length
bits : 6 - 7 (2 bit)

Enumeration: CHRLSelect

0x0 : _5_BIT

Character length is 5 bits

0x1 : _6_BIT

Character length is 6 bits

0x2 : _7_BIT

Character length is 7 bits

0x3 : _8_BIT

Character length is 8 bits

End of enumeration elements list.

CPHA : SPI Clock Phase
bits : 8 - 8 (1 bit)

CPOL : SPI Clock Polarity
bits : 16 - 16 (1 bit)

CLKO : Clock Output Select
bits : 18 - 18 (1 bit)

WRDBT : Wait Read Data Before Transfer
bits : 20 - 20 (1 bit)


US_FIDI_USART_MODE

FI DI Ratio Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

US_FIDI_USART_MODE US_FIDI_USART_MODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FI_DI_RATIO

FI_DI_RATIO : FI Over DI Ratio Value
bits : 0 - 15 (16 bit)


US_FIDI_LON_MODE

FI DI Ratio Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : US_FIDI_USART_MODE
reset_Mask : 0x0

US_FIDI_LON_MODE US_FIDI_LON_MODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BETA2

BETA2 : LON BETA2 Length
bits : 0 - 23 (24 bit)


US_NER

Number of Errors Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

US_NER US_NER read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NB_ERRORS

NB_ERRORS : Number of Errors
bits : 0 - 7 (8 bit)


US_IF

IrDA Filter Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

US_IF US_IF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRDA_FILTER

IRDA_FILTER : IrDA Filter
bits : 0 - 7 (8 bit)


US_MAN

Manchester Configuration Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

US_MAN US_MAN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX_PL TX_PP TX_MPOL RX_PL RX_PP RX_MPOL ONE DRIFT RXIDLEV

TX_PL : Transmitter Preamble Length
bits : 0 - 3 (4 bit)

TX_PP : Transmitter Preamble Pattern
bits : 8 - 9 (2 bit)

Enumeration: TX_PPSelect

0x0 : ALL_ONE

The preamble is composed of '1's

0x1 : ALL_ZERO

The preamble is composed of '0's

0x2 : ZERO_ONE

The preamble is composed of '01's

0x3 : ONE_ZERO

The preamble is composed of '10's

End of enumeration elements list.

TX_MPOL : Transmitter Manchester Polarity
bits : 12 - 12 (1 bit)

RX_PL : Receiver Preamble Length
bits : 16 - 19 (4 bit)

RX_PP : Receiver Preamble Pattern detected
bits : 24 - 25 (2 bit)

Enumeration: RX_PPSelect

0x0 : ALL_ONE

The preamble is composed of '1's

0x1 : ALL_ZERO

The preamble is composed of '0's

0x2 : ZERO_ONE

The preamble is composed of '01's

0x3 : ONE_ZERO

The preamble is composed of '10's

End of enumeration elements list.

RX_MPOL : Receiver Manchester Polarity
bits : 28 - 28 (1 bit)

ONE : Must Be Set to 1
bits : 29 - 29 (1 bit)

DRIFT : Drift Compensation
bits : 30 - 30 (1 bit)

RXIDLEV : Receiver Idle Value
bits : 31 - 31 (1 bit)


US_LINMR

LIN Mode Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

US_LINMR US_LINMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NACT PARDIS CHKDIS CHKTYP DLM FSDIS WKUPTYP DLC PDCM SYNCDIS

NACT : LIN Node Action
bits : 0 - 1 (2 bit)

Enumeration: NACTSelect

0x0 : PUBLISH

The USART transmits the response.

0x1 : SUBSCRIBE

The USART receives the response.

0x2 : IGNORE

The USART does not transmit and does not receive the response.

End of enumeration elements list.

PARDIS : Parity Disable
bits : 2 - 2 (1 bit)

CHKDIS : Checksum Disable
bits : 3 - 3 (1 bit)

CHKTYP : Checksum Type
bits : 4 - 4 (1 bit)

DLM : Data Length Mode
bits : 5 - 5 (1 bit)

FSDIS : Frame Slot Mode Disable
bits : 6 - 6 (1 bit)

WKUPTYP : Wakeup Signal Type
bits : 7 - 7 (1 bit)

DLC : Data Length Control
bits : 8 - 15 (8 bit)

PDCM : DMAC Mode
bits : 16 - 16 (1 bit)

SYNCDIS : Synchronization Disable
bits : 17 - 17 (1 bit)


US_LINIR

LIN Identifier Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

US_LINIR US_LINIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDCHR

IDCHR : Identifier Character
bits : 0 - 7 (8 bit)


US_LINBRR

LIN Baud Rate Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

US_LINBRR US_LINBRR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LINCD LINFP

LINCD : Clock Divider after Synchronization
bits : 0 - 15 (16 bit)

LINFP : Fractional Part after Synchronization
bits : 16 - 18 (3 bit)


US_LONMR

LON Mode Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

US_LONMR US_LONMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMMT COLDET TCOL CDTAIL DMAM LCDS EOFS

COMMT : LON comm_type Parameter Value
bits : 0 - 0 (1 bit)

COLDET : LON Collision Detection Feature
bits : 1 - 1 (1 bit)

TCOL : Terminate Frame upon Collision Notification
bits : 2 - 2 (1 bit)

CDTAIL : LON Collision Detection on Frame Tail
bits : 3 - 3 (1 bit)

DMAM : LON DMA Mode
bits : 4 - 4 (1 bit)

LCDS : LON Collision Detection Source
bits : 5 - 5 (1 bit)

EOFS : End of Frame Condition Size
bits : 16 - 23 (8 bit)


US_LONPR

LON Preamble Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

US_LONPR US_LONPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LONPL

LONPL : LON Preamble Length
bits : 0 - 13 (14 bit)


US_LONDL

LON Data Length Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

US_LONDL US_LONDL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LONDL

LONDL : LON Data Length
bits : 0 - 7 (8 bit)


US_LONL2HDR

LON L2HDR Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

US_LONL2HDR US_LONL2HDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLI ALTP PB

BLI : LON Backlog Increment
bits : 0 - 5 (6 bit)

ALTP : LON Alternate Path Bit
bits : 6 - 6 (1 bit)

PB : LON Priority Bit
bits : 7 - 7 (1 bit)


US_LONBL

LON Backlog Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

US_LONBL US_LONBL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LONBL

LONBL : LON Node Backlog Value
bits : 0 - 5 (6 bit)


US_LONB1TX

LON Beta1 Tx Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

US_LONB1TX US_LONB1TX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BETA1TX

BETA1TX : LON Beta1 Length after Transmission
bits : 0 - 23 (24 bit)


US_LONB1RX

LON Beta1 Rx Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

US_LONB1RX US_LONB1RX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BETA1RX

BETA1RX : LON Beta1 Length after Reception
bits : 0 - 23 (24 bit)


US_LONPRIO

LON Priority Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

US_LONPRIO US_LONPRIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSNB NPS

PSNB : LON Priority Slot Number
bits : 0 - 6 (7 bit)

NPS : LON Node Priority Slot
bits : 8 - 14 (7 bit)


US_IER_USART_MODE

Interrupt Enable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

US_IER_USART_MODE US_IER_USART_MODE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY RXBRK OVRE FRAME PARE TIMEOUT TXEMPTY ITER NACK RIIC DSRIC DCDIC CTSIC MANE

RXRDY : RXRDY Interrupt Enable
bits : 0 - 0 (1 bit)

TXRDY : TXRDY Interrupt Enable
bits : 1 - 1 (1 bit)

RXBRK : Receiver Break Interrupt Enable
bits : 2 - 2 (1 bit)

OVRE : Overrun Error Interrupt Enable
bits : 5 - 5 (1 bit)

FRAME : Framing Error Interrupt Enable
bits : 6 - 6 (1 bit)

PARE : Parity Error Interrupt Enable
bits : 7 - 7 (1 bit)

TIMEOUT : Timeout Interrupt Enable
bits : 8 - 8 (1 bit)

TXEMPTY : TXEMPTY Interrupt Enable
bits : 9 - 9 (1 bit)

ITER : Max number of Repetitions Reached Interrupt Enable
bits : 10 - 10 (1 bit)

NACK : Non Acknowledge Interrupt Enable
bits : 13 - 13 (1 bit)

RIIC : Ring Indicator Input Change Enable
bits : 16 - 16 (1 bit)

DSRIC : Data Set Ready Input Change Enable
bits : 17 - 17 (1 bit)

DCDIC : Data Carrier Detect Input Change Interrupt Enable
bits : 18 - 18 (1 bit)

CTSIC : Clear to Send Input Change Interrupt Enable
bits : 19 - 19 (1 bit)

MANE : Manchester Error Interrupt Enable
bits : 24 - 24 (1 bit)


US_IER_USART_LIN_MODE

Interrupt Enable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : US_IER_USART_MODE
reset_Mask : 0x0

US_IER_USART_LIN_MODE US_IER_USART_LIN_MODE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY OVRE FRAME PARE TIMEOUT TXEMPTY

RXRDY : RXRDY Interrupt Enable
bits : 0 - 0 (1 bit)

TXRDY : TXRDY Interrupt Enable
bits : 1 - 1 (1 bit)

OVRE : Overrun Error Interrupt Enable
bits : 5 - 5 (1 bit)

FRAME : Framing Error Interrupt Enable
bits : 6 - 6 (1 bit)

PARE : Parity Error Interrupt Enable
bits : 7 - 7 (1 bit)

TIMEOUT : Timeout Interrupt Enable
bits : 8 - 8 (1 bit)

TXEMPTY : TXEMPTY Interrupt Enable
bits : 9 - 9 (1 bit)


US_IER_SPI_MODE

Interrupt Enable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : US_IER_USART_MODE
reset_Mask : 0x0

US_IER_SPI_MODE US_IER_SPI_MODE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY OVRE TXEMPTY UNRE NSSE

RXRDY : RXRDY Interrupt Enable
bits : 0 - 0 (1 bit)

TXRDY : TXRDY Interrupt Enable
bits : 1 - 1 (1 bit)

OVRE : Overrun Error Interrupt Enable
bits : 5 - 5 (1 bit)

TXEMPTY : TXEMPTY Interrupt Enable
bits : 9 - 9 (1 bit)

UNRE : Underrun Error Interrupt Enable
bits : 10 - 10 (1 bit)

NSSE : NSS Line (Driving CTS Pin) Rising or Falling Edge Event
bits : 19 - 19 (1 bit)


US_IER_LIN_MODE

Interrupt Enable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : US_IER_USART_MODE
reset_Mask : 0x0

US_IER_LIN_MODE US_IER_LIN_MODE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY OVRE FRAME PARE TIMEOUT TXEMPTY LINBK LINID LINTC LINBE LINISFE LINIPE LINCE LINSNRE LINSTE LINHTE

RXRDY : RXRDY Interrupt Enable
bits : 0 - 0 (1 bit)

TXRDY : TXRDY Interrupt Enable
bits : 1 - 1 (1 bit)

OVRE : Overrun Error Interrupt Enable
bits : 5 - 5 (1 bit)

FRAME : Framing Error Interrupt Enable
bits : 6 - 6 (1 bit)

PARE : Parity Error Interrupt Enable
bits : 7 - 7 (1 bit)

TIMEOUT : Timeout Interrupt Enable
bits : 8 - 8 (1 bit)

TXEMPTY : TXEMPTY Interrupt Enable
bits : 9 - 9 (1 bit)

LINBK : LIN Break Sent or LIN Break Received Interrupt Enable
bits : 13 - 13 (1 bit)

LINID : LIN Identifier Sent or LIN Identifier Received Interrupt Enable
bits : 14 - 14 (1 bit)

LINTC : LIN Transfer Completed Interrupt Enable
bits : 15 - 15 (1 bit)

LINBE : LIN Bus Error Interrupt Enable
bits : 25 - 25 (1 bit)

LINISFE : LIN Inconsistent Synch Field Error Interrupt Enable
bits : 26 - 26 (1 bit)

LINIPE : LIN Identifier Parity Interrupt Enable
bits : 27 - 27 (1 bit)

LINCE : LIN Checksum Error Interrupt Enable
bits : 28 - 28 (1 bit)

LINSNRE : LIN Slave Not Responding Error Interrupt Enable
bits : 29 - 29 (1 bit)

LINSTE : LIN Synch Tolerance Error Interrupt Enable
bits : 30 - 30 (1 bit)

LINHTE : LIN Header Timeout Error Interrupt Enable
bits : 31 - 31 (1 bit)


US_IER_LON_MODE

Interrupt Enable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : US_IER_USART_MODE
reset_Mask : 0x0

US_IER_LON_MODE US_IER_LON_MODE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY OVRE LSFE LCRCE TXEMPTY UNRE LTXD LCOL LFET LRXD LBLOVFE

RXRDY : RXRDY Interrupt Enable
bits : 0 - 0 (1 bit)

TXRDY : TXRDY Interrupt Enable
bits : 1 - 1 (1 bit)

OVRE : Overrun Error Interrupt Enable
bits : 5 - 5 (1 bit)

LSFE : LON Short Frame Error Interrupt Enable
bits : 6 - 6 (1 bit)

LCRCE : LON CRC Error Interrupt Enable
bits : 7 - 7 (1 bit)

TXEMPTY : TXEMPTY Interrupt Enable
bits : 9 - 9 (1 bit)

UNRE : Underrun Error Interrupt Enable
bits : 10 - 10 (1 bit)

LTXD : LON Transmission Done Interrupt Enable
bits : 24 - 24 (1 bit)

LCOL : LON Collision Interrupt Enable
bits : 25 - 25 (1 bit)

LFET : LON Frame Early Termination Interrupt Enable
bits : 26 - 26 (1 bit)

LRXD : LON Reception Done Interrupt Enable
bits : 27 - 27 (1 bit)

LBLOVFE : LON Backlog Overflow Error Interrupt Enable
bits : 28 - 28 (1 bit)


US_IER_LON_SPI_MODE

Interrupt Enable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : US_IER_USART_MODE
reset_Mask : 0x0

US_IER_LON_SPI_MODE US_IER_LON_SPI_MODE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY OVRE TXEMPTY UNRE

RXRDY : RXRDY Interrupt Enable
bits : 0 - 0 (1 bit)

TXRDY : TXRDY Interrupt Enable
bits : 1 - 1 (1 bit)

OVRE : Overrun Error Interrupt Enable
bits : 5 - 5 (1 bit)

TXEMPTY : TXEMPTY Interrupt Enable
bits : 9 - 9 (1 bit)

UNRE : Underrun Error Interrupt Enable
bits : 10 - 10 (1 bit)


US_IDTTX

LON IDT Tx Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

US_IDTTX US_IDTTX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDTTX

IDTTX : LON Indeterminate Time after Transmission (comm_type = 1 mode only)
bits : 0 - 23 (24 bit)


US_IDTRX

LON IDT Rx Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

US_IDTRX US_IDTRX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDTRX

IDTRX : LON Indeterminate Time after Reception (comm_type = 1 mode only)
bits : 0 - 23 (24 bit)


US_ICDIFF

IC DIFF Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

US_ICDIFF US_ICDIFF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICDIFF

ICDIFF : IC Differentiator Number
bits : 0 - 3 (4 bit)


US_IDR_USART_MODE

Interrupt Disable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

US_IDR_USART_MODE US_IDR_USART_MODE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY RXBRK OVRE FRAME PARE TIMEOUT TXEMPTY ITER NACK RIIC DSRIC DCDIC CTSIC MANE

RXRDY : RXRDY Interrupt Disable
bits : 0 - 0 (1 bit)

TXRDY : TXRDY Interrupt Disable
bits : 1 - 1 (1 bit)

RXBRK : Receiver Break Interrupt Disable
bits : 2 - 2 (1 bit)

OVRE : Overrun Error Interrupt Enable
bits : 5 - 5 (1 bit)

FRAME : Framing Error Interrupt Disable
bits : 6 - 6 (1 bit)

PARE : Parity Error Interrupt Disable
bits : 7 - 7 (1 bit)

TIMEOUT : Timeout Interrupt Disable
bits : 8 - 8 (1 bit)

TXEMPTY : TXEMPTY Interrupt Disable
bits : 9 - 9 (1 bit)

ITER : Max Number of Repetitions Reached Interrupt Disable
bits : 10 - 10 (1 bit)

NACK : Non Acknowledge Interrupt Disable
bits : 13 - 13 (1 bit)

RIIC : Ring Indicator Input Change Disable
bits : 16 - 16 (1 bit)

DSRIC : Data Set Ready Input Change Disable
bits : 17 - 17 (1 bit)

DCDIC : Data Carrier Detect Input Change Interrupt Disable
bits : 18 - 18 (1 bit)

CTSIC : Clear to Send Input Change Interrupt Disable
bits : 19 - 19 (1 bit)

MANE : Manchester Error Interrupt Disable
bits : 24 - 24 (1 bit)


US_IDR_USART_LIN_MODE

Interrupt Disable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : US_IDR_USART_MODE
reset_Mask : 0x0

US_IDR_USART_LIN_MODE US_IDR_USART_LIN_MODE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY OVRE FRAME PARE TIMEOUT TXEMPTY RIIC DSRIC DCDIC

RXRDY : RXRDY Interrupt Disable
bits : 0 - 0 (1 bit)

TXRDY : TXRDY Interrupt Disable
bits : 1 - 1 (1 bit)

OVRE : Overrun Error Interrupt Enable
bits : 5 - 5 (1 bit)

FRAME : Framing Error Interrupt Disable
bits : 6 - 6 (1 bit)

PARE : Parity Error Interrupt Disable
bits : 7 - 7 (1 bit)

TIMEOUT : Timeout Interrupt Disable
bits : 8 - 8 (1 bit)

TXEMPTY : TXEMPTY Interrupt Disable
bits : 9 - 9 (1 bit)

RIIC : Ring Indicator Input Change Disable
bits : 16 - 16 (1 bit)

DSRIC : Data Set Ready Input Change Disable
bits : 17 - 17 (1 bit)

DCDIC : Data Carrier Detect Input Change Interrupt Disable
bits : 18 - 18 (1 bit)


US_IDR_SPI_MODE

Interrupt Disable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : US_IDR_USART_MODE
reset_Mask : 0x0

US_IDR_SPI_MODE US_IDR_SPI_MODE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY OVRE TXEMPTY UNRE RIIC DSRIC DCDIC NSSE

RXRDY : RXRDY Interrupt Disable
bits : 0 - 0 (1 bit)

TXRDY : TXRDY Interrupt Disable
bits : 1 - 1 (1 bit)

OVRE : Overrun Error Interrupt Enable
bits : 5 - 5 (1 bit)

TXEMPTY : TXEMPTY Interrupt Disable
bits : 9 - 9 (1 bit)

UNRE : SPI Underrun Error Interrupt Disable
bits : 10 - 10 (1 bit)

RIIC : Ring Indicator Input Change Disable
bits : 16 - 16 (1 bit)

DSRIC : Data Set Ready Input Change Disable
bits : 17 - 17 (1 bit)

DCDIC : Data Carrier Detect Input Change Interrupt Disable
bits : 18 - 18 (1 bit)

NSSE : NSS Line (Driving CTS Pin) Rising or Falling Edge Event
bits : 19 - 19 (1 bit)


US_IDR_LIN_MODE

Interrupt Disable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : US_IDR_USART_MODE
reset_Mask : 0x0

US_IDR_LIN_MODE US_IDR_LIN_MODE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY OVRE FRAME PARE TIMEOUT TXEMPTY LINBK LINID LINTC RIIC DSRIC DCDIC LINBE LINISFE LINIPE LINCE LINSNRE LINSTE LINHTE

RXRDY : RXRDY Interrupt Disable
bits : 0 - 0 (1 bit)

TXRDY : TXRDY Interrupt Disable
bits : 1 - 1 (1 bit)

OVRE : Overrun Error Interrupt Enable
bits : 5 - 5 (1 bit)

FRAME : Framing Error Interrupt Disable
bits : 6 - 6 (1 bit)

PARE : Parity Error Interrupt Disable
bits : 7 - 7 (1 bit)

TIMEOUT : Timeout Interrupt Disable
bits : 8 - 8 (1 bit)

TXEMPTY : TXEMPTY Interrupt Disable
bits : 9 - 9 (1 bit)

LINBK : LIN Break Sent or LIN Break Received Interrupt Disable
bits : 13 - 13 (1 bit)

LINID : LIN Identifier Sent or LIN Identifier Received Interrupt Disable
bits : 14 - 14 (1 bit)

LINTC : LIN Transfer Completed Interrupt Disable
bits : 15 - 15 (1 bit)

RIIC : Ring Indicator Input Change Disable
bits : 16 - 16 (1 bit)

DSRIC : Data Set Ready Input Change Disable
bits : 17 - 17 (1 bit)

DCDIC : Data Carrier Detect Input Change Interrupt Disable
bits : 18 - 18 (1 bit)

LINBE : LIN Bus Error Interrupt Disable
bits : 25 - 25 (1 bit)

LINISFE : LIN Inconsistent Synch Field Error Interrupt Disable
bits : 26 - 26 (1 bit)

LINIPE : LIN Identifier Parity Interrupt Disable
bits : 27 - 27 (1 bit)

LINCE : LIN Checksum Error Interrupt Disable
bits : 28 - 28 (1 bit)

LINSNRE : LIN Slave Not Responding Error Interrupt Disable
bits : 29 - 29 (1 bit)

LINSTE : LIN Synch Tolerance Error Interrupt Disable
bits : 30 - 30 (1 bit)

LINHTE : LIN Header Timeout Error Interrupt Disable
bits : 31 - 31 (1 bit)


US_IDR_LON_MODE

Interrupt Disable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : US_IDR_USART_MODE
reset_Mask : 0x0

US_IDR_LON_MODE US_IDR_LON_MODE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY OVRE LSFE LCRCE TXEMPTY UNRE RIIC DSRIC DCDIC LTXD LCOL LFET LRXD LBLOVFE

RXRDY : RXRDY Interrupt Disable
bits : 0 - 0 (1 bit)

TXRDY : TXRDY Interrupt Disable
bits : 1 - 1 (1 bit)

OVRE : Overrun Error Interrupt Enable
bits : 5 - 5 (1 bit)

LSFE : LON Short Frame Error Interrupt Disable
bits : 6 - 6 (1 bit)

LCRCE : LON CRC Error Interrupt Disable
bits : 7 - 7 (1 bit)

TXEMPTY : TXEMPTY Interrupt Disable
bits : 9 - 9 (1 bit)

UNRE : SPI Underrun Error Interrupt Disable
bits : 10 - 10 (1 bit)

RIIC : Ring Indicator Input Change Disable
bits : 16 - 16 (1 bit)

DSRIC : Data Set Ready Input Change Disable
bits : 17 - 17 (1 bit)

DCDIC : Data Carrier Detect Input Change Interrupt Disable
bits : 18 - 18 (1 bit)

LTXD : LON Transmission Done Interrupt Disable
bits : 24 - 24 (1 bit)

LCOL : LON Collision Interrupt Disable
bits : 25 - 25 (1 bit)

LFET : LON Frame Early Termination Interrupt Disable
bits : 26 - 26 (1 bit)

LRXD : LON Reception Done Interrupt Disable
bits : 27 - 27 (1 bit)

LBLOVFE : LON Backlog Overflow Error Interrupt Disable
bits : 28 - 28 (1 bit)


US_IDR_LON_SPI_MODE

Interrupt Disable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : US_IDR_USART_MODE
reset_Mask : 0x0

US_IDR_LON_SPI_MODE US_IDR_LON_SPI_MODE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY OVRE TXEMPTY UNRE RIIC DSRIC DCDIC

RXRDY : RXRDY Interrupt Disable
bits : 0 - 0 (1 bit)

TXRDY : TXRDY Interrupt Disable
bits : 1 - 1 (1 bit)

OVRE : Overrun Error Interrupt Enable
bits : 5 - 5 (1 bit)

TXEMPTY : TXEMPTY Interrupt Disable
bits : 9 - 9 (1 bit)

UNRE : SPI Underrun Error Interrupt Disable
bits : 10 - 10 (1 bit)

RIIC : Ring Indicator Input Change Disable
bits : 16 - 16 (1 bit)

DSRIC : Data Set Ready Input Change Disable
bits : 17 - 17 (1 bit)

DCDIC : Data Carrier Detect Input Change Interrupt Disable
bits : 18 - 18 (1 bit)


US_WPMR

Write Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

US_WPMR US_WPMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPEN WPKEY

WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)

WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)

Enumeration: WPKEYSelect

0x555341 : PASSWD

Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.

End of enumeration elements list.


US_WPSR

Write Protection Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

US_WPSR US_WPSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPVS WPVSRC

WPVS : Write Protection Violation Status
bits : 0 - 0 (1 bit)

WPVSRC : Write Protection Violation Source
bits : 8 - 23 (16 bit)



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