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ISI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xEC byte (0x0)
mem_usage : registers
protection :

address_offset : 0x0 Bytes (0x0)
size : 0xEC byte (0x0)
mem_usage : registers
protection :

address_offset : 0x0 Bytes (0x0)
size : 0xEC byte (0x0)
mem_usage : registers
protection :

Registers

CFG1

Y2R_SET0

Y2R_SET1

R2Y_SET0

R2Y_SET1

R2Y_SET2

CR

SR

IER

IDR

IMR

DMA_CHER

DMA_CHDR

CFG2

DMA_CHSR

DMA_P_ADDR

DMA_P_CTRL

DMA_P_DSCR

DMA_C_ADDR

DMA_C_CTRL

DMA_C_DSCR

PSIZE

PDECF

WPMR

WPSR

VERSION


CFG1

ISI Configuration 1 Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG1 CFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSYNC_POL VSYNC_POL PIXCLK_POL GRAYLE EMB_SYNC CRC_SYNC FRATE DISCR FULL THMASK SLD SFD

HSYNC_POL : Horizontal Synchronization Polarity
bits : 2 - 2 (1 bit)

VSYNC_POL : Vertical Synchronization Polarity
bits : 3 - 3 (1 bit)

PIXCLK_POL : Pixel Clock Polarity
bits : 4 - 4 (1 bit)

GRAYLE : Grayscale Little Endian
bits : 5 - 5 (1 bit)

EMB_SYNC : Embedded Synchronization
bits : 6 - 6 (1 bit)

CRC_SYNC : Embedded Synchronization Correction
bits : 7 - 7 (1 bit)

FRATE : Frame Rate [0..7]
bits : 8 - 10 (3 bit)

DISCR : Disable Codec Request
bits : 11 - 11 (1 bit)

FULL : Full Mode is Allowed
bits : 12 - 12 (1 bit)

THMASK : Threshold Mask
bits : 13 - 14 (2 bit)

Enumeration: THMASKSelect

0x0 : BEATS_4

Only 4 beats AHB burst allowed

0x1 : BEATS_8

Only 4 and 8 beats AHB burst allowed

0x2 : BEATS_16

4, 8 and 16 beats AHB burst allowed

End of enumeration elements list.

SLD : Start of Line Delay
bits : 16 - 23 (8 bit)

SFD : Start of Frame Delay
bits : 24 - 31 (8 bit)


Y2R_SET0

ISI Color Space Conversion YCrCb To RGB Set 0 Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Y2R_SET0 Y2R_SET0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C0 C1 C2 C3

C0 : Color Space Conversion Matrix Coefficient C0
bits : 0 - 7 (8 bit)

C1 : Color Space Conversion Matrix Coefficient C1
bits : 8 - 15 (8 bit)

C2 : Color Space Conversion Matrix Coefficient C2
bits : 16 - 23 (8 bit)

C3 : Color Space Conversion Matrix Coefficient C3
bits : 24 - 31 (8 bit)


Y2R_SET1

ISI Color Space Conversion YCrCb To RGB Set 1 Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Y2R_SET1 Y2R_SET1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C4 Yoff Croff Cboff

C4 : Color Space Conversion Matrix Coefficient C4
bits : 0 - 8 (9 bit)

Yoff : Color Space Conversion Luminance Default Offset
bits : 12 - 12 (1 bit)

Croff : Color Space Conversion Red Chrominance Default Offset
bits : 13 - 13 (1 bit)

Cboff : Color Space Conversion Blue Chrominance Default Offset
bits : 14 - 14 (1 bit)


R2Y_SET0

ISI Color Space Conversion RGB To YCrCb Set 0 Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R2Y_SET0 R2Y_SET0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C0 C1 C2 Roff

C0 : Color Space Conversion Matrix Coefficient C0
bits : 0 - 6 (7 bit)

C1 : Color Space Conversion Matrix Coefficient C1
bits : 8 - 14 (7 bit)

C2 : Color Space Conversion Matrix Coefficient C2
bits : 16 - 22 (7 bit)

Roff : Color Space Conversion Red Component Offset
bits : 24 - 24 (1 bit)


R2Y_SET1

ISI Color Space Conversion RGB To YCrCb Set 1 Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R2Y_SET1 R2Y_SET1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C3 C4 C5 Goff

C3 : Color Space Conversion Matrix Coefficient C3
bits : 0 - 6 (7 bit)

C4 : Color Space Conversion Matrix Coefficient C4
bits : 8 - 14 (7 bit)

C5 : Color Space Conversion Matrix Coefficient C5
bits : 16 - 22 (7 bit)

Goff : Color Space Conversion Green Component Offset
bits : 24 - 24 (1 bit)


R2Y_SET2

ISI Color Space Conversion RGB To YCrCb Set 2 Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R2Y_SET2 R2Y_SET2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C6 C7 C8 Boff

C6 : Color Space Conversion Matrix Coefficient C6
bits : 0 - 6 (7 bit)

C7 : Color Space Conversion Matrix Coefficient C7
bits : 8 - 14 (7 bit)

C8 : Color Space Conversion Matrix Coefficient C8
bits : 16 - 22 (7 bit)

Boff : Color Space Conversion Blue Component Offset
bits : 24 - 24 (1 bit)


CR

ISI Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CR CR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISI_EN ISI_DIS ISI_SRST ISI_CDC

ISI_EN : ISI Module Enable Request
bits : 0 - 0 (1 bit)

ISI_DIS : ISI Module Disable Request
bits : 1 - 1 (1 bit)

ISI_SRST : ISI Software Reset Request
bits : 2 - 2 (1 bit)

ISI_CDC : ISI Codec Request
bits : 8 - 8 (1 bit)


SR

ISI Status Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE DIS_DONE SRST CDC_PND VSYNC PXFR_DONE CXFR_DONE SIP P_OVR C_OVR CRC_ERR FR_OVR

ENABLE : Module Enable
bits : 0 - 0 (1 bit)

DIS_DONE : Module Disable Request has Terminated (cleared on read)
bits : 1 - 1 (1 bit)

SRST : Module Software Reset Request has Terminated (cleared on read)
bits : 2 - 2 (1 bit)

CDC_PND : Pending Codec Request
bits : 8 - 8 (1 bit)

VSYNC : Vertical Synchronization (cleared on read)
bits : 10 - 10 (1 bit)

PXFR_DONE : Preview DMA Transfer has Terminated (cleared on read)
bits : 16 - 16 (1 bit)

CXFR_DONE : Codec DMA Transfer has Terminated (cleared on read)
bits : 17 - 17 (1 bit)

SIP : Synchronization in Progress
bits : 19 - 19 (1 bit)

P_OVR : Preview Datapath Overflow (cleared on read)
bits : 24 - 24 (1 bit)

C_OVR : Codec Datapath Overflow (cleared on read)
bits : 25 - 25 (1 bit)

CRC_ERR : CRC Synchronization Error (cleared on read)
bits : 26 - 26 (1 bit)

FR_OVR : Frame Rate Overrun (cleared on read)
bits : 27 - 27 (1 bit)


IER

ISI Interrupt Enable Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIS_DONE SRST VSYNC PXFR_DONE CXFR_DONE P_OVR C_OVR CRC_ERR FR_OVR

DIS_DONE : Disable Done Interrupt Enable
bits : 1 - 1 (1 bit)

SRST : Software Reset Interrupt Enable
bits : 2 - 2 (1 bit)

VSYNC : Vertical Synchronization Interrupt Enable
bits : 10 - 10 (1 bit)

PXFR_DONE : Preview DMA Transfer Done Interrupt Enable
bits : 16 - 16 (1 bit)

CXFR_DONE : Codec DMA Transfer Done Interrupt Enable
bits : 17 - 17 (1 bit)

P_OVR : Preview Datapath Overflow Interrupt Enable
bits : 24 - 24 (1 bit)

C_OVR : Codec Datapath Overflow Interrupt Enable
bits : 25 - 25 (1 bit)

CRC_ERR : Embedded Synchronization CRC Error Interrupt Enable
bits : 26 - 26 (1 bit)

FR_OVR : Frame Rate Overflow Interrupt Enable
bits : 27 - 27 (1 bit)


IDR

ISI Interrupt Disable Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIS_DONE SRST VSYNC PXFR_DONE CXFR_DONE P_OVR C_OVR CRC_ERR FR_OVR

DIS_DONE : Disable Done Interrupt Disable
bits : 1 - 1 (1 bit)

SRST : Software Reset Interrupt Disable
bits : 2 - 2 (1 bit)

VSYNC : Vertical Synchronization Interrupt Disable
bits : 10 - 10 (1 bit)

PXFR_DONE : Preview DMA Transfer Done Interrupt Disable
bits : 16 - 16 (1 bit)

CXFR_DONE : Codec DMA Transfer Done Interrupt Disable
bits : 17 - 17 (1 bit)

P_OVR : Preview Datapath Overflow Interrupt Disable
bits : 24 - 24 (1 bit)

C_OVR : Codec Datapath Overflow Interrupt Disable
bits : 25 - 25 (1 bit)

CRC_ERR : Embedded Synchronization CRC Error Interrupt Disable
bits : 26 - 26 (1 bit)

FR_OVR : Frame Rate Overflow Interrupt Disable
bits : 27 - 27 (1 bit)


IMR

ISI Interrupt Mask Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIS_DONE SRST VSYNC PXFR_DONE CXFR_DONE P_OVR C_OVR CRC_ERR FR_OVR

DIS_DONE : Module Disable Operation Completed
bits : 1 - 1 (1 bit)

SRST : Software Reset Completed
bits : 2 - 2 (1 bit)

VSYNC : Vertical Synchronization
bits : 10 - 10 (1 bit)

PXFR_DONE : Preview DMA Transfer Completed
bits : 16 - 16 (1 bit)

CXFR_DONE : Codec DMA Transfer Completed
bits : 17 - 17 (1 bit)

P_OVR : Preview FIFO Overflow
bits : 24 - 24 (1 bit)

C_OVR : Codec FIFO Overflow
bits : 25 - 25 (1 bit)

CRC_ERR : CRC Synchronization Error
bits : 26 - 26 (1 bit)

FR_OVR : Frame Rate Overrun
bits : 27 - 27 (1 bit)


DMA_CHER

DMA Channel Enable Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DMA_CHER DMA_CHER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_CH_EN C_CH_EN

P_CH_EN : Preview Channel Enable
bits : 0 - 0 (1 bit)

C_CH_EN : Codec Channel Enable
bits : 1 - 1 (1 bit)


DMA_CHDR

DMA Channel Disable Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DMA_CHDR DMA_CHDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_CH_DIS C_CH_DIS

P_CH_DIS : Preview Channel Disable Request
bits : 0 - 0 (1 bit)

C_CH_DIS : Codec Channel Disable Request
bits : 1 - 1 (1 bit)


CFG2

ISI Configuration 2 Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG2 CFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IM_VSIZE GS_MODE RGB_MODE GRAYSCALE RGB_SWAP COL_SPACE IM_HSIZE YCC_SWAP RGB_CFG

IM_VSIZE : Vertical Size of the Image Sensor [0..2047]
bits : 0 - 10 (11 bit)

GS_MODE : Grayscale Pixel Format Mode
bits : 11 - 11 (1 bit)

RGB_MODE : RGB Input Mode
bits : 12 - 12 (1 bit)

GRAYSCALE : Grayscale Mode Format Enable
bits : 13 - 13 (1 bit)

RGB_SWAP : RGB Format Swap Mode
bits : 14 - 14 (1 bit)

COL_SPACE : Color Space for the Image Data
bits : 15 - 15 (1 bit)

IM_HSIZE : Horizontal Size of the Image Sensor [0..2047]
bits : 16 - 26 (11 bit)

YCC_SWAP : YCrCb Format Swap Mode
bits : 28 - 29 (2 bit)

Enumeration: YCC_SWAPSelect

0x0 : DEFAULT

Byte 0 Cb(i)Byte 1 Y(i)Byte 2 Cr(i)Byte 3 Y(i+1)

0x1 : MODE1

Byte 0 Cr(i)Byte 1 Y(i)Byte 2 Cb(i)Byte 3 Y(i+1)

0x2 : MODE2

Byte 0 Y(i)Byte 1 Cb(i)Byte 2 Y(i+1)Byte 3 Cr(i)

0x3 : MODE3

Byte 0 Y(i)Byte 1 Cr(i)Byte 2 Y(i+1)Byte 3 Cb(i)

End of enumeration elements list.

RGB_CFG : RGB Pixel Mapping Configuration
bits : 30 - 31 (2 bit)

Enumeration: RGB_CFGSelect

0x0 : DEFAULT

Byte 0 R/G(MSB)Byte 1 G(LSB)/BByte 2 R/G(MSB)Byte 3 G(LSB)/B

0x1 : MODE1

Byte 0 B/G(MSB)Byte 1 G(LSB)/RByte 2 B/G(MSB)Byte 3 G(LSB)/R

0x2 : MODE2

Byte 0 G(LSB)/RByte 1 B/G(MSB)Byte 2 G(LSB)/RByte 3 B/G(MSB)

0x3 : MODE3

Byte 0 G(LSB)/BByte 1 R/G(MSB)Byte 2 G(LSB)/BByte 3 R/G(MSB)

End of enumeration elements list.


DMA_CHSR

DMA Channel Status Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMA_CHSR DMA_CHSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_CH_S C_CH_S

P_CH_S : Preview DMA Channel Status
bits : 0 - 0 (1 bit)

C_CH_S : Code DMA Channel Status
bits : 1 - 1 (1 bit)


DMA_P_ADDR

DMA Preview Base Address Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_P_ADDR DMA_P_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_ADDR

P_ADDR : Preview Image Base Address
bits : 2 - 31 (30 bit)


DMA_P_CTRL

DMA Preview Control Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_P_CTRL DMA_P_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_FETCH P_WB P_IEN P_DONE

P_FETCH : Descriptor Fetch Control Bit
bits : 0 - 0 (1 bit)

P_WB : Descriptor Writeback Control Bit
bits : 1 - 1 (1 bit)

P_IEN : Transfer Done Flag Control
bits : 2 - 2 (1 bit)

P_DONE : Preview Transfer Done
bits : 3 - 3 (1 bit)


DMA_P_DSCR

DMA Preview Descriptor Address Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_P_DSCR DMA_P_DSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_DSCR

P_DSCR : Preview Descriptor Base Address
bits : 2 - 31 (30 bit)


DMA_C_ADDR

DMA Codec Base Address Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_C_ADDR DMA_C_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C_ADDR

C_ADDR : Codec Image Base Address
bits : 2 - 31 (30 bit)


DMA_C_CTRL

DMA Codec Control Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_C_CTRL DMA_C_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C_FETCH C_WB C_IEN C_DONE

C_FETCH : Descriptor Fetch Control Bit
bits : 0 - 0 (1 bit)

C_WB : Descriptor Writeback Control Bit
bits : 1 - 1 (1 bit)

C_IEN : Transfer Done Flag Control
bits : 2 - 2 (1 bit)

C_DONE : Codec Transfer Done
bits : 3 - 3 (1 bit)


DMA_C_DSCR

DMA Codec Descriptor Address Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_C_DSCR DMA_C_DSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C_DSCR

C_DSCR : Codec Descriptor Base Address
bits : 2 - 31 (30 bit)


PSIZE

ISI Preview Size Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSIZE PSIZE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREV_VSIZE PREV_HSIZE

PREV_VSIZE : Vertical Size for the Preview Path
bits : 0 - 9 (10 bit)

PREV_HSIZE : Horizontal Size for the Preview Path
bits : 16 - 25 (10 bit)


PDECF

ISI Preview Decimation Factor Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDECF PDECF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEC_FACTOR

DEC_FACTOR : Decimation Factor
bits : 0 - 7 (8 bit)


WPMR

Write Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WPMR WPMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPEN WPKEY

WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)

WPKEY : Write Protection Key Password
bits : 8 - 31 (24 bit)

Enumeration: WPKEYSelect

0x495349 : PASSWD

Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.

End of enumeration elements list.


WPSR

Write Protection Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WPSR WPSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPVS WPVSRC

WPVS : Write Protection Violation Status
bits : 0 - 0 (1 bit)

WPVSRC : Write Protection Violation Source
bits : 8 - 23 (16 bit)


VERSION

Version Register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

VERSION VERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION MFN

VERSION : Version of the Hardware Module
bits : 0 - 11 (12 bit)
access : read-only

MFN : Metal Fix Number
bits : 16 - 18 (3 bit)
access : read-only



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