\n
address_offset : 0x0 Bytes (0x0)
size : 0xEC byte (0x0)
mem_usage : registers
protection :
address_offset : 0x0 Bytes (0x0)
size : 0xEC byte (0x0)
mem_usage : registers
protection :
address_offset : 0x0 Bytes (0x0)
size : 0xEC byte (0x0)
mem_usage : registers
protection :
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SPIEN : SPI Enable
bits : 0 - 0 (1 bit)
SPIDIS : SPI Disable
bits : 1 - 1 (1 bit)
SWRST : SPI Software Reset
bits : 7 - 7 (1 bit)
REQCLR : Request to Clear the Comparison Trigger
bits : 12 - 12 (1 bit)
TXFCLR : Transmit FIFO Clear
bits : 16 - 16 (1 bit)
RXFCLR : Receive FIFO Clear
bits : 17 - 17 (1 bit)
LASTXFER : Last Transfer
bits : 24 - 24 (1 bit)
FIFOEN : FIFO Enable
bits : 30 - 30 (1 bit)
FIFODIS : FIFO Disable
bits : 31 - 31 (1 bit)
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
SPIEN : SPI Enable
bits : 0 - 0 (1 bit)
access : write-only
SPIDIS : SPI Disable
bits : 1 - 1 (1 bit)
access : write-only
SWRST : SPI Software Reset
bits : 7 - 7 (1 bit)
access : write-only
LASTXFER : Last Transfer
bits : 24 - 24 (1 bit)
access : write-only
Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDRF : Receive Data Register Full (cleared by reading SPI_RDR)
bits : 0 - 0 (1 bit)
TDRE : Transmit Data Register Empty (cleared by writing SPI_TDR)
bits : 1 - 1 (1 bit)
MODF : Mode Fault Error (cleared on read)
bits : 2 - 2 (1 bit)
OVRES : Overrun Error Status (cleared on read)
bits : 3 - 3 (1 bit)
NSSR : NSS Rising (cleared on read)
bits : 8 - 8 (1 bit)
TXEMPTY : Transmission Registers Empty (cleared by writing SPI_TDR)
bits : 9 - 9 (1 bit)
UNDES : Underrun Error Status (Slave mode only) (cleared on read)
bits : 10 - 10 (1 bit)
SPIENS : SPI Enable Status
bits : 16 - 16 (1 bit)
Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
RDRF : Receive Data Register Full (cleared by reading SPI_RDR)
bits : 0 - 0 (1 bit)
access : read-only
TDRE : Transmit Data Register Empty (cleared by writing SPI_TDR)
bits : 1 - 1 (1 bit)
access : read-only
MODF : Mode Fault Error (cleared on read)
bits : 2 - 2 (1 bit)
access : read-only
OVRES : Overrun Error Status (cleared on read)
bits : 3 - 3 (1 bit)
access : read-only
NSSR : NSS Rising (cleared on read)
bits : 8 - 8 (1 bit)
access : read-only
TXEMPTY : Transmission Registers Empty (cleared by writing SPI_TDR)
bits : 9 - 9 (1 bit)
access : read-only
UNDES : Underrun Error Status (Slave mode only) (cleared on read)
bits : 10 - 10 (1 bit)
access : read-only
SPIENS : SPI Enable Status
bits : 16 - 16 (1 bit)
access : read-only
Interrupt Enable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RDRF : Receive Data Register Full Interrupt Enable
bits : 0 - 0 (1 bit)
TDRE : SPI Transmit Data Register Empty Interrupt Enable
bits : 1 - 1 (1 bit)
MODF : Mode Fault Error Interrupt Enable
bits : 2 - 2 (1 bit)
OVRES : Overrun Error Interrupt Enable
bits : 3 - 3 (1 bit)
NSSR : NSS Rising Interrupt Enable
bits : 8 - 8 (1 bit)
TXEMPTY : Transmission Registers Empty Enable
bits : 9 - 9 (1 bit)
UNDES : Underrun Error Interrupt Enable
bits : 10 - 10 (1 bit)
Interrupt Enable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
RDRF : Receive Data Register Full Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
TDRE : SPI Transmit Data Register Empty Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
MODF : Mode Fault Error Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
OVRES : Overrun Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
NSSR : NSS Rising Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
TXEMPTY : Transmission Registers Empty Enable
bits : 9 - 9 (1 bit)
access : write-only
UNDES : Underrun Error Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
Interrupt Disable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RDRF : Receive Data Register Full Interrupt Disable
bits : 0 - 0 (1 bit)
TDRE : SPI Transmit Data Register Empty Interrupt Disable
bits : 1 - 1 (1 bit)
MODF : Mode Fault Error Interrupt Disable
bits : 2 - 2 (1 bit)
OVRES : Overrun Error Interrupt Disable
bits : 3 - 3 (1 bit)
NSSR : NSS Rising Interrupt Disable
bits : 8 - 8 (1 bit)
TXEMPTY : Transmission Registers Empty Disable
bits : 9 - 9 (1 bit)
UNDES : Underrun Error Interrupt Disable
bits : 10 - 10 (1 bit)
Interrupt Disable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
RDRF : Receive Data Register Full Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
TDRE : SPI Transmit Data Register Empty Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
MODF : Mode Fault Error Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
OVRES : Overrun Error Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only
NSSR : NSS Rising Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
TXEMPTY : Transmission Registers Empty Disable
bits : 9 - 9 (1 bit)
access : write-only
UNDES : Underrun Error Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
Interrupt Mask Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDRF : Receive Data Register Full Interrupt Mask
bits : 0 - 0 (1 bit)
TDRE : SPI Transmit Data Register Empty Interrupt Mask
bits : 1 - 1 (1 bit)
MODF : Mode Fault Error Interrupt Mask
bits : 2 - 2 (1 bit)
OVRES : Overrun Error Interrupt Mask
bits : 3 - 3 (1 bit)
NSSR : NSS Rising Interrupt Mask
bits : 8 - 8 (1 bit)
TXEMPTY : Transmission Registers Empty Mask
bits : 9 - 9 (1 bit)
UNDES : Underrun Error Interrupt Mask
bits : 10 - 10 (1 bit)
Interrupt Mask Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
RDRF : Receive Data Register Full Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only
TDRE : SPI Transmit Data Register Empty Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only
MODF : Mode Fault Error Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only
OVRES : Overrun Error Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-only
NSSR : NSS Rising Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-only
TXEMPTY : Transmission Registers Empty Mask
bits : 9 - 9 (1 bit)
access : read-only
UNDES : Underrun Error Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-only
Chip Select Register (CS_number = 0) 0
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPOL : Clock Polarity
bits : 0 - 0 (1 bit)
NCPHA : Clock Phase
bits : 1 - 1 (1 bit)
CSNAAT : Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
bits : 2 - 2 (1 bit)
CSAAT : Chip Select Active After Transfer
bits : 3 - 3 (1 bit)
BITS : Bits Per Transfer
bits : 4 - 7 (4 bit)
Enumeration: BITSSelect
0x0 : _8_BIT
8 bits for transfer
0x1 : _9_BIT
9 bits for transfer
0x2 : _10_BIT
10 bits for transfer
0x3 : _11_BIT
11 bits for transfer
0x4 : _12_BIT
12 bits for transfer
0x5 : _13_BIT
13 bits for transfer
0x6 : _14_BIT
14 bits for transfer
0x7 : _15_BIT
15 bits for transfer
0x8 : _16_BIT
16 bits for transfer
End of enumeration elements list.
SCBR : Serial Clock Bit Rate
bits : 8 - 15 (8 bit)
DLYBS : Delay Before SPCK
bits : 16 - 23 (8 bit)
DLYBCT : Delay Between Consecutive Transfers
bits : 24 - 31 (8 bit)
Chip Select Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CPOL : Clock Polarity
bits : 0 - 0 (1 bit)
access : read-write
NCPHA : Clock Phase
bits : 1 - 1 (1 bit)
access : read-write
CSNAAT : Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
bits : 2 - 2 (1 bit)
access : read-write
CSAAT : Chip Select Active After Transfer
bits : 3 - 3 (1 bit)
access : read-write
BITS : Bits Per Transfer
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0x0 : 8_BIT
8 bits for transfer
0x1 : 9_BIT
9 bits for transfer
0x2 : 10_BIT
10 bits for transfer
0x3 : 11_BIT
11 bits for transfer
0x4 : 12_BIT
12 bits for transfer
0x5 : 13_BIT
13 bits for transfer
0x6 : 14_BIT
14 bits for transfer
0x7 : 15_BIT
15 bits for transfer
0x8 : 16_BIT
16 bits for transfer
End of enumeration elements list.
SCBR : Serial Clock Bit Rate
bits : 8 - 15 (8 bit)
access : read-write
DLYBS : Delay Before SPCK
bits : 16 - 23 (8 bit)
access : read-write
DLYBCT : Delay Between Consecutive Transfers
bits : 24 - 31 (8 bit)
access : read-write
Chip Select Register (CS_number = 0) 0
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPOL : Clock Polarity
bits : 0 - 0 (1 bit)
NCPHA : Clock Phase
bits : 1 - 1 (1 bit)
CSNAAT : Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
bits : 2 - 2 (1 bit)
CSAAT : Chip Select Active After Transfer
bits : 3 - 3 (1 bit)
BITS : Bits Per Transfer
bits : 4 - 7 (4 bit)
Enumeration: BITSSelect
0x0 : _8_BIT
8 bits for transfer
0x1 : _9_BIT
9 bits for transfer
0x2 : _10_BIT
10 bits for transfer
0x3 : _11_BIT
11 bits for transfer
0x4 : _12_BIT
12 bits for transfer
0x5 : _13_BIT
13 bits for transfer
0x6 : _14_BIT
14 bits for transfer
0x7 : _15_BIT
15 bits for transfer
0x8 : _16_BIT
16 bits for transfer
End of enumeration elements list.
SCBR : Serial Clock Bit Rate
bits : 8 - 15 (8 bit)
DLYBS : Delay Before SPCK
bits : 16 - 23 (8 bit)
DLYBCT : Delay Between Consecutive Transfers
bits : 24 - 31 (8 bit)
Chip Select Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CPOL : Clock Polarity
bits : 0 - 0 (1 bit)
access : read-write
NCPHA : Clock Phase
bits : 1 - 1 (1 bit)
access : read-write
CSNAAT : Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
bits : 2 - 2 (1 bit)
access : read-write
CSAAT : Chip Select Active After Transfer
bits : 3 - 3 (1 bit)
access : read-write
BITS : Bits Per Transfer
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0x0 : 8_BIT
8 bits for transfer
0x1 : 9_BIT
9 bits for transfer
0x2 : 10_BIT
10 bits for transfer
0x3 : 11_BIT
11 bits for transfer
0x4 : 12_BIT
12 bits for transfer
0x5 : 13_BIT
13 bits for transfer
0x6 : 14_BIT
14 bits for transfer
0x7 : 15_BIT
15 bits for transfer
0x8 : 16_BIT
16 bits for transfer
End of enumeration elements list.
SCBR : Serial Clock Bit Rate
bits : 8 - 15 (8 bit)
access : read-write
DLYBS : Delay Before SPCK
bits : 16 - 23 (8 bit)
access : read-write
DLYBCT : Delay Between Consecutive Transfers
bits : 24 - 31 (8 bit)
access : read-write
Chip Select Register (CS_number = 0) 0
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPOL : Clock Polarity
bits : 0 - 0 (1 bit)
NCPHA : Clock Phase
bits : 1 - 1 (1 bit)
CSNAAT : Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
bits : 2 - 2 (1 bit)
CSAAT : Chip Select Active After Transfer
bits : 3 - 3 (1 bit)
BITS : Bits Per Transfer
bits : 4 - 7 (4 bit)
Enumeration: BITSSelect
0x0 : _8_BIT
8 bits for transfer
0x1 : _9_BIT
9 bits for transfer
0x2 : _10_BIT
10 bits for transfer
0x3 : _11_BIT
11 bits for transfer
0x4 : _12_BIT
12 bits for transfer
0x5 : _13_BIT
13 bits for transfer
0x6 : _14_BIT
14 bits for transfer
0x7 : _15_BIT
15 bits for transfer
0x8 : _16_BIT
16 bits for transfer
End of enumeration elements list.
SCBR : Serial Clock Bit Rate
bits : 8 - 15 (8 bit)
DLYBS : Delay Before SPCK
bits : 16 - 23 (8 bit)
DLYBCT : Delay Between Consecutive Transfers
bits : 24 - 31 (8 bit)
Chip Select Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CPOL : Clock Polarity
bits : 0 - 0 (1 bit)
access : read-write
NCPHA : Clock Phase
bits : 1 - 1 (1 bit)
access : read-write
CSNAAT : Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
bits : 2 - 2 (1 bit)
access : read-write
CSAAT : Chip Select Active After Transfer
bits : 3 - 3 (1 bit)
access : read-write
BITS : Bits Per Transfer
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0x0 : 8_BIT
8 bits for transfer
0x1 : 9_BIT
9 bits for transfer
0x2 : 10_BIT
10 bits for transfer
0x3 : 11_BIT
11 bits for transfer
0x4 : 12_BIT
12 bits for transfer
0x5 : 13_BIT
13 bits for transfer
0x6 : 14_BIT
14 bits for transfer
0x7 : 15_BIT
15 bits for transfer
0x8 : 16_BIT
16 bits for transfer
End of enumeration elements list.
SCBR : Serial Clock Bit Rate
bits : 8 - 15 (8 bit)
access : read-write
DLYBS : Delay Before SPCK
bits : 16 - 23 (8 bit)
access : read-write
DLYBCT : Delay Between Consecutive Transfers
bits : 24 - 31 (8 bit)
access : read-write
Chip Select Register (CS_number = 0) 0
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPOL : Clock Polarity
bits : 0 - 0 (1 bit)
NCPHA : Clock Phase
bits : 1 - 1 (1 bit)
CSNAAT : Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
bits : 2 - 2 (1 bit)
CSAAT : Chip Select Active After Transfer
bits : 3 - 3 (1 bit)
BITS : Bits Per Transfer
bits : 4 - 7 (4 bit)
Enumeration: BITSSelect
0x0 : _8_BIT
8 bits for transfer
0x1 : _9_BIT
9 bits for transfer
0x2 : _10_BIT
10 bits for transfer
0x3 : _11_BIT
11 bits for transfer
0x4 : _12_BIT
12 bits for transfer
0x5 : _13_BIT
13 bits for transfer
0x6 : _14_BIT
14 bits for transfer
0x7 : _15_BIT
15 bits for transfer
0x8 : _16_BIT
16 bits for transfer
End of enumeration elements list.
SCBR : Serial Clock Bit Rate
bits : 8 - 15 (8 bit)
DLYBS : Delay Before SPCK
bits : 16 - 23 (8 bit)
DLYBCT : Delay Between Consecutive Transfers
bits : 24 - 31 (8 bit)
Chip Select Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CPOL : Clock Polarity
bits : 0 - 0 (1 bit)
access : read-write
NCPHA : Clock Phase
bits : 1 - 1 (1 bit)
access : read-write
CSNAAT : Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
bits : 2 - 2 (1 bit)
access : read-write
CSAAT : Chip Select Active After Transfer
bits : 3 - 3 (1 bit)
access : read-write
BITS : Bits Per Transfer
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0x0 : 8_BIT
8 bits for transfer
0x1 : 9_BIT
9 bits for transfer
0x2 : 10_BIT
10 bits for transfer
0x3 : 11_BIT
11 bits for transfer
0x4 : 12_BIT
12 bits for transfer
0x5 : 13_BIT
13 bits for transfer
0x6 : 14_BIT
14 bits for transfer
0x7 : 15_BIT
15 bits for transfer
0x8 : 16_BIT
16 bits for transfer
End of enumeration elements list.
SCBR : Serial Clock Bit Rate
bits : 8 - 15 (8 bit)
access : read-write
DLYBS : Delay Before SPCK
bits : 16 - 23 (8 bit)
access : read-write
DLYBCT : Delay Between Consecutive Transfers
bits : 24 - 31 (8 bit)
access : read-write
Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSTR : Master/Slave Mode
bits : 0 - 0 (1 bit)
PS : Peripheral Select
bits : 1 - 1 (1 bit)
PCSDEC : Chip Select Decode
bits : 2 - 2 (1 bit)
MODFDIS : Mode Fault Detection
bits : 4 - 4 (1 bit)
WDRBT : Wait Data Read Before Transfer
bits : 5 - 5 (1 bit)
LLB : Local Loopback Enable
bits : 7 - 7 (1 bit)
PCS : Peripheral Chip Select
bits : 16 - 19 (4 bit)
DLYBCS : Delay Between Chip Selects
bits : 24 - 31 (8 bit)
Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
MSTR : Master/Slave Mode
bits : 0 - 0 (1 bit)
access : read-write
PS : Peripheral Select
bits : 1 - 1 (1 bit)
access : read-write
PCSDEC : Chip Select Decode
bits : 2 - 2 (1 bit)
access : read-write
MODFDIS : Mode Fault Detection
bits : 4 - 4 (1 bit)
access : read-write
WDRBT : Wait Data Read Before Transfer
bits : 5 - 5 (1 bit)
access : read-write
LLB : Local Loopback Enable
bits : 7 - 7 (1 bit)
access : read-write
PCS : Peripheral Chip Select
bits : 16 - 19 (4 bit)
access : read-write
DLYBCS : Delay Between Chip Selects
bits : 24 - 31 (8 bit)
access : read-write
Receive Data Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RD : Receive Data
bits : 0 - 15 (16 bit)
PCS : Peripheral Chip Select
bits : 16 - 19 (4 bit)
Receive Data Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
RD : Receive Data
bits : 0 - 15 (16 bit)
access : read-only
PCS : Peripheral Chip Select
bits : 16 - 19 (4 bit)
access : read-only
Transmit Data Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TD : Transmit Data
bits : 0 - 15 (16 bit)
PCS : Peripheral Chip Select
bits : 16 - 19 (4 bit)
LASTXFER : Last Transfer
bits : 24 - 24 (1 bit)
Transmit Data Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
TD : Transmit Data
bits : 0 - 15 (16 bit)
access : write-only
PCS : Peripheral Chip Select
bits : 16 - 19 (4 bit)
access : write-only
LASTXFER : Last Transfer
bits : 24 - 24 (1 bit)
access : write-only
Write Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)
Enumeration: WPKEYSelect
0x535049 : PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
End of enumeration elements list.
Write Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
access : read-write
WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)
access : read-write
Enumeration:
0x535049 : PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
End of enumeration elements list.
Write Protection Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WPVS : Write Protection Violation Status
bits : 0 - 0 (1 bit)
WPVSRC : Write Protection Violation Source
bits : 8 - 15 (8 bit)
Write Protection Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
WPVS : Write Protection Violation Status
bits : 0 - 0 (1 bit)
access : read-only
WPVSRC : Write Protection Violation Source
bits : 8 - 15 (8 bit)
access : read-only
Version Register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
VERSION : Version of the Hardware Module
bits : 0 - 11 (12 bit)
access : read-only
MFN : Metal Fix Number
bits : 16 - 18 (3 bit)
access : read-only
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