\n
address_offset : 0x0 Bytes (0x0)
size : 0xE8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x0 Bytes (0x0)
size : 0xE8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x0 Bytes (0x0)
size : 0xE8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x0 Bytes (0x0)
size : 0xE8 byte (0x0)
mem_usage : registers
protection :
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RSTRX : Reset Receiver
bits : 2 - 2 (1 bit)
RSTTX : Reset Transmitter
bits : 3 - 3 (1 bit)
RXEN : Receiver Enable
bits : 4 - 4 (1 bit)
RXDIS : Receiver Disable
bits : 5 - 5 (1 bit)
TXEN : Transmitter Enable
bits : 6 - 6 (1 bit)
TXDIS : Transmitter Disable
bits : 7 - 7 (1 bit)
RSTSTA : Reset Status
bits : 8 - 8 (1 bit)
REQCLR : Request Clear
bits : 12 - 12 (1 bit)
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RSTRX : Reset Receiver
bits : 2 - 2 (1 bit)
access : write-only
RSTTX : Reset Transmitter
bits : 3 - 3 (1 bit)
access : write-only
RXEN : Receiver Enable
bits : 4 - 4 (1 bit)
access : write-only
RXDIS : Receiver Disable
bits : 5 - 5 (1 bit)
access : write-only
TXEN : Transmitter Enable
bits : 6 - 6 (1 bit)
access : write-only
TXDIS : Transmitter Disable
bits : 7 - 7 (1 bit)
access : write-only
RSTSTA : Reset Status
bits : 8 - 8 (1 bit)
access : write-only
REQCLR : Request Clear
bits : 12 - 12 (1 bit)
access : write-only
DBGE : Debug Enable
bits : 15 - 15 (1 bit)
access : write-only
Interrupt Mask Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : Mask RXRDY Interrupt
bits : 0 - 0 (1 bit)
TXRDY : Disable TXRDY Interrupt
bits : 1 - 1 (1 bit)
OVRE : Mask Overrun Error Interrupt
bits : 5 - 5 (1 bit)
FRAME : Mask Framing Error Interrupt
bits : 6 - 6 (1 bit)
PARE : Mask Parity Error Interrupt
bits : 7 - 7 (1 bit)
TXEMPTY : Mask TXEMPTY Interrupt
bits : 9 - 9 (1 bit)
CMP : Mask Comparison Interrupt
bits : 15 - 15 (1 bit)
Interrupt Mask Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : Mask RXRDY Interrupt
bits : 0 - 0 (1 bit)
access : read-only
TXRDY : Disable TXRDY Interrupt
bits : 1 - 1 (1 bit)
access : read-only
OVRE : Mask Overrun Error Interrupt
bits : 5 - 5 (1 bit)
access : read-only
FRAME : Mask Framing Error Interrupt
bits : 6 - 6 (1 bit)
access : read-only
PARE : Mask Parity Error Interrupt
bits : 7 - 7 (1 bit)
access : read-only
TXEMPTY : Mask TXEMPTY Interrupt
bits : 9 - 9 (1 bit)
access : read-only
CMP : Mask Comparison Interrupt
bits : 15 - 15 (1 bit)
access : read-only
Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : Receiver Ready
bits : 0 - 0 (1 bit)
TXRDY : Transmitter Ready
bits : 1 - 1 (1 bit)
OVRE : Overrun Error
bits : 5 - 5 (1 bit)
FRAME : Framing Error
bits : 6 - 6 (1 bit)
PARE : Parity Error
bits : 7 - 7 (1 bit)
TXEMPTY : Transmitter Empty
bits : 9 - 9 (1 bit)
CMP : Comparison Match
bits : 15 - 15 (1 bit)
Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : Receiver Ready
bits : 0 - 0 (1 bit)
access : read-only
TXRDY : Transmitter Ready
bits : 1 - 1 (1 bit)
access : read-only
OVRE : Overrun Error
bits : 5 - 5 (1 bit)
access : read-only
FRAME : Framing Error
bits : 6 - 6 (1 bit)
access : read-only
PARE : Parity Error
bits : 7 - 7 (1 bit)
access : read-only
TXEMPTY : Transmitter Empty
bits : 9 - 9 (1 bit)
access : read-only
CMP : Comparison Match
bits : 15 - 15 (1 bit)
access : read-only
SWES : SleepWalking Enable Status
bits : 21 - 21 (1 bit)
access : read-only
CLKREQ : Clock Request
bits : 22 - 22 (1 bit)
access : read-only
WKUPREQ : Wake-Up Request
bits : 23 - 23 (1 bit)
access : read-only
Receive Holding Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXCHR : Received Character
bits : 0 - 7 (8 bit)
Receive Holding Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXCHR : Received Character
bits : 0 - 7 (8 bit)
access : read-only
Transmit Holding Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXCHR : Character to be Transmitted
bits : 0 - 7 (8 bit)
Transmit Holding Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXCHR : Character to be Transmitted
bits : 0 - 7 (8 bit)
access : write-only
Baud Rate Generator Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CD : Clock Divisor
bits : 0 - 15 (16 bit)
Baud Rate Generator Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CD : Clock Divisor
bits : 0 - 15 (16 bit)
access : read-write
Comparison Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL1 : First Comparison Value for Received Character
bits : 0 - 7 (8 bit)
CMPMODE : Comparison Mode
bits : 12 - 12 (1 bit)
Enumeration: CMPMODESelect
0 : FLAG_ONLY
Any character is received and comparison function drives CMP flag.
1 : START_CONDITION
Comparison condition must be met to start reception.
End of enumeration elements list.
CMPPAR : Compare Parity
bits : 14 - 14 (1 bit)
VAL2 : Second Comparison Value for Received Character
bits : 16 - 23 (8 bit)
Comparison Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL1 : First Comparison Value for Received Character
bits : 0 - 7 (8 bit)
access : read-write
CMPMODE : Comparison Mode
bits : 12 - 12 (1 bit)
access : read-write
Enumeration: CMPMODESelect
0 : FLAG_ONLY
Any character is received and comparison function drives CMP flag.
1 : START_CONDITION
Comparison condition must be met to start reception.
End of enumeration elements list.
CMPPAR : Compare Parity
bits : 14 - 14 (1 bit)
access : read-write
VAL2 : Second Comparison Value for Received Character
bits : 16 - 23 (8 bit)
access : read-write
Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FILTER : Receiver Digital Filter
bits : 4 - 4 (1 bit)
Enumeration: FILTERSelect
0 : DISABLED
UART does not filter the receive line.
1 : ENABLED
UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority).
End of enumeration elements list.
PAR : Parity Type
bits : 9 - 11 (3 bit)
Enumeration: PARSelect
0x0 : EVEN
Even Parity
0x1 : ODD
Odd Parity
0x2 : SPACE
Space: parity forced to 0
0x3 : MARK
Mark: parity forced to 1
0x4 : NO
No parity
End of enumeration elements list.
BRSRCCK : Baud Rate Source Clock
bits : 12 - 12 (1 bit)
Enumeration: BRSRCCKSelect
0 : PERIPH_CLK
The baud rate is driven by the peripheral clock
1 : PMC_PCK
The baud rate is driven by a PMC-programmable clock PCK (see section Power Management Controller (PMC)).
End of enumeration elements list.
CHMODE : Channel Mode
bits : 14 - 15 (2 bit)
Enumeration: CHMODESelect
0x0 : NORMAL
Normal mode
0x1 : AUTOMATIC
Automatic echo
0x2 : LOCAL_LOOPBACK
Local loopback
0x3 : REMOTE_LOOPBACK
Remote loopback
End of enumeration elements list.
Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FILTER : Receiver Digital Filter
bits : 4 - 4 (1 bit)
access : read-write
Enumeration: FILTERSelect
0 : DISABLED
UART does not filter the receive line.
1 : ENABLED
UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority).
End of enumeration elements list.
PAR : Parity Type
bits : 9 - 11 (3 bit)
access : read-write
Enumeration: PARSelect
0x0 : EVEN
Even Parity
0x1 : ODD
Odd Parity
0x2 : SPACE
Space: parity forced to 0
0x3 : MARK
Mark: parity forced to 1
0x4 : NO
No parity
End of enumeration elements list.
BRSRCCK : Baud Rate Source Clock
bits : 12 - 12 (1 bit)
access : read-write
Enumeration: BRSRCCKSelect
0 : PERIPH_CLK
The baud rate is driven by the peripheral clock
1 : PMC_PCK
The baud rate is driven by a PMC-programmable clock PCK (see section Power Management Controller (PMC)).
End of enumeration elements list.
CHMODE : Channel Mode
bits : 14 - 15 (2 bit)
access : read-write
Enumeration: CHMODESelect
0x0 : NORMAL
Normal mode
0x1 : AUTOMATIC
Automatic echo
0x2 : LOCAL_LOOPBACK
Local loopback
0x3 : REMOTE_LOOPBACK
Remote loopback
End of enumeration elements list.
Interrupt Enable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : Enable RXRDY Interrupt
bits : 0 - 0 (1 bit)
TXRDY : Enable TXRDY Interrupt
bits : 1 - 1 (1 bit)
OVRE : Enable Overrun Error Interrupt
bits : 5 - 5 (1 bit)
FRAME : Enable Framing Error Interrupt
bits : 6 - 6 (1 bit)
PARE : Enable Parity Error Interrupt
bits : 7 - 7 (1 bit)
TXEMPTY : Enable TXEMPTY Interrupt
bits : 9 - 9 (1 bit)
CMP : Enable Comparison Interrupt
bits : 15 - 15 (1 bit)
Interrupt Enable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : Enable RXRDY Interrupt
bits : 0 - 0 (1 bit)
access : write-only
TXRDY : Enable TXRDY Interrupt
bits : 1 - 1 (1 bit)
access : write-only
OVRE : Enable Overrun Error Interrupt
bits : 5 - 5 (1 bit)
access : write-only
FRAME : Enable Framing Error Interrupt
bits : 6 - 6 (1 bit)
access : write-only
PARE : Enable Parity Error Interrupt
bits : 7 - 7 (1 bit)
access : write-only
TXEMPTY : Enable TXEMPTY Interrupt
bits : 9 - 9 (1 bit)
access : write-only
CMP : Enable Comparison Interrupt
bits : 15 - 15 (1 bit)
access : write-only
Interrupt Disable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : Disable RXRDY Interrupt
bits : 0 - 0 (1 bit)
TXRDY : Disable TXRDY Interrupt
bits : 1 - 1 (1 bit)
OVRE : Disable Overrun Error Interrupt
bits : 5 - 5 (1 bit)
FRAME : Disable Framing Error Interrupt
bits : 6 - 6 (1 bit)
PARE : Disable Parity Error Interrupt
bits : 7 - 7 (1 bit)
TXEMPTY : Disable TXEMPTY Interrupt
bits : 9 - 9 (1 bit)
CMP : Disable Comparison Interrupt
bits : 15 - 15 (1 bit)
Interrupt Disable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : Disable RXRDY Interrupt
bits : 0 - 0 (1 bit)
access : write-only
TXRDY : Disable TXRDY Interrupt
bits : 1 - 1 (1 bit)
access : write-only
OVRE : Disable Overrun Error Interrupt
bits : 5 - 5 (1 bit)
access : write-only
FRAME : Disable Framing Error Interrupt
bits : 6 - 6 (1 bit)
access : write-only
PARE : Disable Parity Error Interrupt
bits : 7 - 7 (1 bit)
access : write-only
TXEMPTY : Disable TXEMPTY Interrupt
bits : 9 - 9 (1 bit)
access : write-only
CMP : Disable Comparison Interrupt
bits : 15 - 15 (1 bit)
access : write-only
Write Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)
Enumeration: WPKEYSelect
0x554152 : PASSWD
Writing any other value in this field aborts the write operation.Always reads as 0.
End of enumeration elements list.
Write Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
access : read-write
WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)
access : read-write
Enumeration: WPKEYSelect
0x554152 : PASSWD
Writing any other value in this field aborts the write operation.Always reads as 0.
End of enumeration elements list.
Version Register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
VERSION : Hardware Module Version
bits : 0 - 11 (12 bit)
access : read-only
MFN : Metal Fix Number
bits : 16 - 18 (3 bit)
access : read-only
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