\n
address_offset : 0x0 Bytes (0x0)
size : 0xEC byte (0x0)
mem_usage : registers
protection :
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
Channel Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CH0 : Channel 0 Enable
bits : 0 - 0 (1 bit)
CH1 : Channel 1 Enable
bits : 1 - 1 (1 bit)
Channel Disable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CH0 : Channel 0 Disable
bits : 0 - 0 (1 bit)
CH1 : Channel 1 Disable
bits : 1 - 1 (1 bit)
Channel Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH0 : Channel 0 Status
bits : 0 - 0 (1 bit)
CH1 : Channel 1 Status
bits : 1 - 1 (1 bit)
DACRDY0 : DAC Ready Flag
bits : 8 - 8 (1 bit)
DACRDY1 : DAC Ready Flag
bits : 9 - 9 (1 bit)
Conversion Data Register 0
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DATA0 : Data to Convert for channel 0
bits : 0 - 15 (16 bit)
DATA1 : Data to Convert for channel 1
bits : 16 - 31 (16 bit)
Conversion Data Register 0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DATA0 : Data to Convert for channel 0
bits : 0 - 15 (16 bit)
DATA1 : Data to Convert for channel 1
bits : 16 - 31 (16 bit)
Interrupt Enable Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXRDY0 : Transmit Ready Interrupt Enable of channel 0
bits : 0 - 0 (1 bit)
TXRDY1 : Transmit Ready Interrupt Enable of channel 1
bits : 1 - 1 (1 bit)
EOC0 : End of Conversion Interrupt Enable of channel 0
bits : 4 - 4 (1 bit)
EOC1 : End of Conversion Interrupt Enable of channel 1
bits : 5 - 5 (1 bit)
Interrupt Disable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXRDY0 : Transmit Ready Interrupt Disable of channel 0
bits : 0 - 0 (1 bit)
TXRDY1 : Transmit Ready Interrupt Disable of channel 1
bits : 1 - 1 (1 bit)
EOC0 : End of Conversion Interrupt Disable of channel 0
bits : 4 - 4 (1 bit)
EOC1 : End of Conversion Interrupt Disable of channel 1
bits : 5 - 5 (1 bit)
Interrupt Mask Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXRDY0 : Transmit Ready Interrupt Mask of channel 0
bits : 0 - 0 (1 bit)
TXRDY1 : Transmit Ready Interrupt Mask of channel 1
bits : 1 - 1 (1 bit)
EOC0 : End of Conversion Interrupt Mask of channel 0
bits : 4 - 4 (1 bit)
EOC1 : End of Conversion Interrupt Mask of channel 1
bits : 5 - 5 (1 bit)
Interrupt Status Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXRDY0 : Transmit Ready Interrupt Flag of channel 0
bits : 0 - 0 (1 bit)
TXRDY1 : Transmit Ready Interrupt Flag of channel 1
bits : 1 - 1 (1 bit)
EOC0 : End of Conversion Interrupt Flag of channel 0
bits : 4 - 4 (1 bit)
EOC1 : End of Conversion Interrupt Flag of channel 1
bits : 5 - 5 (1 bit)
Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAXS0 : Max Speed Mode for Channel 0
bits : 0 - 0 (1 bit)
Enumeration: MAXS0Select
0 : TRIG_EVENT
External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.)
1 : MAXIMUM
Max speed mode enabled.
End of enumeration elements list.
MAXS1 : Max Speed Mode for Channel 1
bits : 1 - 1 (1 bit)
Enumeration: MAXS1Select
0 : TRIG_EVENT
External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.)
1 : MAXIMUM
Max speed mode enabled.
End of enumeration elements list.
WORD : Word Transfer Mode
bits : 4 - 4 (1 bit)
Enumeration: WORDSelect
0 : DISABLED
One data to convert is written to the FIFO per access to DACC.
1 : ENABLED
Two data to convert are written to the FIFO per access to DACC (reduces the number of requests to DMA and the number of system bus accesses).
End of enumeration elements list.
ZERO : Must always be written to 0.
bits : 5 - 5 (1 bit)
DIFF : Differential Mode
bits : 23 - 23 (1 bit)
Enumeration: DIFFSelect
0 : DISABLED
DAC0 and DAC1 are single-ended outputs.
1 : ENABLED
DACP and DACN are differential outputs. The differential level is configured by the channel 0 value.
End of enumeration elements list.
PRESCALER : Peripheral Clock to DAC Clock Ratio
bits : 24 - 27 (4 bit)
Trigger Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGEN0 : Trigger Enable of Channel 0
bits : 0 - 0 (1 bit)
Enumeration: TRGEN0Select
0 : DIS
External trigger mode disabled. DACC is in Free-running mode or Max speed mode.
1 : EN
External trigger mode enabled.
End of enumeration elements list.
TRGEN1 : Trigger Enable of Channel 1
bits : 1 - 1 (1 bit)
Enumeration: TRGEN1Select
0 : DIS
External trigger mode disabled. DACC is in Free-running mode or Max speed mode.
1 : EN
External trigger mode enabled.
End of enumeration elements list.
TRGSEL0 : Trigger Selection of Channel 0
bits : 4 - 6 (3 bit)
Enumeration: TRGSEL0Select
0x0 : TRGSEL0
DAC External Trigger Input (DATRG)
0x1 : TRGSEL1
TC0 Channel 0 Output (TIOA0)
0x2 : TRGSEL2
TC0 Channel 1 Output (TIOA1)
0x3 : TRGSEL3
TC0 Channel 2 Output (TIOA2)
0x4 : TRGSEL4
PWM0 Event Line 0
0x5 : TRGSEL5
PWM0 Event Line 1
0x6 : TRGSEL6
PWM1 Event Line 0
0x7 : TRGSEL7
PWM1 Event Line 1
End of enumeration elements list.
TRGSEL1 : Trigger Selection of Channel 1
bits : 8 - 10 (3 bit)
Enumeration: TRGSEL1Select
0x0 : TRGSEL0
DAC External Trigger Input (DATRG)
0x1 : TRGSEL1
TC0 Channel 0 Output (TIOA0)
0x2 : TRGSEL2
TC0 Channel 1 Output (TIOA1)
0x3 : TRGSEL3
TC0 Channel 2 Output (TIOA2)
0x4 : TRGSEL4
PWM0 Event Line 0
0x5 : TRGSEL5
PWM0 Event Line 1
0x6 : TRGSEL6
PWM1 Event Line 0
0x7 : TRGSEL7
PWM1 Event Line 1
End of enumeration elements list.
OSR0 : Over Sampling Ratio of Channel 0
bits : 16 - 18 (3 bit)
Enumeration: OSR0Select
0x0 : OSR_1
OSR = 1
0x1 : OSR_2
OSR = 2
0x2 : OSR_4
OSR = 4
0x3 : OSR_8
OSR = 8
0x4 : OSR_16
OSR = 16
0x5 : OSR_32
OSR = 32
End of enumeration elements list.
OSR1 : Over Sampling Ratio of Channel 1
bits : 20 - 22 (3 bit)
Enumeration: OSR1Select
0x0 : OSR_1
OSR = 1
0x1 : OSR_2
OSR = 2
0x2 : OSR_4
OSR = 4
0x3 : OSR_8
OSR = 8
0x4 : OSR_16
OSR = 16
0x5 : OSR_32
OSR = 32
End of enumeration elements list.
Analog Current Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IBCTLCH0 : Analog Output Current Control
bits : 0 - 1 (2 bit)
IBCTLCH1 : Analog Output Current Control
bits : 2 - 3 (2 bit)
Write Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
WPKEY : Write Protect Key
bits : 8 - 31 (24 bit)
Enumeration: WPKEYSelect
0x444143 : PASSWD
Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0.
End of enumeration elements list.
Write Protection Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WPVS : Write Protection Violation Status
bits : 0 - 0 (1 bit)
WPVSRC : Write Protection Violation Source
bits : 8 - 15 (8 bit)
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